disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/x86/lib/delay.c
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..
@@ -27,9 +27,20 @@
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 # include <asm/smp.h>
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 #endif
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29
 
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+static void delay_loop(u64 __loops);
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+
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+/*
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+ * Calibration and selection of the delay mechanism happens only once
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+ * during boot.
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+ */
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+static void (*delay_fn)(u64) __ro_after_init = delay_loop;
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+static void (*delay_halt_fn)(u64 start, u64 cycles) __ro_after_init;
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+
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 /* simple loop based delay: */
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-static void delay_loop(unsigned long loops)
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+static void delay_loop(u64 __loops)
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 {
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+	unsigned long loops = (unsigned long)__loops;
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+
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 	asm volatile(
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 		"	test %0,%0	\n"
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 		"	jz 3f		\n"
..
..
@@ -43,15 +54,15 @@
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 		"	jnz 2b		\n"
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 		"3:	dec %0		\n"
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-		: /* we don't need output */
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-		:"a" (loops)
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+		: "+a" (loops)
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+		:
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 	);
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 }
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 /* TSC based delay: */
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-static void delay_tsc(unsigned long __loops)
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+static void delay_tsc(u64 cycles)
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 {
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-	u64 bclock, now, loops = __loops;
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+	u64 bclock, now;
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 	int cpu;
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 	preempt_disable();
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@@ -59,7 +70,7 @@
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 	bclock = rdtsc_ordered();
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 	for (;;) {
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 		now = rdtsc_ordered();
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-		if ((now - bclock) >= loops)
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+		if ((now - bclock) >= cycles)
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 			break;
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 		/* Allow RT tasks to run */
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@@ -77,7 +88,7 @@
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 		 * counter for this CPU.
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 		 */
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 		if (unlikely(cpu != smp_processor_id())) {
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-			loops -= (now - bclock);
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+			cycles -= (now - bclock);
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 			cpu = smp_processor_id();
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 			bclock = rdtsc_ordered();
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 		}
..
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@@ -86,65 +97,96 @@
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 }
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 /*
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- * On some AMD platforms, MWAITX has a configurable 32-bit timer, that
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- * counts with TSC frequency. The input value is the loop of the
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- * counter, it will exit when the timer expires.
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+ * On Intel the TPAUSE instruction waits until any of:
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+ * 1) the TSC counter exceeds the value provided in EDX:EAX
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+ * 2) global timeout in IA32_UMWAIT_CONTROL is exceeded
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+ * 3) an external interrupt occurs
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  */
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-static void delay_mwaitx(unsigned long __loops)
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+static void delay_halt_tpause(u64 start, u64 cycles)
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 {
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-	u64 start, end, delay, loops = __loops;
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+	u64 until = start + cycles;
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+	u32 eax, edx;
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+
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+	eax = lower_32_bits(until);
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+	edx = upper_32_bits(until);
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+
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+	/*
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+	 * Hard code the deeper (C0.2) sleep state because exit latency is
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+	 * small compared to the "microseconds" that usleep() will delay.
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+	 */
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+	__tpause(TPAUSE_C02_STATE, edx, eax);
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+}
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+
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+/*
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+ * On some AMD platforms, MWAITX has a configurable 32-bit timer, that
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+ * counts with TSC frequency. The input value is the number of TSC cycles
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+ * to wait. MWAITX will also exit when the timer expires.
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+ */
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+static void delay_halt_mwaitx(u64 unused, u64 cycles)
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+{
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+	u64 delay;
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+
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+	delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles);
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+	/*
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+	 * Use cpu_tss_rw as a cacheline-aligned, seldomly accessed per-cpu
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+	 * variable as the monitor target.
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+	 */
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+	 __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
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+
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+	/*
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+	 * AMD, like Intel, supports the EAX hint and EAX=0xf means, do not
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+	 * enter any deep C-state and we use it here in delay() to minimize
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+	 * wakeup latency.
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+	 */
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+	__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
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+}
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+
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+/*
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+ * Call a vendor specific function to delay for a given amount of time. Because
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+ * these functions may return earlier than requested, check for actual elapsed
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+ * time and call again until done.
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+ */
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+static void delay_halt(u64 __cycles)
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+{
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+	u64 start, end, cycles = __cycles;
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 	/*
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 	 * Timer value of 0 causes MWAITX to wait indefinitely, unless there
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 	 * is a store on the memory monitored by MONITORX.
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 	 */
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-	if (loops == 0)
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+	if (!cycles)
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 		return;
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 	start = rdtsc_ordered();
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 	for (;;) {
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-		delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
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-
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-		/*
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-		 * Use cpu_tss_rw as a cacheline-aligned, seldomly
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-		 * accessed per-cpu variable as the monitor target.
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-		 */
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-		__monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
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-
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-		/*
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-		 * AMD, like Intel's MWAIT version, supports the EAX hint and
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-		 * EAX=0xf0 means, do not enter any deep C-state and we use it
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-		 * here in delay() to minimize wakeup latency.
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-		 */
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-		__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
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-
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+		delay_halt_fn(start, cycles);
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 		end = rdtsc_ordered();
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-		if (loops <= end - start)
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+		if (cycles <= end - start)
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 			break;
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-		loops -= end - start;
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-
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+		cycles -= end - start;
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 		start = end;
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 	}
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 }
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-/*
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- * Since we calibrate only once at boot, this
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- * function should be set once at boot and not changed
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- */
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-static void (*delay_fn)(unsigned long) = delay_loop;
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-
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-void use_tsc_delay(void)
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+void __init use_tsc_delay(void)
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 {
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 	if (delay_fn == delay_loop)
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 		delay_fn = delay_tsc;
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 }
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+void __init use_tpause_delay(void)
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+{
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+	delay_halt_fn = delay_halt_tpause;
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+	delay_fn = delay_halt;
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+}
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+
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 void use_mwaitx_delay(void)
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 {
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-	delay_fn = delay_mwaitx;
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+	delay_halt_fn = delay_halt_mwaitx;
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+	delay_fn = delay_halt;
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 }
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 int read_current_timer(unsigned long *timer_val)
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@@ -162,7 +204,7 @@
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 }
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 EXPORT_SYMBOL(__delay);
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-void __const_udelay(unsigned long xloops)
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+noinline void __const_udelay(unsigned long xloops)
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 {
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 	unsigned long lpj = this_cpu_read(cpu_info.loops_per_jiffy) ? : loops_per_jiffy;
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 	int d0;