disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/x86/include/asm/segment.h
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@@ -31,6 +31,18 @@
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  */
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 #define SEGMENT_RPL_MASK	0x3
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+/*
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+ * When running on Xen PV, the actual privilege level of the kernel is 1,
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+ * not 0. Testing the Requested Privilege Level in a segment selector to
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+ * determine whether the context is user mode or kernel mode with
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+ * SEGMENT_RPL_MASK is wrong because the PV kernel's privilege level
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+ * matches the 0x3 mask.
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+ *
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+ * Testing with USER_SEGMENT_RPL_MASK is valid for both native and Xen PV
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+ * kernels because privilege level 2 is never used.
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+ */
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+#define USER_SEGMENT_RPL_MASK	0x2
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+
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 /* User mode is privilege level 3: */
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 #define USER_RPL		0x3
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@@ -210,15 +222,11 @@
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 #endif
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-#ifndef CONFIG_PARAVIRT
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-# define get_kernel_rpl()		0
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-#endif
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-
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 #define IDT_ENTRIES			256
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 #define NUM_EXCEPTION_VECTORS		32
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 /* Bitmask of exception vectors which push an error code on the stack: */
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-#define EXCEPTION_ERRCODE_MASK		0x00027d00
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+#define EXCEPTION_ERRCODE_MASK		0x20027d00
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 #define GDT_SIZE			(GDT_ENTRIES*8)
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 #define GDT_ENTRY_TLS_ENTRIES		3
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@@ -289,7 +297,7 @@
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 extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT_HANDLER_SIZE];
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 extern void early_ignore_irq(void);
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-#if defined(CONFIG_X86_64) && defined(CONFIG_XEN_PV)
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+#ifdef CONFIG_XEN_PV
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 extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_EARLY_IDT_HANDLER_SIZE];
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 #endif
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