forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/x86/include/asm/msr-index.h
....@@ -41,15 +41,26 @@
4141 
4242 /* Intel MSRs. Some also available on other CPUs */
4343 
44
+#define MSR_TEST_CTRL				0x00000033
45
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29
46
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
47
+
4448 #define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
4549 #define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
4650 #define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
4751 #define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
4852 #define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
4953 #define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
54
+#define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */
55
+#define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
56
+
57
+/* A mask for bits which the kernel toggles when controlling mitigations */
58
+#define SPEC_CTRL_MITIGATIONS_MASK	(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
59
+							| SPEC_CTRL_RRSBA_DIS_S)
5060 
5161 #define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
5262 #define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
63
+#define PRED_CMD_SBPB			BIT(7)	   /* Selective Branch Prediction Barrier */
5364 
5465 #define MSR_PPIN_CTL			0x0000004e
5566 #define MSR_PPIN			0x0000004f
....@@ -60,6 +71,20 @@
6071 #define MSR_PLATFORM_INFO		0x000000ce
6172 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
6273 #define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
74
+
75
+#define MSR_IA32_UMWAIT_CONTROL			0xe1
76
+#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)
77
+#define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)
78
+/*
79
+ * The time field is bit[31:2], but representing a 32bit value with
80
+ * bit[1:0] zero.
81
+ */
82
+#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)
83
+
84
+/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
85
+#define MSR_IA32_CORE_CAPS			  0x000000cf
86
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
87
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
6388 
6489 #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
6590 #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
....@@ -73,6 +98,7 @@
7398 #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
7499 #define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */
75100 #define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */
101
+#define ARCH_CAP_RSBA			BIT(2)	/* RET may use alternative branch predictors */
76102 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */
77103 #define ARCH_CAP_SSB_NO			BIT(4)	/*
78104 						 * Not susceptible to Speculative Store Bypass
....@@ -96,6 +122,50 @@
96122 						 * Not susceptible to
97123 						 * TSX Async Abort (TAA) vulnerabilities.
98124 						 */
125
+#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
126
+						 * Not susceptible to SBDR and SSDP
127
+						 * variants of Processor MMIO stale data
128
+						 * vulnerabilities.
129
+						 */
130
+#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
131
+						 * Not susceptible to FBSDP variant of
132
+						 * Processor MMIO stale data
133
+						 * vulnerabilities.
134
+						 */
135
+#define ARCH_CAP_PSDP_NO		BIT(15)	/*
136
+						 * Not susceptible to PSDP variant of
137
+						 * Processor MMIO stale data
138
+						 * vulnerabilities.
139
+						 */
140
+#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
141
+						 * VERW clears CPU fill buffer
142
+						 * even on MDS_NO CPUs.
143
+						 */
144
+#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
145
+						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
146
+						 * bit available to control VERW
147
+						 * behavior.
148
+						 */
149
+#define ARCH_CAP_RRSBA			BIT(19)	/*
150
+						 * Indicates RET may use predictors
151
+						 * other than the RSB. With eIBRS
152
+						 * enabled predictions in kernel mode
153
+						 * are restricted to targets in
154
+						 * kernel.
155
+						 */
156
+#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
157
+						 * Not susceptible to Post-Barrier
158
+						 * Return Stack Buffer Predictions.
159
+						 */
160
+#define ARCH_CAP_GDS_CTRL		BIT(25)	/*
161
+						 * CPU is vulnerable to Gather
162
+						 * Data Sampling (GDS) and
163
+						 * has controls for mitigation.
164
+						 */
165
+#define ARCH_CAP_GDS_NO			BIT(26)	/*
166
+						 * CPU is not vulnerable to Gather
167
+						 * Data Sampling (GDS).
168
+						 */
99169 
100170 #define MSR_IA32_FLUSH_CMD		0x0000010b
101171 #define L1D_FLUSH			BIT(0)	/*
....@@ -113,6 +183,9 @@
113183 /* SRBDS support */
114184 #define MSR_IA32_MCU_OPT_CTRL		0x00000123
115185 #define RNGDS_MITG_DIS			BIT(0)
186
+#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
187
+#define GDS_MITG_DIS			BIT(4)	/* Disable GDS mitigation */
188
+#define GDS_MITG_LOCKED			BIT(5)	/* GDS mitigation locked */
116189 
117190 #define MSR_IA32_SYSENTER_CS		0x00000174
118191 #define MSR_IA32_SYSENTER_ESP		0x00000175
....@@ -131,6 +204,10 @@
131204 
132205 #define MSR_LBR_SELECT			0x000001c8
133206 #define MSR_LBR_TOS			0x000001c9
207
+
208
+#define MSR_IA32_POWER_CTL		0x000001fc
209
+#define MSR_IA32_POWER_CTL_BIT_EE	19
210
+
134211 #define MSR_LBR_NHM_FROM		0x00000680
135212 #define MSR_LBR_NHM_TO			0x000006c0
136213 #define MSR_LBR_CORE_FROM		0x00000040
....@@ -140,15 +217,68 @@
140217 #define LBR_INFO_MISPRED		BIT_ULL(63)
141218 #define LBR_INFO_IN_TX			BIT_ULL(62)
142219 #define LBR_INFO_ABORT			BIT_ULL(61)
220
+#define LBR_INFO_CYC_CNT_VALID		BIT_ULL(60)
143221 #define LBR_INFO_CYCLES			0xffff
222
+#define LBR_INFO_BR_TYPE_OFFSET		56
223
+#define LBR_INFO_BR_TYPE		(0xfull << LBR_INFO_BR_TYPE_OFFSET)
224
+
225
+#define MSR_ARCH_LBR_CTL		0x000014ce
226
+#define ARCH_LBR_CTL_LBREN		BIT(0)
227
+#define ARCH_LBR_CTL_CPL_OFFSET		1
228
+#define ARCH_LBR_CTL_CPL		(0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
229
+#define ARCH_LBR_CTL_STACK_OFFSET	3
230
+#define ARCH_LBR_CTL_STACK		(0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
231
+#define ARCH_LBR_CTL_FILTER_OFFSET	16
232
+#define ARCH_LBR_CTL_FILTER		(0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
233
+#define MSR_ARCH_LBR_DEPTH		0x000014cf
234
+#define MSR_ARCH_LBR_FROM_0		0x00001500
235
+#define MSR_ARCH_LBR_TO_0		0x00001600
236
+#define MSR_ARCH_LBR_INFO_0		0x00001200
144237 
145238 #define MSR_IA32_PEBS_ENABLE		0x000003f1
239
+#define MSR_PEBS_DATA_CFG		0x000003f2
146240 #define MSR_IA32_DS_AREA		0x00000600
147241 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
148242 #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
149243 
150244 #define MSR_IA32_RTIT_CTL		0x00000570
245
+#define RTIT_CTL_TRACEEN		BIT(0)
246
+#define RTIT_CTL_CYCLEACC		BIT(1)
247
+#define RTIT_CTL_OS			BIT(2)
248
+#define RTIT_CTL_USR			BIT(3)
249
+#define RTIT_CTL_PWR_EVT_EN		BIT(4)
250
+#define RTIT_CTL_FUP_ON_PTW		BIT(5)
251
+#define RTIT_CTL_FABRIC_EN		BIT(6)
252
+#define RTIT_CTL_CR3EN			BIT(7)
253
+#define RTIT_CTL_TOPA			BIT(8)
254
+#define RTIT_CTL_MTC_EN			BIT(9)
255
+#define RTIT_CTL_TSC_EN			BIT(10)
256
+#define RTIT_CTL_DISRETC		BIT(11)
257
+#define RTIT_CTL_PTW_EN			BIT(12)
258
+#define RTIT_CTL_BRANCH_EN		BIT(13)
259
+#define RTIT_CTL_MTC_RANGE_OFFSET	14
260
+#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
261
+#define RTIT_CTL_CYC_THRESH_OFFSET	19
262
+#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
263
+#define RTIT_CTL_PSB_FREQ_OFFSET	24
264
+#define RTIT_CTL_PSB_FREQ		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
265
+#define RTIT_CTL_ADDR0_OFFSET		32
266
+#define RTIT_CTL_ADDR0			(0x0full << RTIT_CTL_ADDR0_OFFSET)
267
+#define RTIT_CTL_ADDR1_OFFSET		36
268
+#define RTIT_CTL_ADDR1			(0x0full << RTIT_CTL_ADDR1_OFFSET)
269
+#define RTIT_CTL_ADDR2_OFFSET		40
270
+#define RTIT_CTL_ADDR2			(0x0full << RTIT_CTL_ADDR2_OFFSET)
271
+#define RTIT_CTL_ADDR3_OFFSET		44
272
+#define RTIT_CTL_ADDR3			(0x0full << RTIT_CTL_ADDR3_OFFSET)
151273 #define MSR_IA32_RTIT_STATUS		0x00000571
274
+#define RTIT_STATUS_FILTEREN		BIT(0)
275
+#define RTIT_STATUS_CONTEXTEN		BIT(1)
276
+#define RTIT_STATUS_TRIGGEREN		BIT(2)
277
+#define RTIT_STATUS_BUFFOVF		BIT(3)
278
+#define RTIT_STATUS_ERROR		BIT(4)
279
+#define RTIT_STATUS_STOPPED		BIT(5)
280
+#define RTIT_STATUS_BYTECNT_OFFSET	32
281
+#define RTIT_STATUS_BYTECNT		(0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
152282 #define MSR_IA32_RTIT_ADDR0_A		0x00000580
153283 #define MSR_IA32_RTIT_ADDR0_B		0x00000581
154284 #define MSR_IA32_RTIT_ADDR1_A		0x00000582
....@@ -182,6 +312,9 @@
182312 #define MSR_IA32_LASTINTFROMIP		0x000001dd
183313 #define MSR_IA32_LASTINTTOIP		0x000001de
184314 
315
+#define MSR_IA32_PASID			0x00000d93
316
+#define MSR_IA32_PASID_VALID		BIT_ULL(31)
317
+
185318 /* DEBUGCTLMSR bits (others vary by model): */
186319 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
187320 #define DEBUGCTLMSR_BTF_SHIFT		1
....@@ -192,12 +325,11 @@
192325 #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
193326 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
194327 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
328
+#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI	(1UL << 12)
195329 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT	14
196330 #define DEBUGCTLMSR_FREEZE_IN_SMM	(1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
197331 
198332 #define MSR_PEBS_FRONTEND		0x000003f7
199
-
200
-#define MSR_IA32_POWER_CTL		0x000001fc
201333 
202334 #define MSR_IA32_MC0_CTL		0x00000400
203335 #define MSR_IA32_MC0_STATUS		0x00000401
....@@ -248,6 +380,9 @@
248380 #define MSR_PP1_POWER_LIMIT		0x00000640
249381 #define MSR_PP1_ENERGY_STATUS		0x00000641
250382 #define MSR_PP1_POLICY			0x00000642
383
+
384
+#define MSR_AMD_PKG_ENERGY_STATUS	0xc001029b
385
+#define MSR_AMD_RAPL_POWER_UNIT		0xc0010299
251386 
252387 /* Config TDP MSRs */
253388 #define MSR_CONFIG_TDP_NOMINAL		0x00000648
....@@ -348,18 +483,34 @@
348483 /* Alternative perfctr range with full access. */
349484 #define MSR_IA32_PMC0			0x000004c1
350485 
351
-/* AMD64 MSRs. Not complete. See the architecture manual for a more
352
-   complete list. */
486
+/* Auto-reload via MSR instead of DS area */
487
+#define MSR_RELOAD_PMC0			0x000014c1
488
+#define MSR_RELOAD_FIXED_CTR0		0x00001309
353489 
490
+/*
491
+ * AMD64 MSRs. Not complete. See the architecture manual for a more
492
+ * complete list.
493
+ */
354494 #define MSR_AMD64_PATCH_LEVEL		0x0000008b
355495 #define MSR_AMD64_TSC_RATIO		0xc0000104
356496 #define MSR_AMD64_NB_CFG		0xc001001f
357
-#define MSR_AMD64_CPUID_FN_1		0xc0011004
358497 #define MSR_AMD64_PATCH_LOADER		0xc0010020
498
+#define MSR_AMD_PERF_CTL		0xc0010062
499
+#define MSR_AMD_PERF_STATUS		0xc0010063
500
+#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
359501 #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
360502 #define MSR_AMD64_OSVW_STATUS		0xc0010141
503
+#define MSR_AMD_PPIN_CTL		0xc00102f0
504
+#define MSR_AMD_PPIN			0xc00102f1
505
+#define MSR_AMD64_CPUID_FN_1		0xc0011004
361506 #define MSR_AMD64_LS_CFG		0xc0011020
362507 #define MSR_AMD64_DC_CFG		0xc0011022
508
+
509
+#define MSR_AMD64_DE_CFG		0xc0011029
510
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1
511
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
512
+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
513
+
363514 #define MSR_AMD64_BU_CFG2		0xc001102a
364515 #define MSR_AMD64_IBSFETCHCTL		0xc0011030
365516 #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
....@@ -380,14 +531,21 @@
380531 #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
381532 #define MSR_AMD64_IBSOPDATA4		0xc001103d
382533 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
534
+#define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e
535
+#define MSR_AMD64_SEV_ES_GHCB		0xc0010130
383536 #define MSR_AMD64_SEV			0xc0010131
384537 #define MSR_AMD64_SEV_ENABLED_BIT	0
538
+#define MSR_AMD64_SEV_ES_ENABLED_BIT	1
385539 #define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
540
+#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
386541 
387542 #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
388543 
389544 /* Fam 17h MSRs */
390545 #define MSR_F17H_IRPERF			0xc00000e9
546
+
547
+#define MSR_ZEN2_SPECTRAL_CHICKEN	0xc00110e3
548
+#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT	BIT_ULL(1)
391549 
392550 /* Fam 16h MSRs */
393551 #define MSR_F16H_L2I_PERF_CTL		0xc0010230
....@@ -398,6 +556,8 @@
398556 #define MSR_F16H_DR0_ADDR_MASK		0xc0011027
399557 
400558 /* Fam 15h MSRs */
559
+#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
560
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
401561 #define MSR_F15H_PERF_CTL		0xc0010200
402562 #define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
403563 #define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
....@@ -428,9 +588,6 @@
428588 #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
429589 #define FAM10H_MMIO_CONF_BASE_SHIFT	20
430590 #define MSR_FAM10H_NODE_ID		0xc001100c
431
-#define MSR_F10H_DECFG			0xc0011029
432
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
433
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE		BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
434591 
435592 /* K8 MSRs */
436593 #define MSR_K8_TOP_MEM1			0xc001001a
....@@ -508,18 +665,20 @@
508665 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
509666 #define MSR_EBC_FREQUENCY_ID		0x0000002c
510667 #define MSR_SMI_COUNT			0x00000034
511
-#define MSR_IA32_FEATURE_CONTROL        0x0000003a
668
+
669
+/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
670
+#define MSR_IA32_FEAT_CTL		0x0000003a
671
+#define FEAT_CTL_LOCKED				BIT(0)
672
+#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX		BIT(1)
673
+#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX	BIT(2)
674
+#define FEAT_CTL_LMCE_ENABLED			BIT(20)
675
+
512676 #define MSR_IA32_TSC_ADJUST             0x0000003b
513677 #define MSR_IA32_BNDCFGS		0x00000d90
514678 
515679 #define MSR_IA32_BNDCFGS_RSVD		0x00000ffc
516680 
517681 #define MSR_IA32_XSS			0x00000da0
518
-
519
-#define FEATURE_CONTROL_LOCKED				(1<<0)
520
-#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
521
-#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
522
-#define FEATURE_CONTROL_LMCE				(1<<20)
523682 
524683 #define MSR_IA32_APICBASE		0x0000001b
525684 #define MSR_IA32_APICBASE_BSP		(1<<8)
....@@ -537,9 +696,6 @@
537696 #define MSR_IA32_PERF_STATUS		0x00000198
538697 #define MSR_IA32_PERF_CTL		0x00000199
539698 #define INTEL_PERF_CTL_MASK		0xffff
540
-#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
541
-#define MSR_AMD_PERF_STATUS		0xc0010063
542
-#define MSR_AMD_PERF_CTL		0xc0010062
543699 
544700 #define MSR_IA32_MPERF			0x000000e7
545701 #define MSR_IA32_APERF			0x000000e8
....@@ -770,10 +926,21 @@
770926 #define MSR_CORE_PERF_FIXED_CTR0	0x00000309
771927 #define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
772928 #define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
929
+#define MSR_CORE_PERF_FIXED_CTR3	0x0000030c
773930 #define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
774931 #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
775932 #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
776933 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
934
+
935
+#define MSR_PERF_METRICS		0x00000329
936
+
937
+/* PERF_GLOBAL_OVF_CTL bits */
938
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
939
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
940
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT		62
941
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF			(1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
942
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT		63
943
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD			(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
777944 
778945 /* Geode defined MSRs */
779946 #define MSR_GEODE_BUSCONT_CONF0		0x00001900
....@@ -808,6 +975,7 @@
808975 #define VMX_BASIC_INOUT		0x0040000000000000LLU
809976 
810977 /* MSR_IA32_VMX_MISC bits */
978
+#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
811979 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
812980 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
813981 /* AMD-V MSRs */