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| 3 | 3 | * Copyright (C) 2020 SiFive |
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| 4 | 4 | */ |
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| 5 | 5 | |
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| 6 | +#ifndef _ASM_RISCV_INSN_H |
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| 7 | +#define _ASM_RISCV_INSN_H |
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| 8 | + |
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| 6 | 9 | #include <linux/bits.h> |
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| 7 | 10 | |
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| 8 | 11 | /* The bit field of immediate value in I-type instruction */ |
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| .. | .. |
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| 125 | 128 | #define FUNCT3_C_J 0xa000 |
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| 126 | 129 | #define FUNCT3_C_JAL 0x2000 |
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| 127 | 130 | #define FUNCT4_C_JR 0x8000 |
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| 128 | | -#define FUNCT4_C_JALR 0xf000 |
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| 131 | +#define FUNCT4_C_JALR 0x9000 |
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| 129 | 132 | |
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| 130 | 133 | #define FUNCT12_SRET 0x10200000 |
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| 131 | 134 | |
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| .. | .. |
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| 217 | 220 | (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \ |
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| 218 | 221 | (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ |
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| 219 | 222 | (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) |
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| 223 | + |
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| 224 | +#endif /* _ASM_RISCV_INSN_H */ |
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