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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/powerpc/sysdev/dart_iommu.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * arch/powerpc/sysdev/dart_iommu.c
34  *
....@@ -10,21 +11,6 @@
1011  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
1112  *
1213  * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
13
- *
14
- *
15
- * This program is free software; you can redistribute it and/or modify
16
- * it under the terms of the GNU General Public License as published by
17
- * the Free Software Foundation; either version 2 of the License, or
18
- * (at your option) any later version.
19
- *
20
- * This program is distributed in the hope that it will be useful,
21
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
22
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
- * GNU General Public License for more details.
24
- *
25
- * You should have received a copy of the GNU General Public License
26
- * along with this program; if not, write to the Free Software
27
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
2814  */
2915 
3016 #include <linux/init.h>
....@@ -158,7 +144,7 @@
158144 	unsigned int tmp;
159145 
160146 	/* Perform a standard cache flush */
161
-	flush_inval_dcache_range(start, end);
147
+	flush_dcache_range(start, end);
162148 
163149 	/*
164150 	 * Perform the sequence described in the CPC925 manual to
....@@ -251,8 +237,11 @@
251237 	 * 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
252238 	 * will blow up an entire large page anyway in the kernel mapping.
253239 	 */
254
-	dart_tablebase = __va(memblock_alloc_base(1UL<<24,
255
-						  1UL<<24, 0x80000000L));
240
+	dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M,
241
+					MEMBLOCK_LOW_LIMIT, SZ_2G,
242
+					NUMA_NO_NODE);
243
+	if (!dart_tablebase)
244
+		panic("Failed to allocate 16MB below 2GB for DART table\n");
256245 
257246 	/* There is no point scanning the DART space for leaks*/
258247 	kmemleak_no_scan((void *)dart_tablebase);
....@@ -261,7 +250,10 @@
261250 	 * that to work around what looks like a problem with the HT bridge
262251 	 * prefetching into invalid pages and corrupting data
263252 	 */
264
-	tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
253
+	tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
254
+	if (!tmp)
255
+		panic("DART: table allocation failed\n");
256
+
265257 	dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
266258 					 DARTMAP_RPNMASK);
267259 
....@@ -352,19 +344,12 @@
352344 	iommu_table_dart.it_index = 0;
353345 	iommu_table_dart.it_blocksize = 1;
354346 	iommu_table_dart.it_ops = &iommu_dart_ops;
355
-	iommu_init_table(&iommu_table_dart, -1);
347
+	iommu_init_table(&iommu_table_dart, -1, 0, 0);
356348 
357349 	/* Reserve the last page of the DART to avoid possible prefetch
358350 	 * past the DART mapped area
359351 	 */
360352 	set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
361
-}
362
-
363
-static void pci_dma_dev_setup_dart(struct pci_dev *dev)
364
-{
365
-	if (dart_is_u4)
366
-		set_dma_offset(&dev->dev, DART_U4_BYPASS_BASE);
367
-	set_iommu_table_base(&dev->dev, &iommu_table_dart);
368353 }
369354 
370355 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
....@@ -390,27 +375,18 @@
390375 	return false;
391376 }
392377 
393
-static int dart_dma_set_mask(struct device *dev, u64 dma_mask)
378
+static void pci_dma_dev_setup_dart(struct pci_dev *dev)
394379 {
395
-	if (!dev->dma_mask || !dma_supported(dev, dma_mask))
396
-		return -EIO;
380
+	if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
381
+		dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
382
+	set_iommu_table_base(&dev->dev, &iommu_table_dart);
383
+}
397384 
398
-	/* U4 supports a DART bypass, we use it for 64-bit capable
399
-	 * devices to improve performances. However, that only works
400
-	 * for devices connected to U4 own PCIe interface, not bridged
401
-	 * through hypertransport. We need the device to support at
402
-	 * least 40 bits of addresses.
403
-	 */
404
-	if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) {
405
-		dev_info(dev, "Using 64-bit DMA iommu bypass\n");
406
-		set_dma_ops(dev, &dma_nommu_ops);
407
-	} else {
408
-		dev_info(dev, "Using 32-bit DMA via iommu\n");
409
-		set_dma_ops(dev, &dma_iommu_ops);
410
-	}
411
-
412
-	*dev->dma_mask = dma_mask;
413
-	return 0;
385
+static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask)
386
+{
387
+	return dart_is_u4 &&
388
+		dart_device_on_pcie(&dev->dev) &&
389
+		mask >= DMA_BIT_MASK(40);
414390 }
415391 
416392 void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
....@@ -427,27 +403,23 @@
427403 	}
428404 
429405 	/* Initialize the DART HW */
430
-	if (dart_init(dn) != 0)
431
-		goto bail;
432
-
433
-	/* Setup bypass if supported */
434
-	if (dart_is_u4)
435
-		ppc_md.dma_set_mask = dart_dma_set_mask;
436
-
406
+	if (dart_init(dn) != 0) {
407
+		of_node_put(dn);
408
+		return;
409
+	}
410
+	/*
411
+	 * U4 supports a DART bypass, we use it for 64-bit capable devices to
412
+	 * improve performance.  However, that only works for devices connected
413
+	 * to the U4 own PCIe interface, not bridged through hypertransport.
414
+	 * We need the device to support at least 40 bits of addresses.
415
+	 */
437416 	controller_ops->dma_dev_setup = pci_dma_dev_setup_dart;
438417 	controller_ops->dma_bus_setup = pci_dma_bus_setup_dart;
418
+	controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart;
439419 
440420 	/* Setup pci_dma ops */
441421 	set_pci_dma_ops(&dma_iommu_ops);
442
-	return;
443
-
444
- bail:
445
-	/* If init failed, use direct iommu and null setup functions */
446
-	controller_ops->dma_dev_setup = NULL;
447
-	controller_ops->dma_bus_setup = NULL;
448
-
449
-	/* Setup pci_dma ops */
450
-	set_pci_dma_ops(&dma_nommu_ops);
422
+	of_node_put(dn);
451423 }
452424 
453425 #ifdef CONFIG_PM