disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/powerpc/platforms/8xx/Kconfig
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@@ -98,15 +98,6 @@
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 # 8xx specific questions.
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 comment "Generic MPC8xx Options"
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-config 8xx_COPYBACK
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-	bool "Copy-Back Data Cache (else Writethrough)"
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-	help
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-	  Saying Y here will cause the cache on an MPC8xx processor to be used
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-	  in Copy-Back mode.  If you say N here, it is used in Writethrough
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-	  mode.
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-
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-	  If in doubt, say Y here.
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-
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 config 8xx_GPIO
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 	bool "GPIO API Support"
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 	select GPIOLIB
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@@ -157,6 +148,13 @@
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 	help
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 	  Help not implemented yet, coming soon.
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+config SMC_UCODE_PATCH
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+	bool "SMC relocation patch"
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+	help
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+	  This microcode relocates SMC1 and SMC2 parameter RAMs at
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+	  offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM
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+	  for SCC3 and SCC4.
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+
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 endchoice
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 config UCODE_PATCH
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@@ -164,4 +162,45 @@
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 	default y
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 	depends on !NO_UCODE_PATCH
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+menu "8xx advanced setup"
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+	depends on PPC_8xx
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+
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+config PIN_TLB
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+	bool "Pinned Kernel TLBs"
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+	depends on ADVANCED_OPTIONS
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+	help
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+	  On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
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+	  table 4 TLBs can be pinned.
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+
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+	  It reduces the amount of usable TLBs to 28 (ie by 12%). That's the
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+	  reason why we make it selectable.
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+
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+	  This option does nothing, it just activate the selection of what
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+	  to pin.
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+
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+config PIN_TLB_DATA
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+	bool "Pinned TLB for DATA"
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+	depends on PIN_TLB
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+	default y
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+	help
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+	  This pins the first 32 Mbytes of memory with 8M pages.
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+
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+config PIN_TLB_IMMR
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+	bool "Pinned TLB for IMMR"
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+	depends on PIN_TLB
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+	default y
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+	help
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+	  This pins the IMMR area with a 512kbytes page. In case
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+	  CONFIG_PIN_TLB_DATA is also selected, it will reduce
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+	  CONFIG_PIN_TLB_DATA to 24 Mbytes.
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+
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+config PIN_TLB_TEXT
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+	bool "Pinned TLB for TEXT"
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+	depends on PIN_TLB
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+	default y
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+	help
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+	  This pins kernel text with 8M pages.
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+
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+endmenu
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+
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 endmenu