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hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/powerpc/include/asm/reg.h
....@@ -12,6 +12,7 @@
1212 #ifdef __KERNEL__
1313 
1414 #include <linux/stringify.h>
15
+#include <linux/const.h>
1516 #include <asm/cputable.h>
1617 #include <asm/asm-const.h>
1718 #include <asm/feature-fixups.h>
....@@ -25,9 +26,7 @@
2526 #include <asm/reg_fsl_emb.h>
2627 #endif
2728 
28
-#ifdef CONFIG_PPC_8xx
2929 #include <asm/reg_8xx.h>
30
-#endif /* CONFIG_PPC_8xx */
3130 
3231 #define MSR_SF_LG	63              /* Enable 64 bit mode */
3332 #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
....@@ -38,6 +37,7 @@
3837 #define MSR_TM_LG	32		/* Trans Mem Available */
3938 #define MSR_VEC_LG	25	        /* Enable AltiVec */
4039 #define MSR_VSX_LG	23		/* Enable VSX */
40
+#define MSR_S_LG	22		/* Secure state */
4141 #define MSR_POW_LG	18		/* Enable Power Management */
4242 #define MSR_WE_LG	18		/* Wait State Enable */
4343 #define MSR_TGPR_LG	17		/* TLB Update registers in use */
....@@ -71,11 +71,13 @@
7171 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
7272 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
7373 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
74
+#define MSR_S		__MASK(MSR_S_LG)	/* Secure state */
7475 #else
7576 /* so tests for these bits fail on 32-bit */
7677 #define MSR_SF		0
7778 #define MSR_ISF		0
7879 #define MSR_HV		0
80
+#define MSR_S		0
7981 #endif
8082 
8183 /*
....@@ -168,6 +170,7 @@
168170 #define PSSCR_ESL		0x00200000 /* Enable State Loss */
169171 #define PSSCR_SD		0x00400000 /* Status Disable */
170172 #define PSSCR_PLS	0xf000000000000000 /* Power-saving Level Status */
173
+#define PSSCR_PLS_SHIFT	60
171174 #define PSSCR_GUEST_VIS	0xf0000000000003ffUL /* Guest-visible PSSCR fields */
172175 #define PSSCR_FAKE_SUSPEND	0x00000400 /* Fake-suspend bit (P9 DD2.2) */
173176 #define PSSCR_FAKE_SUSPEND_LG	10	   /* Fake-suspend bit position */
....@@ -281,14 +284,16 @@
281284 #define   CTRL_CT1	0x40000000	/* thread 1 */
282285 #define   CTRL_TE	0x00c00000	/* thread enable */
283286 #define   CTRL_RUNLATCH	0x1
284
-#define SPRN_DAWR	0xB4
287
+#define SPRN_DAWR0	0xB4
288
+#define SPRN_DAWR1	0xB5
285289 #define SPRN_RPR	0xBA	/* Relative Priority Register */
286290 #define SPRN_CIABR	0xBB
287291 #define   CIABR_PRIV		0x3
288292 #define   CIABR_PRIV_USER	1
289293 #define   CIABR_PRIV_SUPER	2
290294 #define   CIABR_PRIV_HYPER	3
291
-#define SPRN_DAWRX	0xBC
295
+#define SPRN_DAWRX0	0xBC
296
+#define SPRN_DAWRX1	0xBD
292297 #define   DAWRX_USER	__MASK(0)
293298 #define   DAWRX_KERNEL	__MASK(1)
294299 #define   DAWRX_HYP	__MASK(2)
....@@ -395,6 +400,7 @@
395400 #define SPRN_RWMR	0x375	/* Region-Weighting Mode Register */
396401 
397402 /* HFSCR and FSCR bit numbers are the same */
403
+#define FSCR_PREFIX_LG	13	/* Enable Prefix Instructions */
398404 #define FSCR_SCV_LG	12	/* Enable System Call Vectored */
399405 #define FSCR_MSGP_LG	10	/* Enable MSGP */
400406 #define FSCR_TAR_LG	8	/* Enable Target Address Register */
....@@ -406,11 +412,13 @@
406412 #define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
407413 #define FSCR_FP_LG	0	/* Enable Floating Point */
408414 #define SPRN_FSCR	0x099	/* Facility Status & Control Register */
415
+#define   FSCR_PREFIX	__MASK(FSCR_PREFIX_LG)
409416 #define   FSCR_SCV	__MASK(FSCR_SCV_LG)
410417 #define   FSCR_TAR	__MASK(FSCR_TAR_LG)
411418 #define   FSCR_EBB	__MASK(FSCR_EBB_LG)
412419 #define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)
413420 #define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */
421
+#define   HFSCR_PREFIX	__MASK(FSCR_PREFIX_LG)
414422 #define   HFSCR_MSGP	__MASK(FSCR_MSGP_LG)
415423 #define   HFSCR_TAR	__MASK(FSCR_TAR_LG)
416424 #define   HFSCR_EBB	__MASK(FSCR_EBB_LG)
....@@ -420,6 +428,7 @@
420428 #define   HFSCR_DSCR	__MASK(FSCR_DSCR_LG)
421429 #define   HFSCR_VECVSX	__MASK(FSCR_VECVSX_LG)
422430 #define   HFSCR_FP	__MASK(FSCR_FP_LG)
431
+#define   HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56)	/* interrupt cause */
423432 #define SPRN_TAR	0x32f	/* Target Address Register */
424433 #define SPRN_LPCR	0x13E	/* LPAR Control Register */
425434 #define   LPCR_VPM0		ASM_CONST(0x8000000000000000)
....@@ -435,6 +444,7 @@
435444 #define   LPCR_VRMA_LP1		ASM_CONST(0x0000800000000000)
436445 #define   LPCR_RMLS		0x1C000000	/* Implementation dependent RMO limit sel */
437446 #define   LPCR_RMLS_SH		26
447
+#define   LPCR_HAIL		ASM_CONST(0x0000000004000000)   /* HV AIL (ISAv3.1) */
438448 #define   LPCR_ILE		ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
439449 #define   LPCR_AIL		ASM_CONST(0x0000000001800000)	/* Alternate interrupt location */
440450 #define   LPCR_AIL_0		ASM_CONST(0x0000000000000000)	/* MMU off exception offset 0x0 */
....@@ -465,22 +475,28 @@
465475 #ifndef SPRN_LPID
466476 #define SPRN_LPID	0x13F	/* Logical Partition Identifier */
467477 #endif
468
-#define   LPID_RSVD	0x3ff		/* Reserved LPID for partn switching */
478
+#define   LPID_RSVD_POWER7	0x3ff	/* Reserved LPID for partn switching */
479
+#define   LPID_RSVD		0xfff	/* Reserved LPID for partn switching */
469480 #define	SPRN_HMER	0x150	/* Hypervisor maintenance exception reg */
470481 #define   HMER_DEBUG_TRIG	(1ul << (63 - 17)) /* Debug trigger */
471482 #define	SPRN_HMEER	0x151	/* Hyp maintenance exception enable reg */
472483 #define SPRN_PCR	0x152	/* Processor compatibility register */
473
-#define   PCR_VEC_DIS	(1ul << (63-0))	/* Vec. disable (bit NA since POWER8) */
474
-#define   PCR_VSX_DIS	(1ul << (63-1))	/* VSX disable (bit NA since POWER8) */
475
-#define   PCR_TM_DIS	(1ul << (63-2))	/* Trans. memory disable (POWER8) */
484
+#define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since POWER8) */
485
+#define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA since POWER8) */
486
+#define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory disable (POWER8) */
487
+#define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */
488
+#define   PCR_HIGH_BITS	(PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
476489 /*
477490  * These bits are used in the function kvmppc_set_arch_compat() to specify and
478491  * determine both the compatibility level which we want to emulate and the
479492  * compatibility level which the host is capable of emulating.
480493  */
494
+#define   PCR_ARCH_300	0x10		/* Architecture 3.00 */
481495 #define   PCR_ARCH_207	0x8		/* Architecture 2.07 */
482496 #define   PCR_ARCH_206	0x4		/* Architecture 2.06 */
483497 #define   PCR_ARCH_205	0x2		/* Architecture 2.05 */
498
+#define   PCR_LOW_BITS	(PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
499
+#define   PCR_MASK	~(PCR_HIGH_BITS | PCR_LOW_BITS)	/* PCR Reserved Bits */
484500 #define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
485501 #define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */
486502 #define SPRN_TLBVPNR	0x155	/* P7 TLB control register */
....@@ -506,6 +522,8 @@
506522 #define SPRN_TSCR	0x399	/* Thread Switch Control Register */
507523 
508524 #define SPRN_DEC	0x016		/* Decrement Register */
525
+#define SPRN_PIT	0x3DB		/* Programmable Interval Timer (40x/BOOKE) */
526
+
509527 #define SPRN_DER	0x095		/* Debug Enable Register */
510528 #define DER_RSTE	0x40000000	/* Reset Interrupt */
511529 #define DER_CHSTPE	0x20000000	/* Check Stop */
....@@ -581,7 +599,7 @@
581599 #define HID0_POWER9_RADIX	__MASK(63 - 8)
582600 
583601 #define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
584
-#ifdef CONFIG_6xx
602
+#ifdef CONFIG_PPC_BOOK3S_32
585603 #define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
586604 #define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
587605 #define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
....@@ -740,8 +758,20 @@
740758 #define SPRN_USPRG7	0x107	/* SPRG7 userspace read */
741759 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
742760 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
761
+
762
+#ifdef CONFIG_PPC_BOOK3S
763
+/*
764
+ * Bits loaded from MSR upon interrupt.
765
+ * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
766
+ * loaded from MSR. The exception is that SRESET and MCE do not always load
767
+ * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
768
+ * it.
769
+ */
770
+#define   SRR1_MSR_BITS		(~0x783f0000UL)
771
+#endif
772
+
743773 #define   SRR1_ISI_NOPT		0x40000000 /* ISI: Not found in hash */
744
-#define   SRR1_ISI_N_OR_G	0x10000000 /* ISI: Access is no-exec or G */
774
+#define   SRR1_ISI_N_G_OR_CIP	0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */
745775 #define   SRR1_ISI_PROT		0x08000000 /* ISI: Other protection fault */
746776 #define   SRR1_WAKEMASK		0x00380000 /* reason for wakeup */
747777 #define   SRR1_WAKEMASK_P8	0x003c0000 /* reason for wakeup on POWER8 and 9 */
....@@ -757,10 +787,9 @@
757787 #define	  SRR1_WAKERESET	0x00100000 /* System reset */
758788 #define   SRR1_WAKEHDBELL	0x000c0000 /* Hypervisor doorbell on P8 */
759789 #define	  SRR1_WAKESTATE	0x00030000 /* Powersave exit mask [46:47] */
760
-#define	  SRR1_WS_DEEPEST	0x00030000 /* Some resources not maintained,
761
-					  * may not be recoverable */
762
-#define	  SRR1_WS_DEEPER	0x00020000 /* Some resources not maintained */
763
-#define	  SRR1_WS_DEEP		0x00010000 /* All resources maintained */
790
+#define	  SRR1_WS_HVLOSS	0x00030000 /* HV resources not maintained */
791
+#define	  SRR1_WS_GPRLOSS	0x00020000 /* GPRs not maintained */
792
+#define	  SRR1_WS_NOLOSS	0x00010000 /* All resources maintained */
764793 #define   SRR1_PROGTM		0x00200000 /* TM Bad Thing */
765794 #define   SRR1_PROGFPE		0x00100000 /* Floating Point Enabled */
766795 #define   SRR1_PROGILL		0x00080000 /* Illegal instruction */
....@@ -769,10 +798,13 @@
769798 #define   SRR1_PROGADDR		0x00010000 /* SRR0 contains subsequent addr */
770799 
771800 #define   SRR1_MCE_MCP		0x00080000 /* Machine check signal caused interrupt */
801
+#define   SRR1_BOUNDARY		0x10000000 /* Prefixed instruction crosses 64-byte boundary */
802
+#define   SRR1_PREFIXED		0x20000000 /* Exception caused by prefixed instruction */
772803 
773804 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
774805 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
775806 #define   HSRR1_DENORM		0x00100000 /* Denorm exception */
807
+#define   HSRR1_HISI_WRITE	0x00010000 /* HISI bcs couldn't update mem */
776808 
777809 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
778810 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */
....@@ -833,6 +865,7 @@
833865 #define   MMCR0_BHRBA	0x00200000UL /* BHRB Access allowed in userspace */
834866 #define   MMCR0_EBE	0x00100000UL /* Event based branch enable */
835867 #define   MMCR0_PMCC	0x000c0000UL /* PMC control */
868
+#define   MMCR0_PMCCEXT	ASM_CONST(0x00000200) /* PMCCEXT control */
836869 #define   MMCR0_PMCC_U6	0x00080000UL /* PMC1-6 are R/W by user (PR) */
837870 #define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
838871 #define   MMCR0_PMCjCE	ASM_CONST(0x00004000) /* PMCj count enable*/
....@@ -849,7 +882,9 @@
849882 #define   MMCR0_FCHV	0x00000001UL /* freeze conditions in hypervisor mode */
850883 #define SPRN_MMCR1	798
851884 #define SPRN_MMCR2	785
885
+#define SPRN_MMCR3	754
852886 #define SPRN_UMMCR2	769
887
+#define SPRN_UMMCR3	738
853888 #define SPRN_MMCRA	0x312
854889 #define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
855890 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
....@@ -859,6 +894,7 @@
859894 #define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
860895 #define   MMCRA_SLOT_SHIFT	24
861896 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
897
+#define   MMCRA_BHRB_DISABLE  _UL(0x2000000000) // BHRB disable bit for ISA v3.1
862898 #define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL	/* SDAR/SIAR synced */
863899 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
864900 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
....@@ -891,6 +927,10 @@
891927 #define   SIER_SIHV		0x1000000	/* Sampled MSR_HV */
892928 #define   SIER_SIAR_VALID	0x0400000	/* SIAR contents valid */
893929 #define   SIER_SDAR_VALID	0x0200000	/* SDAR contents valid */
930
+#define SPRN_SIER2	752
931
+#define SPRN_SIER3	753
932
+#define SPRN_USIER2	736
933
+#define SPRN_USIER3	737
894934 #define SPRN_SIAR	796
895935 #define SPRN_SDAR	797
896936 #define SPRN_TACR	888
....@@ -1060,7 +1100,7 @@
10601100  *	- SPRG9 debug exception scratch
10611101  *
10621102  * All 32-bit:
1063
- *	- SPRG3 current thread_info pointer
1103
+ *	- SPRG3 current thread_struct physical addr pointer
10641104  *        (virtual on BookE, physical on others)
10651105  *
10661106  * 32-bit classic:
....@@ -1165,7 +1205,7 @@
11651205 #ifdef CONFIG_PPC_BOOK3S_32
11661206 #define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
11671207 #define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
1168
-#define SPRN_SPRG_RTAS		SPRN_SPRG2
1208
+#define SPRN_SPRG_PGDIR		SPRN_SPRG2
11691209 #define SPRN_SPRG_603_LRU	SPRN_SPRG4
11701210 #endif
11711211 
....@@ -1317,6 +1357,7 @@
13171357 #define PVR_POWER8NVL	0x004C
13181358 #define PVR_POWER8	0x004D
13191359 #define PVR_POWER9	0x004E
1360
+#define PVR_POWER10	0x0080
13201361 #define PVR_BE		0x0070
13211362 #define PVR_PA6T	0x0090
13221363 
....@@ -1327,6 +1368,7 @@
13271368 #define PVR_ARCH_206p	0x0f100003
13281369 #define PVR_ARCH_207	0x0f000004
13291370 #define PVR_ARCH_300	0x0f000005
1371
+#define PVR_ARCH_31	0x0f000006
13301372 
13311373 /* Macros for setting and retrieving special purpose registers */
13321374 #ifndef __ASSEMBLY__
....@@ -1362,6 +1404,14 @@
13621404 #define wrtspr(rn)	asm volatile("mtspr " __stringify(rn) ",0" : \
13631405 				     : : "memory")
13641406 
1407
+static inline void wrtee(unsigned long val)
1408
+{
1409
+	if (__builtin_constant_p(val))
1410
+		asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory");
1411
+	else
1412
+		asm volatile("wrtee %0" : : "r" (val) : "memory");
1413
+}
1414
+
13651415 extern unsigned long msr_check_and_set(unsigned long bits);
13661416 extern bool strict_msr_control;
13671417 extern void __msr_check_and_clear(unsigned long bits);
....@@ -1371,50 +1421,33 @@
13711421 		__msr_check_and_clear(bits);
13721422 }
13731423 
1374
-#ifdef __powerpc64__
1375
-#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1424
+#if defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)
13761425 #define mftb()		({unsigned long rval;				\
13771426 			asm volatile(					\
13781427 				"90:	mfspr %0, %2;\n"		\
1379
-				"97:	cmpwi %0,0;\n"			\
1380
-				"	beq- 90b;\n"			\
1381
-				"99:\n"					\
1382
-				".section __ftr_fixup,\"a\"\n"		\
1383
-				".align 3\n"				\
1384
-				"98:\n"					\
1385
-				"	.8byte %1\n"			\
1386
-				"	.8byte %1\n"			\
1387
-				"	.8byte 97b-98b\n"		\
1388
-				"	.8byte 99b-98b\n"		\
1389
-				"	.8byte 0\n"			\
1390
-				"	.8byte 0\n"			\
1391
-				".previous"				\
1428
+				ASM_FTR_IFSET(				\
1429
+					"97:	cmpwi %0,0;\n"		\
1430
+					"	beq- 90b;\n", "", %1)	\
13921431 			: "=r" (rval) \
13931432 			: "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
13941433 			rval;})
1434
+#elif defined(CONFIG_PPC_8xx)
1435
+#define mftb()		({unsigned long rval;	\
1436
+			asm volatile("mftbl %0" : "=r" (rval)); rval;})
13951437 #else
13961438 #define mftb()		({unsigned long rval;	\
13971439 			asm volatile("mfspr %0, %1" : \
13981440 				     "=r" (rval) : "i" (SPRN_TBRL)); rval;})
13991441 #endif /* !CONFIG_PPC_CELL */
14001442 
1401
-#else /* __powerpc64__ */
1402
-
14031443 #if defined(CONFIG_PPC_8xx)
1404
-#define mftbl()		({unsigned long rval;	\
1405
-			asm volatile("mftbl %0" : "=r" (rval)); rval;})
14061444 #define mftbu()		({unsigned long rval;	\
14071445 			asm volatile("mftbu %0" : "=r" (rval)); rval;})
14081446 #else
1409
-#define mftbl()		({unsigned long rval;	\
1410
-			asm volatile("mfspr %0, %1" : "=r" (rval) : \
1411
-				"i" (SPRN_TBRL)); rval;})
14121447 #define mftbu()		({unsigned long rval;	\
14131448 			asm volatile("mfspr %0, %1" : "=r" (rval) : \
14141449 				"i" (SPRN_TBRU)); rval;})
14151450 #endif
1416
-#define mftb()		mftbl()
1417
-#endif /* !__powerpc64__ */
14181451 
14191452 #define mttbl(v)	asm volatile("mttbl %0":: "r"(v))
14201453 #define mttbu(v)	asm volatile("mttbu %0":: "r"(v))
....@@ -1423,11 +1456,18 @@
14231456 #define mfsrin(v)	({unsigned int rval; \
14241457 			asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
14251458 					rval;})
1459
+
1460
+static inline void mtsrin(u32 val, u32 idx)
1461
+{
1462
+	asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx));
1463
+}
14261464 #endif
14271465 
14281466 #define proc_trap()	asm volatile("trap")
14291467 
1430
-extern unsigned long current_stack_pointer(void);
1468
+extern unsigned long current_stack_frame(void);
1469
+
1470
+register unsigned long current_stack_pointer asm("r1");
14311471 
14321472 extern unsigned long scom970_read(unsigned int address);
14331473 extern void scom970_write(unsigned int address, unsigned long value);
....@@ -1440,7 +1480,7 @@
14401480 {
14411481 	/*
14421482 	 *  The HID0 update on Power8 should at the very least be
1443
-	 *  preceded by a a SYNC instruction followed by an ISYNC
1483
+	 *  preceded by a SYNC instruction followed by an ISYNC
14441484 	 *  instruction
14451485 	 */
14461486 	asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));