disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/powerpc/include/asm/ppc_asm.h
..
..
@@ -311,18 +311,48 @@
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 	addis	reg,reg,(name - 0b)@ha;		\
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 	addi	reg,reg,(name - 0b)@l;
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-#ifdef __powerpc64__
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-#ifdef HAVE_AS_ATHIGH
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+#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
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 #define __AS_ATHIGH high
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 #else
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 #define __AS_ATHIGH h
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 #endif
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-#define LOAD_REG_IMMEDIATE(reg,expr)		\
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-	lis     reg,(expr)@highest;		\
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-	ori     reg,reg,(expr)@higher;	\
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-	rldicr  reg,reg,32,31;		\
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-	oris    reg,reg,(expr)@__AS_ATHIGH;	\
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-	ori     reg,reg,(expr)@l;
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+
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+.macro __LOAD_REG_IMMEDIATE_32 r, x
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+	.if (\x) >= 0x8000 || (\x) < -0x8000
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+		lis \r, (\x)@__AS_ATHIGH
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+		.if (\x) & 0xffff != 0
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+			ori \r, \r, (\x)@l
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+		.endif
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+	.else
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+		li \r, (\x)@l
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+	.endif
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+.endm
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+
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+.macro __LOAD_REG_IMMEDIATE r, x
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+	.if (\x) >= 0x80000000 || (\x) < -0x80000000
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+		__LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
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+		sldi	\r, \r, 32
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+		.if (\x) & 0xffff0000 != 0
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+			oris \r, \r, (\x)@__AS_ATHIGH
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+		.endif
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+		.if (\x) & 0xffff != 0
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+			ori \r, \r, (\x)@l
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+		.endif
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+	.else
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+		__LOAD_REG_IMMEDIATE_32 \r, \x
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+	.endif
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+.endm
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+
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+#ifdef __powerpc64__
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+
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+#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
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+
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+#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr)	\
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+	lis	tmp, (expr)@highest;		\
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+	lis	reg, (expr)@__AS_ATHIGH;	\
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+	ori	tmp, tmp, (expr)@higher;	\
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+	ori	reg, reg, (expr)@l;		\
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+	rldimi	reg, tmp, 32, 0
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356
 
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 #define LOAD_REG_ADDR(reg,name)			\
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 	ld	reg,name@got(r2)
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@@ -335,11 +365,13 @@
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 #else /* 32-bit */
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367
 
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-#define LOAD_REG_IMMEDIATE(reg,expr)		\
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+#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
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+
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+#define LOAD_REG_IMMEDIATE_SYM(reg,expr)		\
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 	lis	reg,(expr)@ha;		\
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 	addi	reg,reg,(expr)@l;
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373
 
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-#define LOAD_REG_ADDR(reg,name)		LOAD_REG_IMMEDIATE(reg, name)
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+#define LOAD_REG_ADDR(reg,name)		LOAD_REG_IMMEDIATE_SYM(reg, name)
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375
 
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 #define LOAD_REG_ADDRBASE(reg, name)	lis	reg,name@ha
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 #define ADDROFF(name)			name@l
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@@ -350,26 +382,6 @@
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 #endif
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383
 
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 /* various errata or part fixups */
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-#ifdef CONFIG_PPC601_SYNC_FIX
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-#define SYNC				\
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-BEGIN_FTR_SECTION			\
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-	sync;				\
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-	isync;				\
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-END_FTR_SECTION_IFSET(CPU_FTR_601)
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-#define SYNC_601			\
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-BEGIN_FTR_SECTION			\
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-	sync;				\
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-END_FTR_SECTION_IFSET(CPU_FTR_601)
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-#define ISYNC_601			\
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-BEGIN_FTR_SECTION			\
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-	isync;				\
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-END_FTR_SECTION_IFSET(CPU_FTR_601)
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-#else
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-#define	SYNC
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-#define SYNC_601
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-#define ISYNC_601
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-#endif
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-
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 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
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386
 #define MFTB(dest)			\
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 90:	mfspr dest, SPRN_TBRL;		\
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@@ -391,13 +403,8 @@
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403
 
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 #ifndef CONFIG_SMP
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 #define TLBSYNC
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-#else /* CONFIG_SMP */
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-/* tlbsync is not implemented on 601 */
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-#define TLBSYNC				\
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-BEGIN_FTR_SECTION			\
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-	tlbsync;			\
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-	sync;				\
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-END_FTR_SECTION_IFCLR(CPU_FTR_601)
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+#else
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+#define TLBSYNC		tlbsync; sync
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 #endif
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 #ifdef CONFIG_PPC64
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@@ -480,26 +487,11 @@
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 	ori	rd,rd,((KERNELBASE>>48)&0xFFFF);\
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 	rotldi	rd,rd,48
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 #else
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-/*
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- * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
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- * physical base address of RAM at compile time.
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- */
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 #define toreal(rd)	tophys(rd,rd)
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 #define fromreal(rd)	tovirt(rd,rd)
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-#define tophys(rd,rs)				\
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-0:	addis	rd,rs,-PAGE_OFFSET@h;		\
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-	.section ".vtop_fixup","aw";		\
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-	.align  1;				\
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-	.long   0b;				\
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-	.previous
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-
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-#define tovirt(rd,rs)				\
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-0:	addis	rd,rs,PAGE_OFFSET@h;		\
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-	.section ".ptov_fixup","aw";		\
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-	.align  1;				\
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-	.long   0b;				\
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-	.previous
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+#define tophys(rd, rs)	addis	rd, rs, -PAGE_OFFSET@h
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+#define tovirt(rd, rs)	addis	rd, rs, PAGE_OFFSET@h
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 #endif
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 #ifdef CONFIG_PPC_BOOK3S_64
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@@ -752,6 +744,8 @@
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 #define N_SLINE	68
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 #define N_SO	100
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746
 
747
+#define RFSCV	.long 0x4c0000a4
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+
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 /*
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  * Create an endian fixup trampoline
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  *
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@@ -771,7 +765,7 @@
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 #define FIXUP_ENDIAN
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 #else
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 /*
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- * This version may be used in in HV or non-HV context.
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+ * This version may be used in HV or non-HV context.
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  * MSR[EE] must be disabled.
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  */
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 #define FIXUP_ENDIAN						   \