disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/powerpc/include/asm/imc-pmu.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 #ifndef __ASM_POWERPC_IMC_PMU_H
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 #define __ASM_POWERPC_IMC_PMU_H
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@@ -7,11 +8,6 @@
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  * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
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  *           (C) 2017 Anju T Sudhakar, IBM Corporation.
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  *           (C) 2017 Hemant K Shaw, IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or later version.
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  */
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 #include <linux/perf_event.h>
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@@ -33,6 +29,7 @@
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  */
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 #define THREAD_IMC_LDBAR_MASK           0x0003ffffffffe000ULL
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 #define THREAD_IMC_ENABLE               0x8000000000000000ULL
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+#define TRACE_IMC_ENABLE		0x4000000000000000ULL
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 /*
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  * For debugfs interface for imc-mode and imc-command
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@@ -59,6 +56,34 @@
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 	char *scale;
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 };
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+/*
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+ * Trace IMC hardware updates a 64bytes record on
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+ * Core Performance Monitoring Counter (CPMC)
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+ * overflow. Here is the layout for the trace imc record
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+ *
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+ * DW 0 : Timebase
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+ * DW 1 : Program Counter
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+ * DW 2 : PIDR information
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+ * DW 3 : CPMC1
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+ * DW 4 : CPMC2
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+ * DW 5 : CPMC3
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+ * Dw 6 : CPMC4
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+ * DW 7 : Timebase
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+ * .....
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+ *
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+ * The following is the data structure to hold trace imc data.
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+ */
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+struct trace_imc_data {
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+	u64 tb1;
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+	u64 ip;
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+	u64 val;
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+	u64 cpmc1;
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+	u64 cpmc2;
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+	u64 cpmc3;
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+	u64 cpmc4;
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+	u64 tb2;
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+};
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+
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 /* Event attribute array index */
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 #define IMC_FORMAT_ATTR		0
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 #define IMC_EVENT_ATTR		1
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@@ -67,6 +92,18 @@
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 /* PMU Format attribute macros */
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 #define IMC_EVENT_OFFSET_MASK	0xffffffffULL
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+
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+/*
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+ * Macro to mask bits 0:21 of first double word(which is the timebase) to
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+ * compare with 8th double word (timebase) of trace imc record data.
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+ */
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+#define IMC_TRACE_RECORD_TB1_MASK      0x3ffffffffffULL
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+
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+/*
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+ * Bit 0:1 in third DW of IMC trace record
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+ * specifies the MSR[HV PR] values.
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+ */
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+#define IMC_TRACE_RECORD_VAL_HVPR(x)	((x) >> 62)
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 /*
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  * Device tree parser code detects IMC pmu support and
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@@ -100,7 +137,7 @@
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  * are inited.
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  */
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 struct imc_pmu_ref {
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-	struct mutex lock;
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+	spinlock_t lock;
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 	unsigned int id;
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 	int refc;
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 };
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@@ -113,6 +150,7 @@
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 enum {
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 	IMC_TYPE_THREAD		= 0x1,
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+	IMC_TYPE_TRACE		= 0x2,
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 	IMC_TYPE_CORE		= 0x4,
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 	IMC_TYPE_CHIP           = 0x10,
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 };
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@@ -123,6 +161,8 @@
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 #define IMC_DOMAIN_NEST		1
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 #define IMC_DOMAIN_CORE		2
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 #define IMC_DOMAIN_THREAD	3
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+/* For trace-imc the domain is still thread but it operates in trace-mode */
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+#define IMC_DOMAIN_TRACE	4
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 extern int init_imc_pmu(struct device_node *parent,
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 				struct imc_pmu *pmu_ptr, int pmu_id);