disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/powerpc/include/asm/cputhreads.h
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@@ -28,6 +28,7 @@
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 #define threads_per_core	1
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 #define threads_per_subcore	1
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 #define threads_shift		0
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+#define has_big_cores		0
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 #define threads_core_mask	(*get_cpu_mask(0))
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 #endif
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..
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@@ -97,6 +98,36 @@
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 	return cpu | (threads_per_core - 1);
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 }
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+/*
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+ * tlb_thread_siblings are siblings which share a TLB. This is not
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+ * architected, is not something a hypervisor could emulate and a future
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+ * CPU may change behaviour even in compat mode, so this should only be
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+ * used on PowerNV, and only with care.
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+ */
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+static inline int cpu_first_tlb_thread_sibling(int cpu)
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+{
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+	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))
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+		return cpu & ~0x6;	/* Big Core */
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+	else
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+		return cpu_first_thread_sibling(cpu);
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+}
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+
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+static inline int cpu_last_tlb_thread_sibling(int cpu)
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+{
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+	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))
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+		return cpu | 0x6;	/* Big Core */
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+	else
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+		return cpu_last_thread_sibling(cpu);
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+}
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+
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+static inline int cpu_tlb_thread_sibling_step(void)
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+{
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+	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))
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+		return 2;		/* Big Core */
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+	else
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+		return 1;
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+}
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+
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 static inline u32 get_tensr(void)
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 {
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 #ifdef	CONFIG_BOOKE