.. | .. |
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6 | 6 | #include <linux/compiler.h> |
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7 | 7 | #include <asm/synch.h> |
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8 | 8 | #include <linux/bug.h> |
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9 | | -#include <asm/asm-405.h> |
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10 | 9 | |
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11 | 10 | #ifdef __BIG_ENDIAN |
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12 | 11 | #define BITOFF_CAL(size, off) ((sizeof(u32) - size - off) * BITS_PER_BYTE) |
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.. | .. |
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29 | 28 | "1: lwarx %0,0,%3\n" \ |
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30 | 29 | " andc %1,%0,%5\n" \ |
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31 | 30 | " or %1,%1,%4\n" \ |
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32 | | - PPC405_ERR77(0,%3) \ |
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33 | 31 | " stwcx. %1,0,%3\n" \ |
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34 | 32 | " bne- 1b\n" \ |
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35 | 33 | : "=&r" (prev), "=&r" (tmp), "+m" (*(u32*)p) \ |
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.. | .. |
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60 | 58 | " bne- 2f\n" \ |
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61 | 59 | " andc %1,%0,%6\n" \ |
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62 | 60 | " or %1,%1,%5\n" \ |
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63 | | - PPC405_ERR77(0,%3) \ |
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64 | 61 | " stwcx. %1,0,%3\n" \ |
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65 | 62 | " bne- 1b\n" \ |
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66 | 63 | br2 \ |
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.. | .. |
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92 | 89 | |
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93 | 90 | __asm__ __volatile__( |
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94 | 91 | "1: lwarx %0,0,%2 \n" |
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95 | | - PPC405_ERR77(0,%2) |
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96 | 92 | " stwcx. %3,0,%2 \n\ |
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97 | 93 | bne- 1b" |
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98 | 94 | : "=&r" (prev), "+m" (*(volatile unsigned int *)p) |
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.. | .. |
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109 | 105 | |
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110 | 106 | __asm__ __volatile__( |
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111 | 107 | "1: lwarx %0,0,%2\n" |
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112 | | - PPC405_ERR77(0, %2) |
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113 | 108 | " stwcx. %3,0,%2\n" |
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114 | 109 | " bne- 1b" |
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115 | 110 | : "=&r" (prev), "+m" (*p) |
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.. | .. |
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127 | 122 | |
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128 | 123 | __asm__ __volatile__( |
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129 | 124 | "1: ldarx %0,0,%2 \n" |
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130 | | - PPC405_ERR77(0,%2) |
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131 | 125 | " stdcx. %3,0,%2 \n\ |
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132 | 126 | bne- 1b" |
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133 | 127 | : "=&r" (prev), "+m" (*(volatile unsigned long *)p) |
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.. | .. |
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144 | 138 | |
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145 | 139 | __asm__ __volatile__( |
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146 | 140 | "1: ldarx %0,0,%2\n" |
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147 | | - PPC405_ERR77(0, %2) |
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148 | 141 | " stdcx. %3,0,%2\n" |
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149 | 142 | " bne- 1b" |
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150 | 143 | : "=&r" (prev), "+m" (*p) |
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.. | .. |
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229 | 222 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ |
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230 | 223 | cmpw 0,%0,%3\n\ |
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231 | 224 | bne- 2f\n" |
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232 | | - PPC405_ERR77(0,%2) |
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233 | 225 | " stwcx. %4,0,%2\n\ |
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234 | 226 | bne- 1b" |
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235 | 227 | PPC_ATOMIC_EXIT_BARRIER |
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.. | .. |
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252 | 244 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ |
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253 | 245 | cmpw 0,%0,%3\n\ |
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254 | 246 | bne- 2f\n" |
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255 | | - PPC405_ERR77(0,%2) |
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256 | 247 | " stwcx. %4,0,%2\n\ |
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257 | 248 | bne- 1b" |
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258 | 249 | "\n\ |
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.. | .. |
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273 | 264 | "1: lwarx %0,0,%2 # __cmpxchg_u32_relaxed\n" |
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274 | 265 | " cmpw 0,%0,%3\n" |
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275 | 266 | " bne- 2f\n" |
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276 | | - PPC405_ERR77(0, %2) |
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277 | 267 | " stwcx. %4,0,%2\n" |
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278 | 268 | " bne- 1b\n" |
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279 | 269 | "2:" |
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.. | .. |
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301 | 291 | "1: lwarx %0,0,%2 # __cmpxchg_u32_acquire\n" |
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302 | 292 | " cmpw 0,%0,%3\n" |
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303 | 293 | " bne- 2f\n" |
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304 | | - PPC405_ERR77(0, %2) |
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305 | 294 | " stwcx. %4,0,%2\n" |
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306 | 295 | " bne- 1b\n" |
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307 | 296 | PPC_ACQUIRE_BARRIER |
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