.. | .. |
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90 | 90 | cpu0: PowerPC,e500mc@0 { |
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91 | 91 | device_type = "cpu"; |
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92 | 92 | reg = <0>; |
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93 | | - clocks = <&mux0>; |
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| 93 | + clocks = <&clockgen 1 0>; |
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94 | 94 | next-level-cache = <&L2_0>; |
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95 | 95 | fsl,portid-mapping = <0x80000000>; |
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96 | 96 | L2_0: l2-cache { |
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.. | .. |
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100 | 100 | cpu1: PowerPC,e500mc@1 { |
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101 | 101 | device_type = "cpu"; |
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102 | 102 | reg = <1>; |
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103 | | - clocks = <&mux1>; |
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| 103 | + clocks = <&clockgen 1 1>; |
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104 | 104 | next-level-cache = <&L2_1>; |
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105 | 105 | fsl,portid-mapping = <0x40000000>; |
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106 | 106 | L2_1: l2-cache { |
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.. | .. |
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110 | 110 | cpu2: PowerPC,e500mc@2 { |
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111 | 111 | device_type = "cpu"; |
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112 | 112 | reg = <2>; |
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113 | | - clocks = <&mux2>; |
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| 113 | + clocks = <&clockgen 1 2>; |
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114 | 114 | next-level-cache = <&L2_2>; |
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115 | 115 | fsl,portid-mapping = <0x20000000>; |
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116 | 116 | L2_2: l2-cache { |
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.. | .. |
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120 | 120 | cpu3: PowerPC,e500mc@3 { |
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121 | 121 | device_type = "cpu"; |
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122 | 122 | reg = <3>; |
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123 | | - clocks = <&mux3>; |
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| 123 | + clocks = <&clockgen 1 3>; |
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124 | 124 | next-level-cache = <&L2_3>; |
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125 | 125 | fsl,portid-mapping = <0x10000000>; |
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126 | 126 | L2_3: l2-cache { |
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