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2 | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
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3 | 3 | |
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4 | 4 | #include <linux/cpu.h> |
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5 | | -#include <linux/bootmem.h> |
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6 | | -#include <linux/seq_file.h> |
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7 | 5 | #include <linux/memblock.h> |
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| 6 | +#include <linux/seq_file.h> |
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8 | 7 | #include <linux/console.h> |
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9 | 8 | #include <linux/screen_info.h> |
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10 | 9 | #include <linux/delay.h> |
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.. | .. |
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16 | 15 | #include <asm/proc-fns.h> |
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17 | 16 | #include <asm/cache_info.h> |
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18 | 17 | #include <asm/elf.h> |
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| 18 | +#include <asm/fpu.h> |
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19 | 19 | #include <nds32_intrinsic.h> |
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20 | 20 | |
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21 | 21 | #define HWCAP_MFUSR_PC 0x000001 |
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.. | .. |
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39 | 39 | #define HWCAP_FPU_DP 0x040000 |
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40 | 40 | #define HWCAP_V2 0x080000 |
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41 | 41 | #define HWCAP_DX_REGS 0x100000 |
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| 42 | +#define HWCAP_HWPRE 0x200000 |
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42 | 43 | |
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43 | 44 | unsigned long cpu_id, cpu_rev, cpu_cfgid; |
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| 45 | +bool has_fpu = false; |
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44 | 46 | char cpu_series; |
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45 | 47 | char *endianness = NULL; |
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46 | 48 | |
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.. | .. |
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74 | 76 | "fpu_dp", |
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75 | 77 | "v2", |
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76 | 78 | "dx_regs", |
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| 79 | + "hw_pre", |
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77 | 80 | NULL, |
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78 | 81 | }; |
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79 | 82 | |
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.. | .. |
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138 | 141 | (aliasing_num - 1) << PAGE_SHIFT; |
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139 | 142 | } |
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140 | 143 | #endif |
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| 144 | +#ifdef CONFIG_FPU |
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| 145 | + /* Disable fpu and enable when it is used. */ |
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| 146 | + if (has_fpu) |
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| 147 | + disable_fpu(); |
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| 148 | +#endif |
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141 | 149 | } |
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142 | 150 | |
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143 | 151 | static void __init setup_cpuinfo(void) |
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.. | .. |
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182 | 190 | if (cpu_cfgid & 0x0004) |
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183 | 191 | elf_hwcap |= HWCAP_EXT2; |
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184 | 192 | |
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185 | | - if (cpu_cfgid & 0x0008) |
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| 193 | + if (cpu_cfgid & 0x0008) { |
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186 | 194 | elf_hwcap |= HWCAP_FPU; |
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187 | | - |
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| 195 | + has_fpu = true; |
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| 196 | + } |
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188 | 197 | if (cpu_cfgid & 0x0010) |
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189 | 198 | elf_hwcap |= HWCAP_STRING; |
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190 | 199 | |
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.. | .. |
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214 | 223 | if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C) |
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215 | 224 | elf_hwcap |= HWCAP_L2C; |
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216 | 225 | |
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| 226 | +#ifdef CONFIG_HW_PRE |
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| 227 | + if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN) |
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| 228 | + elf_hwcap |= HWCAP_HWPRE; |
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| 229 | +#endif |
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| 230 | + |
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217 | 231 | tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); |
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218 | 232 | if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE)) |
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219 | 233 | tmp |= CACHE_CTL_mskDC_EN; |
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.. | .. |
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235 | 249 | memory_end = memory_start = 0; |
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236 | 250 | |
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237 | 251 | /* Find main memory where is the kernel */ |
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238 | | - for_each_memblock(memory, region) { |
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239 | | - memory_start = region->base; |
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240 | | - memory_end = region->base + region->size; |
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241 | | - pr_info("%s: Memory: 0x%x-0x%x\n", __func__, |
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242 | | - memory_start, memory_end); |
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243 | | - } |
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| 252 | + memory_start = memblock_start_of_DRAM(); |
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| 253 | + memory_end = memblock_end_of_DRAM(); |
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244 | 254 | |
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245 | 255 | if (!memory_end) { |
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246 | 256 | panic("No memory!"); |
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.. | .. |
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302 | 312 | parse_early_param(); |
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303 | 313 | |
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304 | 314 | unflatten_and_copy_device_tree(); |
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305 | | - |
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306 | | - if(IS_ENABLED(CONFIG_VT)) { |
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307 | | - if(IS_ENABLED(CONFIG_DUMMY_CONSOLE)) |
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308 | | - conswitchp = &dummy_con; |
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309 | | - } |
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310 | 315 | |
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311 | 316 | *cmdline_p = boot_command_line; |
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312 | 317 | early_trap_init(); |
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