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hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/mips/include/asm/hazards.h
....@@ -22,8 +22,9 @@
2222 /*
2323  * TLB hazards
2424  */
25
-#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
26
-	!defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
25
+#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
26
+     defined(CONFIG_CPU_MIPSR6)) && \
27
+    !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
2728 
2829 /*
2930  * MIPSR2 defines ehb for hazard avoidance
....@@ -66,10 +67,11 @@
6667 	unsigned long tmp;						\
6768 									\
6869 	__asm__ __volatile__(						\
70
+	"	.set	push					\n"	\
6971 	"	.set "MIPS_ISA_LEVEL"				\n"	\
7072 	"	dla	%0, 1f					\n"	\
7173 	"	jr.hb	%0					\n"	\
72
-	"	.set	mips0					\n"	\
74
+	"	.set	pop					\n"	\
7375 	"1:							\n"	\
7476 	: "=r" (tmp));							\
7577 } while (0)
....@@ -141,10 +143,11 @@
141143 	unsigned long tmp;						\
142144 									\
143145 	__asm__ __volatile__(						\
146
+	"	.set	push					\n"	\
144147 	"	.set	mips64r2				\n"	\
145148 	"	dla	%0, 1f					\n"	\
146149 	"	jr.hb	%0					\n"	\
147
-	"	.set	mips0					\n"	\
150
+	"	.set	pop					\n"	\
148151 	"1:							\n"	\
149152 	: "=r" (tmp));							\
150153 } while (0)
....@@ -156,7 +159,7 @@
156159 } while (0)
157160 
158161 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
159
-	defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
162
+	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
160163 	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
161164 
162165 /*
....@@ -276,7 +279,8 @@
276279 
277280 #define __disable_fpu_hazard
278281 
279
-#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
282
+#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
283
+      defined(CONFIG_CPU_MIPSR6)
280284 
281285 #define __enable_fpu_hazard						\
282286 	___ehb