disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/ia64/include/asm/pgtable.h
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@@ -279,16 +279,16 @@
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 #define pud_bad(pud)			(!ia64_phys_addr_valid(pud_val(pud)))
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 #define pud_present(pud)		(pud_val(pud) != 0UL)
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 #define pud_clear(pudp)			(pud_val(*(pudp)) = 0UL)
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-#define pud_page_vaddr(pud)		((unsigned long) __va(pud_val(pud) & _PFN_MASK))
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+#define pud_pgtable(pud)		((pmd_t *) __va(pud_val(pud) & _PFN_MASK))
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 #define pud_page(pud)			virt_to_page((pud_val(pud) + PAGE_OFFSET))
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 #if CONFIG_PGTABLE_LEVELS == 4
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-#define pgd_none(pgd)			(!pgd_val(pgd))
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-#define pgd_bad(pgd)			(!ia64_phys_addr_valid(pgd_val(pgd)))
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-#define pgd_present(pgd)		(pgd_val(pgd) != 0UL)
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-#define pgd_clear(pgdp)			(pgd_val(*(pgdp)) = 0UL)
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-#define pgd_page_vaddr(pgd)		((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
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-#define pgd_page(pgd)			virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
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+#define p4d_none(p4d)			(!p4d_val(p4d))
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+#define p4d_bad(p4d)			(!ia64_phys_addr_valid(p4d_val(p4d)))
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+#define p4d_present(p4d)		(p4d_val(p4d) != 0UL)
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+#define p4d_clear(p4dp)			(p4d_val(*(p4dp)) = 0UL)
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+#define p4d_pgtable(p4d)		((pud_t *) __va(p4d_val(p4d) & _PFN_MASK))
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+#define p4d_page(p4d)			virt_to_page((p4d_val(p4d) + PAGE_OFFSET))
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 #endif
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 /*
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@@ -298,7 +298,6 @@
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 #define pte_exec(pte)		((pte_val(pte) & _PAGE_AR_RX) != 0)
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 #define pte_dirty(pte)		((pte_val(pte) & _PAGE_D) != 0)
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 #define pte_young(pte)		((pte_val(pte) & _PAGE_A) != 0)
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-#define pte_special(pte)	0
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 /*
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  * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
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@@ -311,7 +310,6 @@
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 #define pte_mkclean(pte)	(__pte(pte_val(pte) & ~_PAGE_D))
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 #define pte_mkdirty(pte)	(__pte(pte_val(pte) | _PAGE_D))
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 #define pte_mkhuge(pte)		(__pte(pte_val(pte)))
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-#define pte_mkspecial(pte)	(pte)
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 /*
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  * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
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@@ -366,17 +364,14 @@
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 	return (region << (PAGE_SHIFT - 6)) | l1index;
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 }
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+#define pgd_index pgd_index
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-/* The offset in the 1-level directory is given by the 3 region bits
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-   (61..63) and the level-1 bits.  */
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-static inline pgd_t*
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-pgd_offset (const struct mm_struct *mm, unsigned long address)
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-{
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-	return mm->pgd + pgd_index(address);
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-}
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-
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-/* In the kernel's mapped region we completely ignore the region number
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-   (since we know it's in region number 5). */
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+/*
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+ * In the kernel's mapped region we know everything is in region number 5, so
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+ * as an optimisation its PGD already points to the area for that region.
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+ * However, this also means that we cannot use pgd_index() and we must
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+ * never add the region here.
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+ */
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 #define pgd_offset_k(addr) \
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 	(init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
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@@ -384,25 +379,6 @@
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    resides in the kernel-mapped segment, hence we use pgd_offset_k()
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    here.  */
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 #define pgd_offset_gate(mm, addr)	pgd_offset_k(addr)
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-
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-#if CONFIG_PGTABLE_LEVELS == 4
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-/* Find an entry in the second-level page table.. */
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-#define pud_offset(dir,addr) \
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-	((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
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-#endif
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-
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-/* Find an entry in the third-level page table.. */
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-#define pmd_offset(dir,addr) \
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-	((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
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-
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-/*
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- * Find an entry in the third-level page table.  This looks more complicated than it
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- * should be because some platforms place page tables in high memory.
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- */
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-#define pte_index(addr)	 	(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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-#define pte_offset_kernel(dir,addr)	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
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-#define pte_offset_map(dir,addr)	pte_offset_kernel(dir, addr)
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-#define pte_unmap(pte)			do { } while (0)
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 /* atomic versions of the some PTE manipulations: */
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@@ -544,9 +520,9 @@
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 #  ifdef CONFIG_VIRTUAL_MEM_MAP
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   /* arch mem_map init routine is needed due to holes in a virtual mem_map */
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-#   define __HAVE_ARCH_MEMMAP_INIT
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-    extern void memmap_init (unsigned long size, int nid, unsigned long zone,
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-			     unsigned long start_pfn);
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+void memmap_init(void);
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+void arch_memmap_init(unsigned long size, int nid, unsigned long zone,
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+		      unsigned long start_pfn);
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 #  endif /* CONFIG_VIRTUAL_MEM_MAP */
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 # endif /* !__ASSEMBLY__ */
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@@ -567,11 +543,6 @@
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 #define KERNEL_TR_PAGE_SHIFT	_PAGE_SIZE_64M
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 #define KERNEL_TR_PAGE_SIZE	(1 << KERNEL_TR_PAGE_SHIFT)
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-/*
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- * No page table caches to initialise
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- */
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-#define pgtable_cache_init()	do { } while (0)
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-
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 /* These tell get_user_pages() that the first gate page is accessible from user-level.  */
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 #define FIXADDR_USER_START	GATE_ADDR
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 #ifdef HAVE_BUGGY_SEGREL
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@@ -588,10 +559,8 @@
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 #if CONFIG_PGTABLE_LEVELS == 3
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-#define __ARCH_USE_5LEVEL_HACK
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 #include <asm-generic/pgtable-nopud.h>
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 #endif
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-#include <asm-generic/5level-fixup.h>
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-#include <asm-generic/pgtable.h>
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+#include <asm-generic/pgtable-nop4d.h>
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 #endif /* _ASM_IA64_PGTABLE_H */