~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,18 +1,8 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Record and handle CPU attributes.
3	4	*
4	5	* Copyright (C) 2014 ARM Ltd.
5		- * This program is free software; you can redistribute it and/or modify
6		- * it under the terms of the GNU General Public License version 2 as
7		- * published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- * GNU General Public License for more details.
13		- *
14		- * You should have received a copy of the GNU General Public License
15		- * along with this program. If not, see <http://www.gnu.org/licenses/>.
16	6	*/
17	7	#include <asm/arch_timer.h>
18	8	#include <asm/cache.h>
..	..	@@ -34,12 +24,6 @@
34	24	#include <linux/sched.h>
35	25	#include <linux/smp.h>
36	26	#include <linux/delay.h>
37		-#include <linux/of_fdt.h>
38		-
39		-char* (*arch_read_hardware_id)(void);
40		-EXPORT_SYMBOL(arch_read_hardware_id);
41		-
42		-static const char *machine_name;
43	27
44	28	unsigned int system_serial_low;
45	29	EXPORT_SYMBOL(system_serial_low);
..	..	@@ -55,82 +39,106 @@
55	39	DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
56	40	static struct cpuinfo_arm64 boot_cpu_data;
57	41
58		-static char *icache_policy_str[] = {
59		- [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
	42	+static const char *icache_policy_str[] = {
	43	+ [ICACHE_POLICY_VPIPT] = "VPIPT",
	44	+ [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
60	45	[ICACHE_POLICY_VIPT] = "VIPT",
61	46	[ICACHE_POLICY_PIPT] = "PIPT",
62		- [ICACHE_POLICY_VPIPT] = "VPIPT",
63	47	};
64	48
65	49	unsigned long __icache_flags;
66	50
67	51	static const char *const hwcap_str[] = {
68		- "fp",
69		- "asimd",
70		- "evtstrm",
71		- "aes",
72		- "pmull",
73		- "sha1",
74		- "sha2",
75		- "crc32",
76		- "atomics",
77		- "fphp",
78		- "asimdhp",
79		- "cpuid",
80		- "asimdrdm",
81		- "jscvt",
82		- "fcma",
83		- "lrcpc",
84		- "dcpop",
85		- "sha3",
86		- "sm3",
87		- "sm4",
88		- "asimddp",
89		- "sha512",
90		- "sve",
91		- "asimdfhm",
92		- "dit",
93		- "uscat",
94		- "ilrcpc",
95		- "flagm",
96		- "ssbs",
97		- NULL
	52	+ [KERNEL_HWCAP_FP] = "fp",
	53	+ [KERNEL_HWCAP_ASIMD] = "asimd",
	54	+ [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
	55	+ [KERNEL_HWCAP_AES] = "aes",
	56	+ [KERNEL_HWCAP_PMULL] = "pmull",
	57	+ [KERNEL_HWCAP_SHA1] = "sha1",
	58	+ [KERNEL_HWCAP_SHA2] = "sha2",
	59	+ [KERNEL_HWCAP_CRC32] = "crc32",
	60	+ [KERNEL_HWCAP_ATOMICS] = "atomics",
	61	+ [KERNEL_HWCAP_FPHP] = "fphp",
	62	+ [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
	63	+ [KERNEL_HWCAP_CPUID] = "cpuid",
	64	+ [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
	65	+ [KERNEL_HWCAP_JSCVT] = "jscvt",
	66	+ [KERNEL_HWCAP_FCMA] = "fcma",
	67	+ [KERNEL_HWCAP_LRCPC] = "lrcpc",
	68	+ [KERNEL_HWCAP_DCPOP] = "dcpop",
	69	+ [KERNEL_HWCAP_SHA3] = "sha3",
	70	+ [KERNEL_HWCAP_SM3] = "sm3",
	71	+ [KERNEL_HWCAP_SM4] = "sm4",
	72	+ [KERNEL_HWCAP_ASIMDDP] = "asimddp",
	73	+ [KERNEL_HWCAP_SHA512] = "sha512",
	74	+ [KERNEL_HWCAP_SVE] = "sve",
	75	+ [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
	76	+ [KERNEL_HWCAP_DIT] = "dit",
	77	+ [KERNEL_HWCAP_USCAT] = "uscat",
	78	+ [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
	79	+ [KERNEL_HWCAP_FLAGM] = "flagm",
	80	+ [KERNEL_HWCAP_SSBS] = "ssbs",
	81	+ [KERNEL_HWCAP_SB] = "sb",
	82	+ [KERNEL_HWCAP_PACA] = "paca",
	83	+ [KERNEL_HWCAP_PACG] = "pacg",
	84	+ [KERNEL_HWCAP_DCPODP] = "dcpodp",
	85	+ [KERNEL_HWCAP_SVE2] = "sve2",
	86	+ [KERNEL_HWCAP_SVEAES] = "sveaes",
	87	+ [KERNEL_HWCAP_SVEPMULL] = "svepmull",
	88	+ [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
	89	+ [KERNEL_HWCAP_SVESHA3] = "svesha3",
	90	+ [KERNEL_HWCAP_SVESM4] = "svesm4",
	91	+ [KERNEL_HWCAP_FLAGM2] = "flagm2",
	92	+ [KERNEL_HWCAP_FRINT] = "frint",
	93	+ [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
	94	+ [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
	95	+ [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
	96	+ [KERNEL_HWCAP_SVEBF16] = "svebf16",
	97	+ [KERNEL_HWCAP_I8MM] = "i8mm",
	98	+ [KERNEL_HWCAP_BF16] = "bf16",
	99	+ [KERNEL_HWCAP_DGH] = "dgh",
	100	+ [KERNEL_HWCAP_RNG] = "rng",
	101	+ [KERNEL_HWCAP_BTI] = "bti",
	102	+ [KERNEL_HWCAP_MTE] = "mte",
	103	+ [KERNEL_HWCAP_ECV] = "ecv",
	104	+ [KERNEL_HWCAP_AFP] = "afp",
	105	+ [KERNEL_HWCAP_RPRES] = "rpres",
98	106	};
99	107
100	108	#ifdef CONFIG_COMPAT
	109	+#define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
101	110	static const char *const compat_hwcap_str[] = {
102		- "swp",
103		- "half",
104		- "thumb",
105		- "26bit",
106		- "fastmult",
107		- "fpa",
108		- "vfp",
109		- "edsp",
110		- "java",
111		- "iwmmxt",
112		- "crunch",
113		- "thumbee",
114		- "neon",
115		- "vfpv3",
116		- "vfpv3d16",
117		- "tls",
118		- "vfpv4",
119		- "idiva",
120		- "idivt",
121		- "vfpd32",
122		- "lpae",
123		- "evtstrm",
124		- NULL
	111	+ [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
	112	+ [COMPAT_KERNEL_HWCAP(HALF)] = "half",
	113	+ [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
	114	+ [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
	115	+ [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
	116	+ [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
	117	+ [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
	118	+ [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
	119	+ [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
	120	+ [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
	121	+ [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
	122	+ [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
	123	+ [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
	124	+ [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
	125	+ [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
	126	+ [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
	127	+ [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
	128	+ [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
	129	+ [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
	130	+ [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
	131	+ [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
	132	+ [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
125	133	};
126	134
	135	+#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
127	136	static const char *const compat_hwcap2_str[] = {
128		- "aes",
129		- "pmull",
130		- "sha1",
131		- "sha2",
132		- "crc32",
133		- NULL
	137	+ [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
	138	+ [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
	139	+ [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
	140	+ [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
	141	+ [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
134	142	};
135	143	#endif /* CONFIG_COMPAT */
136	144
..	..	@@ -167,17 +175,26 @@
167	175	seq_puts(m, "Features\t:");
168	176	if (compat) {
169	177	#ifdef CONFIG_COMPAT
170		- for (j = 0; compat_hwcap_str[j]; j++)
171		- if (compat_elf_hwcap & (1 << j))
172		- seq_printf(m, " %s", compat_hwcap_str[j]);
	178	+ for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
	179	+ if (compat_elf_hwcap & (1 << j)) {
	180	+ /*
	181	+ * Warn once if any feature should not
	182	+ * have been present on arm64 platform.
	183	+ */
	184	+ if (WARN_ON_ONCE(!compat_hwcap_str[j]))
	185	+ continue;
173	186
174		- for (j = 0; compat_hwcap2_str[j]; j++)
	187	+ seq_printf(m, " %s", compat_hwcap_str[j]);
	188	+ }
	189	+ }
	190	+
	191	+ for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
175	192	if (compat_elf_hwcap2 & (1 << j))
176	193	seq_printf(m, " %s", compat_hwcap2_str[j]);
177	194	#endif /* CONFIG_COMPAT */
178	195	} else {
179		- for (j = 0; hwcap_str[j]; j++)
180		- if (elf_hwcap & (1 << j))
	196	+ for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
	197	+ if (cpu_have_feature(j))
181	198	seq_printf(m, " %s", hwcap_str[j]);
182	199	}
183	200	seq_puts(m, "\n");
..	..	@@ -189,11 +206,6 @@
189	206	seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
190	207	seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
191	208	}
192		-
193		- if (!arch_read_hardware_id)
194		- seq_printf(m, "Hardware\t: %s\n", machine_name);
195		- else
196		- seq_printf(m, "Hardware\t: %s\n", arch_read_hardware_id());
197	209
198	210	seq_printf(m, "Serial\t\t: %08x%08x\n",
199	211	system_serial_high, system_serial_low);
..	..	@@ -322,6 +334,8 @@
322	334	}
323	335	return 0;
324	336	}
	337	+device_initcall(cpuinfo_regs_init);
	338	+
325	339	static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
326	340	{
327	341	unsigned int cpu = smp_processor_id();
..	..	@@ -333,20 +347,54 @@
333	347	case ICACHE_POLICY_VPIPT:
334	348	set_bit(ICACHEF_VPIPT, &__icache_flags);
335	349	break;
336		- default:
337		- /* Fallthrough */
	350	+ case ICACHE_POLICY_RESERVED:
338	351	case ICACHE_POLICY_VIPT:
339	352	/* Assume aliasing */
340	353	set_bit(ICACHEF_ALIASING, &__icache_flags);
	354	+ break;
341	355	}
342	356
343	357	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
344	358	}
345	359
	360	+static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
	361	+{
	362	+ info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
	363	+ info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
	364	+ info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
	365	+ info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
	366	+ info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
	367	+ info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
	368	+ info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
	369	+ info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
	370	+ info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
	371	+ info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
	372	+ info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
	373	+ info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
	374	+ info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
	375	+ info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
	376	+ info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
	377	+ info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
	378	+ info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
	379	+ info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
	380	+
	381	+ info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
	382	+ info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
	383	+ info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
	384	+}
	385	+
346	386	static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
347	387	{
348	388	info->reg_cntfrq = arch_timer_get_cntfrq();
349		- info->reg_ctr = read_cpuid_cachetype();
	389	+ /*
	390	+ * Use the effective value of the CTR_EL0 than the raw value
	391	+ * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
	392	+ * with the CLIDR_EL1 fields to avoid triggering false warnings
	393	+ * when there is a mismatch across the CPUs. Keep track of the
	394	+ * effective value of the CTR_EL0 in our internal records for
	395	+ * acurate sanity check and feature enablement.
	396	+ */
	397	+ info->reg_ctr = read_cpuid_effective_cachetype();
350	398	info->reg_dczid = read_cpuid(DCZID_EL0);
351	399	info->reg_midr = read_cpuid_id();
352	400	info->reg_revidr = read_cpuid(REVIDR_EL1);
..	..	@@ -355,6 +403,7 @@
355	403	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
356	404	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
357	405	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
	406	+ info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
358	407	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
359	408	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
360	409	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
..	..	@@ -362,26 +411,8 @@
362	411	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
363	412	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
364	413
365		- /* Update the 32bit ID registers only if AArch32 is implemented */
366		- if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
367		- info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
368		- info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
369		- info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
370		- info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
371		- info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
372		- info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
373		- info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
374		- info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
375		- info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
376		- info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
377		- info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
378		- info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
379		- info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
380		-
381		- info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
382		- info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
383		- info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
384		- }
	414	+ if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
	415	+ __cpuinfo_store_cpu_32bit(&info->aarch32);
385	416
386	417	if (IS_ENABLED(CONFIG_ARM64_SVE) &&
387	418	id_aa64pfr0_sve(info->reg_id_aa64pfr0))
..	..	@@ -404,7 +435,4 @@
404	435
405	436	boot_cpu_data = *info;
406	437	init_cpu_features(&boot_cpu_data);
407		- machine_name = of_flat_dt_get_machine_name();
408	438	}
409		-
410		-device_initcall(cpuinfo_regs_init);