disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/arm64/kernel/cacheinfo.c
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@@ -1,20 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  ARM64 cacheinfo support
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  *
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  *  Copyright (C) 2015 ARM Ltd.
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  *  All Rights Reserved
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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- * kind, whether express or implied; without even the implied warranty
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- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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8
 
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 #include <linux/acpi.h>
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@@ -27,6 +16,15 @@
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 #define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
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 #define CLIDR_CTYPE(clidr, level)	\
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 	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
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+
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+int cache_line_size(void)
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+{
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+	if (coherency_max_size != 0)
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+		return coherency_max_size;
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+
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+	return cache_line_size_of_cpu();
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+}
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+EXPORT_SYMBOL_GPL(cache_line_size);
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 static inline enum cache_type get_cache_type(int level)
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 {
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@@ -47,7 +45,8 @@
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 int init_cache_level(unsigned int cpu)
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 {
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-	unsigned int ctype, level, leaves, fw_level;
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+	unsigned int ctype, level, leaves;
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+	int fw_level;
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 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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 	for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
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@@ -65,6 +64,9 @@
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 	else
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 		fw_level = acpi_find_last_cache_level(cpu);
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+	if (fw_level < 0)
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+		return fw_level;
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+
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 	if (level < fw_level) {
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 		/*
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 		 * some external caches not specified in CLIDR_EL1