disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/arm64/boot/dts/qcom/ipq8074.dtsi
..
..
@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
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3
  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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4
  */
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5
 
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
..
..
@@ -18,17 +10,226 @@
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 	model = "Qualcomm Technologies, Inc. IPQ8074";
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11
 	compatible = "qcom,ipq8074";
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12
 
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+	clocks {
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+		sleep_clk: sleep_clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <32768>;
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+			#clock-cells = <0>;
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+		};
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+
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+		xo: xo {
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+			compatible = "fixed-clock";
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+			clock-frequency = <19200000>;
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+			#clock-cells = <0>;
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+		};
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+	};
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+
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+	cpus {
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+		#address-cells = <0x1>;
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+		#size-cells = <0x0>;
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+
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+		CPU0: cpu@0 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			reg = <0x0>;
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+			next-level-cache = <&L2_0>;
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+			enable-method = "psci";
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+		};
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+
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+		CPU1: cpu@1 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			enable-method = "psci";
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+			reg = <0x1>;
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+			next-level-cache = <&L2_0>;
45
+		};
46
+
47
+		CPU2: cpu@2 {
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+			device_type = "cpu";
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+			compatible = "arm,cortex-a53";
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+			enable-method = "psci";
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+			reg = <0x2>;
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+			next-level-cache = <&L2_0>;
53
+		};
54
+
55
+		CPU3: cpu@3 {
56
+			device_type = "cpu";
57
+			compatible = "arm,cortex-a53";
58
+			enable-method = "psci";
59
+			reg = <0x3>;
60
+			next-level-cache = <&L2_0>;
61
+		};
62
+
63
+		L2_0: l2-cache {
64
+			compatible = "cache";
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+			cache-level = <0x2>;
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+		};
67
+	};
68
+
69
+	pmu {
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+		compatible = "arm,cortex-a53-pmu";
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+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
72
+	};
73
+
74
+	psci {
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+		compatible = "arm,psci-1.0";
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+		method = "smc";
77
+	};
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+
21
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 	soc: soc {
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80
 		#address-cells = <0x1>;
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81
 		#size-cells = <0x1>;
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 		ranges = <0 0 0 0xffffffff>;
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83
 		compatible = "simple-bus";
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84
 
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+		ssphy_1: phy@58000 {
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+			compatible = "qcom,ipq8074-qmp-usb3-phy";
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+			reg = <0x00058000 0x1c4>;
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+			#clock-cells = <1>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
92
+
93
+			clocks = <&gcc GCC_USB1_AUX_CLK>,
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+				<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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+				<&xo>;
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+			clock-names = "aux", "cfg_ahb", "ref";
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+
98
+			resets =  <&gcc GCC_USB1_PHY_BCR>,
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+				<&gcc GCC_USB3PHY_1_PHY_BCR>;
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+			reset-names = "phy","common";
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+			status = "disabled";
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+
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+			usb1_ssphy: lane@58200 {
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+				reg = <0x00058200 0x130>,       /* Tx */
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+				      <0x00058400 0x200>,     /* Rx */
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+				      <0x00058800 0x1f8>,     /* PCS  */
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+				      <0x00058600 0x044>;     /* PCS misc*/
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+				#phy-cells = <0>;
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+				clocks = <&gcc GCC_USB1_PIPE_CLK>;
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+				clock-names = "pipe0";
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+				clock-output-names = "usb3phy_1_cc_pipe_clk";
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+			};
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+		};
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+
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+		qusb_phy_1: phy@59000 {
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+			compatible = "qcom,ipq8074-qusb2-phy";
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+			reg = <0x00059000 0x180>;
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+			#phy-cells = <0>;
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+
120
+			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
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+				 <&xo>;
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+			clock-names = "cfg_ahb", "ref";
123
+
124
+			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
125
+			status = "disabled";
126
+		};
127
+
128
+		ssphy_0: phy@78000 {
129
+			compatible = "qcom,ipq8074-qmp-usb3-phy";
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+			reg = <0x00078000 0x1c4>;
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+			#clock-cells = <1>;
132
+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
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+
136
+			clocks = <&gcc GCC_USB0_AUX_CLK>,
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+				<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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+				<&xo>;
139
+			clock-names = "aux", "cfg_ahb", "ref";
140
+
141
+			resets =  <&gcc GCC_USB0_PHY_BCR>,
142
+				<&gcc GCC_USB3PHY_0_PHY_BCR>;
143
+			reset-names = "phy","common";
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+			status = "disabled";
145
+
146
+			usb0_ssphy: lane@78200 {
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+				reg = <0x00078200 0x130>,       /* Tx */
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+				      <0x00078400 0x200>,     /* Rx */
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+				      <0x00078800 0x1f8>,     /* PCS  */
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+				      <0x00078600 0x044>;     /* PCS misc*/
151
+				#phy-cells = <0>;
152
+				clocks = <&gcc GCC_USB0_PIPE_CLK>;
153
+				clock-names = "pipe0";
154
+				clock-output-names = "usb3phy_0_cc_pipe_clk";
155
+			};
156
+		};
157
+
158
+		qusb_phy_0: phy@79000 {
159
+			compatible = "qcom,ipq8074-qusb2-phy";
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+			reg = <0x00079000 0x180>;
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+			#phy-cells = <0>;
162
+
163
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
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+				 <&xo>;
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+			clock-names = "cfg_ahb", "ref";
166
+
167
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
168
+		};
169
+
170
+		pcie_qmp0: phy@84000 {
171
+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
172
+			reg = <0x00084000 0x1bc>;
173
+			#address-cells = <1>;
174
+			#size-cells = <1>;
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+			ranges;
176
+
177
+			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
178
+				<&gcc GCC_PCIE0_AHB_CLK>;
179
+			clock-names = "aux", "cfg_ahb";
180
+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
181
+				<&gcc GCC_PCIE0PHY_PHY_BCR>;
182
+			reset-names = "phy",
183
+				      "common";
184
+			status = "disabled";
185
+
186
+			pcie_phy0: phy@84200 {
187
+				reg = <0x84200 0x16c>,
188
+				      <0x84400 0x200>,
189
+				      <0x84800 0x1f0>,
190
+				      <0x84c00 0xf4>;
191
+				#phy-cells = <0>;
192
+				#clock-cells = <0>;
193
+				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
194
+				clock-names = "pipe0";
195
+				clock-output-names = "pcie20_phy0_pipe_clk";
196
+			};
197
+		};
198
+
199
+		pcie_qmp1: phy@8e000 {
200
+			compatible = "qcom,ipq8074-qmp-pcie-phy";
201
+			reg = <0x0008e000 0x1c4>;
202
+			#address-cells = <1>;
203
+			#size-cells = <1>;
204
+			ranges;
205
+
206
+			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
207
+				<&gcc GCC_PCIE1_AHB_CLK>;
208
+			clock-names = "aux", "cfg_ahb";
209
+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
210
+				<&gcc GCC_PCIE1PHY_PHY_BCR>;
211
+			reset-names = "phy",
212
+				      "common";
213
+			status = "disabled";
214
+
215
+			pcie_phy1: phy@8e200 {
216
+				reg = <0x8e200 0x130>,
217
+				      <0x8e400 0x200>,
218
+				      <0x8e800 0x1f8>;
219
+				#phy-cells = <0>;
220
+				#clock-cells = <0>;
221
+				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
222
+				clock-names = "pipe0";
223
+				clock-output-names = "pcie20_phy1_pipe_clk";
224
+			};
225
+		};
226
+
27
227
 		tlmm: pinctrl@1000000 {
28
228
 			compatible = "qcom,ipq8074-pinctrl";
29
-			reg = <0x1000000 0x300000>;
229
+			reg = <0x01000000 0x300000>;
30
230
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
31
231
 			gpio-controller;
232
+			gpio-ranges = <&tlmm 0 0 70>;
32
233
 			#gpio-cells = <0x2>;
33
234
 			interrupt-controller;
34
235
 			#interrupt-cells = <0x2>;
..
..
@@ -73,102 +274,38 @@
73
274
 			};
74
275
 		};
75
276
 
76
-		intc: interrupt-controller@b000000 {
77
-			compatible = "qcom,msm-qgic2";
78
-			interrupt-controller;
79
-			#interrupt-cells = <0x3>;
80
-			reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
81
-		};
82
-
83
-		timer {
84
-			compatible = "arm,armv8-timer";
85
-			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86
-				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87
-				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88
-				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
89
-		};
90
-
91
-		timer@b120000 {
92
-			#address-cells = <1>;
93
-			#size-cells = <1>;
94
-			ranges;
95
-			compatible = "arm,armv7-timer-mem";
96
-			reg = <0xb120000 0x1000>;
97
-			clock-frequency = <19200000>;
98
-
99
-			frame@b120000 {
100
-				frame-number = <0>;
101
-				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
102
-					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
103
-				reg = <0xb121000 0x1000>,
104
-				      <0xb122000 0x1000>;
105
-			};
106
-
107
-			frame@b123000 {
108
-				frame-number = <1>;
109
-				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
110
-				reg = <0xb123000 0x1000>;
111
-				status = "disabled";
112
-			};
113
-
114
-			frame@b124000 {
115
-				frame-number = <2>;
116
-				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
117
-				reg = <0xb124000 0x1000>;
118
-				status = "disabled";
119
-			};
120
-
121
-			frame@b125000 {
122
-				frame-number = <3>;
123
-				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
124
-				reg = <0xb125000 0x1000>;
125
-				status = "disabled";
126
-			};
127
-
128
-			frame@b126000 {
129
-				frame-number = <4>;
130
-				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
131
-				reg = <0xb126000 0x1000>;
132
-				status = "disabled";
133
-			};
134
-
135
-			frame@b127000 {
136
-				frame-number = <5>;
137
-				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
138
-				reg = <0xb127000 0x1000>;
139
-				status = "disabled";
140
-			};
141
-
142
-			frame@b128000 {
143
-				frame-number = <6>;
144
-				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
145
-				reg = <0xb128000 0x1000>;
146
-				status = "disabled";
147
-			};
148
-		};
149
-
150
277
 		gcc: gcc@1800000 {
151
278
 			compatible = "qcom,gcc-ipq8074";
152
-			reg = <0x1800000 0x80000>;
279
+			reg = <0x01800000 0x80000>;
153
280
 			#clock-cells = <0x1>;
154
281
 			#reset-cells = <0x1>;
155
282
 		};
156
283
 
157
-		blsp1_uart5: serial@78b3000 {
158
-			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
159
-			reg = <0x78b3000 0x200>;
160
-			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
161
-			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
162
-				 <&gcc GCC_BLSP1_AHB_CLK>;
163
-			clock-names = "core", "iface";
164
-			pinctrl-0 = <&serial_4_pins>;
165
-			pinctrl-names = "default";
284
+		sdhc_1: sdhci@7824900 {
285
+			compatible = "qcom,sdhci-msm-v4";
286
+			reg = <0x7824900 0x500>, <0x7824000 0x800>;
287
+			reg-names = "hc_mem", "core_mem";
288
+
289
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
290
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
291
+			interrupt-names = "hc_irq", "pwr_irq";
292
+
293
+			clocks = <&xo>,
294
+				 <&gcc GCC_SDCC1_AHB_CLK>,
295
+				 <&gcc GCC_SDCC1_APPS_CLK>;
296
+			clock-names = "xo", "iface", "core";
297
+			max-frequency = <384000000>;
298
+			mmc-ddr-1_8v;
299
+			mmc-hs200-1_8v;
300
+			mmc-hs400-1_8v;
301
+			bus-width = <8>;
302
+
166
303
 			status = "disabled";
167
304
 		};
168
305
 
169
306
 		blsp_dma: dma@7884000 {
170
307
 			compatible = "qcom,bam-v1.7.0";
171
-			reg = <0x7884000 0x2b000>;
308
+			reg = <0x07884000 0x2b000>;
172
309
 			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
173
310
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
174
311
 			clock-names = "bam_clk";
..
..
@@ -178,7 +315,7 @@
178
315
 
179
316
 		blsp1_uart1: serial@78af000 {
180
317
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
181
-			reg = <0x78af000 0x200>;
318
+			reg = <0x078af000 0x200>;
182
319
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
183
320
 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
184
321
 				 <&gcc GCC_BLSP1_AHB_CLK>;
..
..
@@ -188,7 +325,7 @@
188
325
 
189
326
 		blsp1_uart3: serial@78b1000 {
190
327
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
191
-			reg = <0x78b1000 0x200>;
328
+			reg = <0x078b1000 0x200>;
192
329
 			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
193
330
 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
194
331
 				<&gcc GCC_BLSP1_AHB_CLK>;
..
..
@@ -201,11 +338,23 @@
201
338
 			status = "disabled";
202
339
 		};
203
340
 
341
+		blsp1_uart5: serial@78b3000 {
342
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
343
+			reg = <0x078b3000 0x200>;
344
+			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
345
+			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
346
+				 <&gcc GCC_BLSP1_AHB_CLK>;
347
+			clock-names = "core", "iface";
348
+			pinctrl-0 = <&serial_4_pins>;
349
+			pinctrl-names = "default";
350
+			status = "disabled";
351
+		};
352
+
204
353
 		blsp1_spi1: spi@78b5000 {
205
354
 			compatible = "qcom,spi-qup-v2.2.1";
206
355
 			#address-cells = <1>;
207
356
 			#size-cells = <0>;
208
-			reg = <0x78b5000 0x600>;
357
+			reg = <0x078b5000 0x600>;
209
358
 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
210
359
 			spi-max-frequency = <50000000>;
211
360
 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
..
..
@@ -222,7 +371,7 @@
222
371
 			compatible = "qcom,i2c-qup-v2.2.1";
223
372
 			#address-cells = <1>;
224
373
 			#size-cells = <0>;
225
-			reg = <0x78b6000 0x600>;
374
+			reg = <0x078b6000 0x600>;
226
375
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
227
376
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
228
377
 				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
..
..
@@ -239,7 +388,7 @@
239
388
 			compatible = "qcom,i2c-qup-v2.2.1";
240
389
 			#address-cells = <1>;
241
390
 			#size-cells = <0>;
242
-			reg = <0x78b7000 0x600>;
391
+			reg = <0x078b7000 0x600>;
243
392
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
244
393
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
245
394
 				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
..
..
@@ -252,7 +401,7 @@
252
401
 
253
402
 		qpic_bam: dma@7984000 {
254
403
 			compatible = "qcom,bam-v1.7.0";
255
-			reg = <0x7984000 0x1a000>;
404
+			reg = <0x07984000 0x1a000>;
256
405
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
257
406
 			clocks = <&gcc GCC_QPIC_AHB_CLK>;
258
407
 			clock-names = "bam_clk";
..
..
@@ -261,9 +410,9 @@
261
410
 			status = "disabled";
262
411
 		};
263
412
 
264
-		qpic_nand: nand@79b0000 {
413
+		qpic_nand: nand-controller@79b0000 {
265
414
 			compatible = "qcom,ipq8074-nand";
266
-			reg = <0x79b0000 0x10000>;
415
+			reg = <0x079b0000 0x10000>;
267
416
 			#address-cells = <1>;
268
417
 			#size-cells = <0>;
269
418
 			clocks = <&gcc GCC_QPIC_CLK>,
..
..
@@ -279,105 +428,174 @@
279
428
 			status = "disabled";
280
429
 		};
281
430
 
282
-		pcie_phy0: phy@86000 {
283
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
284
-			reg = <0x86000 0x1000>;
285
-			#phy-cells = <0>;
286
-			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
287
-			clock-names = "pipe_clk";
288
-			clock-output-names = "pcie20_phy0_pipe_clk";
431
+		usb_0: usb@8af8800 {
432
+			compatible = "qcom,dwc3";
433
+			reg = <0x08af8800 0x400>;
434
+			#address-cells = <1>;
435
+			#size-cells = <1>;
436
+			ranges;
289
437
 
290
-			resets = <&gcc GCC_PCIE0_PHY_BCR>,
291
-				<&gcc GCC_PCIE0PHY_PHY_BCR>;
292
-			reset-names = "phy",
293
-				      "common";
438
+			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
439
+				<&gcc GCC_USB0_MASTER_CLK>,
440
+				<&gcc GCC_USB0_SLEEP_CLK>,
441
+				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
442
+			clock-names = "sys_noc_axi",
443
+				"master",
444
+				"sleep",
445
+				"mock_utmi";
446
+
447
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
448
+					  <&gcc GCC_USB0_MASTER_CLK>,
449
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
450
+			assigned-clock-rates = <133330000>,
451
+						<133330000>,
452
+						<19200000>;
453
+
454
+			resets = <&gcc GCC_USB0_BCR>;
294
455
 			status = "disabled";
456
+
457
+			dwc_0: dwc3@8a00000 {
458
+				compatible = "snps,dwc3";
459
+				reg = <0x8a00000 0xcd00>;
460
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
461
+				phys = <&qusb_phy_0>, <&usb0_ssphy>;
462
+				phy-names = "usb2-phy", "usb3-phy";
463
+				snps,is-utmi-l1-suspend;
464
+				snps,hird-threshold = /bits/ 8 <0x0>;
465
+				snps,dis_u2_susphy_quirk;
466
+				snps,dis_u3_susphy_quirk;
467
+				dr_mode = "host";
468
+			};
295
469
 		};
296
470
 
297
-		pcie0: pci@20000000 {
298
-			compatible = "qcom,pcie-ipq8074";
299
-			reg =  <0x20000000 0xf1d
300
-				0x20000f20 0xa8
301
-				0x80000 0x2000
302
-				0x20100000 0x1000>;
303
-			reg-names = "dbi", "elbi", "parf", "config";
304
-			device_type = "pci";
305
-			linux,pci-domain = <0>;
306
-			bus-range = <0x00 0xff>;
307
-			num-lanes = <1>;
308
-			#address-cells = <3>;
309
-			#size-cells = <2>;
471
+		usb_1: usb@8cf8800 {
472
+			compatible = "qcom,dwc3";
473
+			reg = <0x08cf8800 0x400>;
474
+			#address-cells = <1>;
475
+			#size-cells = <1>;
476
+			ranges;
310
477
 
311
-			phys = <&pcie_phy0>;
312
-			phy-names = "pciephy";
478
+			clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
479
+				<&gcc GCC_USB1_MASTER_CLK>,
480
+				<&gcc GCC_USB1_SLEEP_CLK>,
481
+				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
482
+			clock-names = "sys_noc_axi",
483
+				"master",
484
+				"sleep",
485
+				"mock_utmi";
313
486
 
314
-			ranges = <0x81000000 0 0x20200000 0x20200000
315
-				  0 0x100000   /* downstream I/O */
316
-				  0x82000000 0 0x20300000 0x20300000
317
-				  0 0xd00000>; /* non-prefetchable memory */
487
+			assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
488
+					  <&gcc GCC_USB1_MASTER_CLK>,
489
+					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
490
+			assigned-clock-rates = <133330000>,
491
+						<133330000>,
492
+						<19200000>;
318
493
 
319
-			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
320
-			interrupt-names = "msi";
321
-			#interrupt-cells = <1>;
322
-			interrupt-map-mask = <0 0 0 0x7>;
323
-			interrupt-map = <0 0 0 1 &intc 0 75
324
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
325
-					<0 0 0 2 &intc 0 78
326
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
327
-					<0 0 0 3 &intc 0 79
328
-					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
329
-					<0 0 0 4 &intc 0 83
330
-					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
331
-
332
-			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
333
-				 <&gcc GCC_PCIE0_AXI_M_CLK>,
334
-				 <&gcc GCC_PCIE0_AXI_S_CLK>,
335
-				 <&gcc GCC_PCIE0_AHB_CLK>,
336
-				 <&gcc GCC_PCIE0_AUX_CLK>;
337
-
338
-			clock-names = "iface",
339
-				      "axi_m",
340
-				      "axi_s",
341
-				      "ahb",
342
-				      "aux";
343
-			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
344
-				 <&gcc GCC_PCIE0_SLEEP_ARES>,
345
-				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
346
-				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
347
-				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
348
-				 <&gcc GCC_PCIE0_AHB_ARES>,
349
-				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
350
-			reset-names = "pipe",
351
-				      "sleep",
352
-				      "sticky",
353
-				      "axi_m",
354
-				      "axi_s",
355
-				      "ahb",
356
-				      "axi_m_sticky";
494
+			resets = <&gcc GCC_USB1_BCR>;
357
495
 			status = "disabled";
496
+
497
+			dwc_1: dwc3@8c00000 {
498
+				compatible = "snps,dwc3";
499
+				reg = <0x8c00000 0xcd00>;
500
+				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
501
+				phys = <&qusb_phy_1>, <&usb1_ssphy>;
502
+				phy-names = "usb2-phy", "usb3-phy";
503
+				snps,is-utmi-l1-suspend;
504
+				snps,hird-threshold = /bits/ 8 <0x0>;
505
+				snps,dis_u2_susphy_quirk;
506
+				snps,dis_u3_susphy_quirk;
507
+				dr_mode = "host";
508
+			};
358
509
 		};
359
510
 
360
-		pcie_phy1: phy@8e000 {
361
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
362
-			reg = <0x8e000 0x1000>;
363
-			#phy-cells = <0>;
364
-			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
365
-			clock-names = "pipe_clk";
366
-			clock-output-names = "pcie20_phy1_pipe_clk";
511
+		intc: interrupt-controller@b000000 {
512
+			compatible = "qcom,msm-qgic2";
513
+			interrupt-controller;
514
+			#interrupt-cells = <0x3>;
515
+			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
516
+		};
367
517
 
368
-			resets = <&gcc GCC_PCIE1_PHY_BCR>,
369
-				<&gcc GCC_PCIE1PHY_PHY_BCR>;
370
-			reset-names = "phy",
371
-				      "common";
372
-			status = "disabled";
518
+		timer {
519
+			compatible = "arm,armv8-timer";
520
+			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
521
+				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
522
+				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
523
+				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
524
+		};
525
+
526
+		watchdog: watchdog@b017000 {
527
+			compatible = "qcom,kpss-wdt";
528
+			reg = <0xb017000 0x1000>;
529
+			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
530
+			clocks = <&sleep_clk>;
531
+			timeout-sec = <30>;
532
+		};
533
+
534
+		timer@b120000 {
535
+			#address-cells = <1>;
536
+			#size-cells = <1>;
537
+			ranges;
538
+			compatible = "arm,armv7-timer-mem";
539
+			reg = <0x0b120000 0x1000>;
540
+			clock-frequency = <19200000>;
541
+
542
+			frame@b120000 {
543
+				frame-number = <0>;
544
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
545
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
546
+				reg = <0x0b121000 0x1000>,
547
+				      <0x0b122000 0x1000>;
548
+			};
549
+
550
+			frame@b123000 {
551
+				frame-number = <1>;
552
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
553
+				reg = <0x0b123000 0x1000>;
554
+				status = "disabled";
555
+			};
556
+
557
+			frame@b124000 {
558
+				frame-number = <2>;
559
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
560
+				reg = <0x0b124000 0x1000>;
561
+				status = "disabled";
562
+			};
563
+
564
+			frame@b125000 {
565
+				frame-number = <3>;
566
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
567
+				reg = <0x0b125000 0x1000>;
568
+				status = "disabled";
569
+			};
570
+
571
+			frame@b126000 {
572
+				frame-number = <4>;
573
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
574
+				reg = <0x0b126000 0x1000>;
575
+				status = "disabled";
576
+			};
577
+
578
+			frame@b127000 {
579
+				frame-number = <5>;
580
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
581
+				reg = <0x0b127000 0x1000>;
582
+				status = "disabled";
583
+			};
584
+
585
+			frame@b128000 {
586
+				frame-number = <6>;
587
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
588
+				reg = <0x0b128000 0x1000>;
589
+				status = "disabled";
590
+			};
373
591
 		};
374
592
 
375
593
 		pcie1: pci@10000000 {
376
594
 			compatible = "qcom,pcie-ipq8074";
377
-			reg =  <0x10000000 0xf1d
378
-				0x10000f20 0xa8
379
-				0x88000 0x2000
380
-				0x10100000 0x1000>;
595
+			reg =  <0x10000000 0xf1d>,
596
+			       <0x10000f20 0xa8>,
597
+			       <0x00088000 0x2000>,
598
+			       <0x10100000 0x1000>;
381
599
 			reg-names = "dbi", "elbi", "parf", "config";
382
600
 			device_type = "pci";
383
601
 			linux,pci-domain = <1>;
..
..
@@ -389,10 +607,8 @@
389
607
 			phys = <&pcie_phy1>;
390
608
 			phy-names = "pciephy";
391
609
 
392
-			ranges = <0x81000000 0 0x10200000 0x10200000
393
-				  0 0x100000   /* downstream I/O */
394
-				  0x82000000 0 0x10300000 0x10300000
395
-				  0 0xd00000>; /* non-prefetchable memory */
610
+			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
611
+				 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
396
612
 
397
613
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
398
614
 			interrupt-names = "msi";
..
..
@@ -433,71 +649,70 @@
433
649
 				      "axi_m_sticky";
434
650
 			status = "disabled";
435
651
 		};
436
-	};
437
652
 
438
-	cpus {
439
-		#address-cells = <0x1>;
440
-		#size-cells = <0x0>;
653
+		pcie0: pci@20000000 {
654
+			compatible = "qcom,pcie-ipq8074-gen3";
655
+			reg = <0x20000000 0xf1d>,
656
+			      <0x20000f20 0xa8>,
657
+			      <0x20001000 0x1000>,
658
+			      <0x00080000 0x4000>,
659
+			      <0x20100000 0x1000>;
660
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
661
+			device_type = "pci";
662
+			linux,pci-domain = <0>;
663
+			bus-range = <0x00 0xff>;
664
+			num-lanes = <1>;
665
+			max-link-speed = <3>;
666
+			#address-cells = <3>;
667
+			#size-cells = <2>;
441
668
 
442
-		CPU0: cpu@0 {
443
-			device_type = "cpu";
444
-			compatible = "arm,cortex-a53", "arm,armv8";
445
-			reg = <0x0>;
446
-			next-level-cache = <&L2_0>;
447
-			enable-method = "psci";
448
-		};
669
+			phys = <&pcie_phy0>;
670
+			phy-names = "pciephy";
449
671
 
450
-		CPU1: cpu@1 {
451
-			device_type = "cpu";
452
-			compatible = "arm,cortex-a53", "arm,armv8";
453
-			enable-method = "psci";
454
-			reg = <0x1>;
455
-			next-level-cache = <&L2_0>;
456
-		};
672
+			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
673
+				 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
457
674
 
458
-		CPU2: cpu@2 {
459
-			device_type = "cpu";
460
-			compatible = "arm,cortex-a53", "arm,armv8";
461
-			enable-method = "psci";
462
-			reg = <0x2>;
463
-			next-level-cache = <&L2_0>;
464
-		};
675
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
676
+			interrupt-names = "msi";
677
+			#interrupt-cells = <1>;
678
+			interrupt-map-mask = <0 0 0 0x7>;
679
+			interrupt-map = <0 0 0 1 &intc 0 75
680
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
681
+					<0 0 0 2 &intc 0 78
682
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
683
+					<0 0 0 3 &intc 0 79
684
+					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
685
+					<0 0 0 4 &intc 0 83
686
+					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
465
687
 
466
-		CPU3: cpu@3 {
467
-			device_type = "cpu";
468
-			compatible = "arm,cortex-a53", "arm,armv8";
469
-			enable-method = "psci";
470
-			reg = <0x3>;
471
-			next-level-cache = <&L2_0>;
472
-		};
688
+			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
689
+				 <&gcc GCC_PCIE0_AXI_M_CLK>,
690
+				 <&gcc GCC_PCIE0_AXI_S_CLK>,
691
+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
692
+				 <&gcc GCC_PCIE0_RCHNG_CLK>;
693
+			clock-names = "iface",
694
+				      "axi_m",
695
+				      "axi_s",
696
+				      "axi_bridge",
697
+				      "rchng";
473
698
 
474
-		L2_0: l2-cache {
475
-			compatible = "cache";
476
-			cache-level = <0x2>;
477
-		};
478
-	};
479
-
480
-	psci {
481
-		compatible = "arm,psci-1.0";
482
-		method = "smc";
483
-	};
484
-
485
-	pmu {
486
-		compatible = "arm,armv8-pmuv3";
487
-		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
488
-	};
489
-
490
-	clocks {
491
-		sleep_clk: sleep_clk {
492
-			compatible = "fixed-clock";
493
-			clock-frequency = <32000>;
494
-			#clock-cells = <0>;
495
-		};
496
-
497
-		xo: xo {
498
-			compatible = "fixed-clock";
499
-			clock-frequency = <19200000>;
500
-			#clock-cells = <0>;
699
+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
700
+				 <&gcc GCC_PCIE0_SLEEP_ARES>,
701
+				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
702
+				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
703
+				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
704
+				 <&gcc GCC_PCIE0_AHB_ARES>,
705
+				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
706
+				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
707
+			reset-names = "pipe",
708
+				      "sleep",
709
+				      "sticky",
710
+				      "axi_m",
711
+				      "axi_s",
712
+				      "ahb",
713
+				      "axi_m_sticky",
714
+				      "axi_s_sticky";
715
+			status = "disabled";
501
716
 		};
502
717
 	};
503
718
 };