forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi
....@@ -3,8 +3,11 @@
33 #include <dt-bindings/gpio/tegra-gpio.h>
44 #include <dt-bindings/memory/tegra210-mc.h>
55 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7
+#include <dt-bindings/reset/tegra210-car.h>
68 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 #include <dt-bindings/thermal/tegra124-soctherm.h>
10
+#include <dt-bindings/soc/tegra-pmc.h>
811 
912 / {
1013 	compatible = "nvidia,tegra210";
....@@ -15,9 +18,9 @@
1518 	pcie@1003000 {
1619 		compatible = "nvidia,tegra210-pcie";
1720 		device_type = "pci";
18
-		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
19
-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
20
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21
+		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22
+		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23
+		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
2124 		reg-names = "pads", "afi", "cs";
2225 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2326 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
....@@ -31,11 +34,11 @@
3134 		#address-cells = <3>;
3235 		#size-cells = <2>;
3336 
34
-		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
35
-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
36
-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
37
-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
38
-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
37
+		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38
+			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39
+			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40
+			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41
+			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
3942 
4043 		clocks = <&tegra_car TEGRA210_CLK_PCIE>,
4144 			 <&tegra_car TEGRA210_CLK_AFI>,
....@@ -46,6 +49,11 @@
4649 			 <&tegra_car 72>,
4750 			 <&tegra_car 74>;
4851 		reset-names = "pex", "afi", "pcie_x";
52
+
53
+		pinctrl-names = "default", "idle";
54
+		pinctrl-0 = <&pex_dpd_disable>;
55
+		pinctrl-1 = <&pex_dpd_enable>;
56
+
4957 		status = "disabled";
5058 
5159 		pci@1,0 {
....@@ -78,10 +86,11 @@
7886 	};
7987 
8088 	host1x@50000000 {
81
-		compatible = "nvidia,tegra210-host1x", "simple-bus";
89
+		compatible = "nvidia,tegra210-host1x";
8290 		reg = <0x0 0x50000000 0x0 0x00034000>;
8391 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
8492 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93
+		interrupt-names = "syncpt", "host1x";
8594 		clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
8695 		clock-names = "host1x";
8796 		resets = <&tegra_car 28>;
....@@ -129,9 +138,44 @@
129138 
130139 		vi@54080000 {
131140 			compatible = "nvidia,tegra210-vi";
132
-			reg = <0x0 0x54080000 0x0 0x00040000>;
141
+			reg = <0x0 0x54080000 0x0 0x700>;
133142 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
134143 			status = "disabled";
144
+			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145
+			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146
+
147
+			clocks = <&tegra_car TEGRA210_CLK_VI>;
148
+			power-domains = <&pd_venc>;
149
+
150
+			#address-cells = <1>;
151
+			#size-cells = <1>;
152
+
153
+			ranges = <0x0 0x0 0x54080000 0x2000>;
154
+
155
+			csi@838 {
156
+				compatible = "nvidia,tegra210-csi";
157
+				reg = <0x838 0x1300>;
158
+				status = "disabled";
159
+				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160
+						  <&tegra_car TEGRA210_CLK_CILCD>,
161
+						  <&tegra_car TEGRA210_CLK_CILE>,
162
+						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
163
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164
+							 <&tegra_car TEGRA210_CLK_PLL_P>,
165
+							 <&tegra_car TEGRA210_CLK_PLL_P>;
166
+				assigned-clock-rates = <102000000>,
167
+						       <102000000>,
168
+						       <102000000>,
169
+						       <972000000>;
170
+
171
+				clocks = <&tegra_car TEGRA210_CLK_CSI>,
172
+					 <&tegra_car TEGRA210_CLK_CILAB>,
173
+					 <&tegra_car TEGRA210_CLK_CILCD>,
174
+					 <&tegra_car TEGRA210_CLK_CILE>,
175
+					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176
+				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177
+				power-domains = <&pd_sor>;
178
+			};
135179 		};
136180 
137181 		tsec@54100000 {
....@@ -143,14 +187,14 @@
143187 			compatible = "nvidia,tegra210-dc";
144188 			reg = <0x0 0x54200000 0x0 0x00040000>;
145189 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
146
-			clocks = <&tegra_car TEGRA210_CLK_DISP1>,
147
-				 <&tegra_car TEGRA210_CLK_PLL_P>;
148
-			clock-names = "dc", "parent";
190
+			clocks = <&tegra_car TEGRA210_CLK_DISP1>;
191
+			clock-names = "dc";
149192 			resets = <&tegra_car 27>;
150193 			reset-names = "dc";
151194 
152195 			iommus = <&mc TEGRA_SWGROUP_DC>;
153196 
197
+			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
154198 			nvidia,head = <0>;
155199 		};
156200 
....@@ -158,18 +202,18 @@
158202 			compatible = "nvidia,tegra210-dc";
159203 			reg = <0x0 0x54240000 0x0 0x00040000>;
160204 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
161
-			clocks = <&tegra_car TEGRA210_CLK_DISP2>,
162
-				 <&tegra_car TEGRA210_CLK_PLL_P>;
163
-			clock-names = "dc", "parent";
205
+			clocks = <&tegra_car TEGRA210_CLK_DISP2>;
206
+			clock-names = "dc";
164207 			resets = <&tegra_car 26>;
165208 			reset-names = "dc";
166209 
167210 			iommus = <&mc TEGRA_SWGROUP_DCB>;
168211 
212
+			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
169213 			nvidia,head = <1>;
170214 		};
171215 
172
-		dsi@54300000 {
216
+		dsia: dsi@54300000 {
173217 			compatible = "nvidia,tegra210-dsi";
174218 			reg = <0x0 0x54300000 0x0 0x00040000>;
175219 			clocks = <&tegra_car TEGRA210_CLK_DSIA>,
....@@ -206,7 +250,7 @@
206250 			status = "disabled";
207251 		};
208252 
209
-		dsi@54400000 {
253
+		dsib: dsi@54400000 {
210254 			compatible = "nvidia,tegra210-dsi";
211255 			reg = <0x0 0x54400000 0x0 0x00040000>;
212256 			clocks = <&tegra_car TEGRA210_CLK_DSIB>,
....@@ -242,15 +286,16 @@
242286 			status = "disabled";
243287 		};
244288 
245
-		sor@54540000 {
289
+		sor0: sor@54540000 {
246290 			compatible = "nvidia,tegra210-sor";
247291 			reg = <0x0 0x54540000 0x0 0x00040000>;
248292 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
249293 			clocks = <&tegra_car TEGRA210_CLK_SOR0>,
294
+				 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
250295 				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
251296 				 <&tegra_car TEGRA210_CLK_PLL_DP>,
252297 				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
253
-			clock-names = "sor", "parent", "dp", "safe";
298
+			clock-names = "sor", "out", "parent", "dp", "safe";
254299 			resets = <&tegra_car 182>;
255300 			reset-names = "sor";
256301 			pinctrl-0 = <&state_dpaux_aux>;
....@@ -261,7 +306,7 @@
261306 			status = "disabled";
262307 		};
263308 
264
-		sor@54580000 {
309
+		sor1: sor@54580000 {
265310 			compatible = "nvidia,tegra210-sor1";
266311 			reg = <0x0 0x54580000 0x0 0x00040000>;
267312 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
....@@ -282,7 +327,7 @@
282327 		};
283328 
284329 		dpaux: dpaux@545c0000 {
285
-			compatible = "nvidia,tegra124-dpaux";
330
+			compatible = "nvidia,tegra210-dpaux";
286331 			reg = <0x0 0x545c0000 0x0 0x00040000>;
287332 			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
288333 			clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
....@@ -318,6 +363,9 @@
318363 			compatible = "nvidia,tegra210-isp";
319364 			reg = <0x0 0x54600000 0x0 0x00040000>;
320365 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
366
+			clocks = <&tegra_car TEGRA210_CLK_ISPA>;
367
+			resets = <&tegra_car 23>;
368
+			reset-names = "isp";
321369 			status = "disabled";
322370 		};
323371 
....@@ -325,6 +373,9 @@
325373 			compatible = "nvidia,tegra210-isp";
326374 			reg = <0x0 0x54680000 0x0 0x00040000>;
327375 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
376
+			clocks = <&tegra_car TEGRA210_CLK_ISPB>;
377
+			resets = <&tegra_car 3>;
378
+			reset-names = "isp";
328379 			status = "disabled";
329380 		};
330381 
....@@ -332,7 +383,16 @@
332383 			compatible = "nvidia,tegra210-i2c-vi";
333384 			reg = <0x0 0x546c0000 0x0 0x00040000>;
334385 			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
386
+			clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
387
+				 <&tegra_car TEGRA210_CLK_I2CSLOW>;
388
+			clock-names = "div-clk", "slow";
389
+			resets = <&tegra_car 208>;
390
+			reset-names = "i2c";
391
+			power-domains = <&pd_venc>;
335392 			status = "disabled";
393
+
394
+			#address-cells = <1>;
395
+			#size-cells = <0>;
336396 		};
337397 	};
338398 
....@@ -382,14 +442,22 @@
382442 	};
383443 
384444 	timer@60005000 {
385
-		compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
445
+		compatible = "nvidia,tegra210-timer";
386446 		reg = <0x0 0x60005000 0x0 0x400>;
387
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
447
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
448
+			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
388449 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
389450 			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
390451 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
391452 			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
392
-			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
453
+			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
454
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
455
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
456
+			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
457
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
458
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
459
+			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
460
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
393461 		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
394462 		clock-names = "timer";
395463 	};
....@@ -468,13 +536,55 @@
468536 	apbmisc@70000800 {
469537 		compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
470538 		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
471
-		      <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
539
+		      <0x0 0x70000008 0x0 0x04>;   /* Strapping options */
472540 	};
473541 
474542 	pinmux: pinmux@700008d4 {
475543 		compatible = "nvidia,tegra210-pinmux";
476544 		reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
477545 		      <0x0 0x70003000 0x0 0x294>; /* Mux registers */
546
+		sdmmc1_3v3_drv: sdmmc1-3v3-drv {
547
+			sdmmc1 {
548
+				nvidia,pins = "drive_sdmmc1";
549
+				nvidia,pull-down-strength = <0x8>;
550
+				nvidia,pull-up-strength = <0x8>;
551
+			};
552
+		};
553
+		sdmmc1_1v8_drv: sdmmc1-1v8-drv {
554
+			sdmmc1 {
555
+				nvidia,pins = "drive_sdmmc1";
556
+				nvidia,pull-down-strength = <0x4>;
557
+				nvidia,pull-up-strength = <0x3>;
558
+			};
559
+		};
560
+		sdmmc2_1v8_drv: sdmmc2-1v8-drv {
561
+			sdmmc2 {
562
+				nvidia,pins = "drive_sdmmc2";
563
+				nvidia,pull-down-strength = <0x10>;
564
+				nvidia,pull-up-strength = <0x10>;
565
+			};
566
+		};
567
+		sdmmc3_3v3_drv: sdmmc3-3v3-drv {
568
+			sdmmc3 {
569
+				nvidia,pins = "drive_sdmmc3";
570
+				nvidia,pull-down-strength = <0x8>;
571
+				nvidia,pull-up-strength = <0x8>;
572
+			};
573
+		};
574
+		sdmmc3_1v8_drv: sdmmc3-1v8-drv {
575
+			sdmmc3 {
576
+				nvidia,pins = "drive_sdmmc3";
577
+				nvidia,pull-down-strength = <0x4>;
578
+				nvidia,pull-up-strength = <0x3>;
579
+			};
580
+		};
581
+		sdmmc4_1v8_drv: sdmmc4-1v8-drv {
582
+			sdmmc4 {
583
+				nvidia,pins = "drive_sdmmc4";
584
+				nvidia,pull-down-strength = <0x10>;
585
+				nvidia,pull-up-strength = <0x10>;
586
+			};
587
+		};
478588 	};
479589 
480590 	/*
....@@ -553,7 +663,7 @@
553663 	};
554664 
555665 	i2c@7000c000 {
556
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
666
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
557667 		reg = <0x0 0x7000c000 0x0 0x100>;
558668 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
559669 		#address-cells = <1>;
....@@ -568,7 +678,7 @@
568678 	};
569679 
570680 	i2c@7000c400 {
571
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
681
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
572682 		reg = <0x0 0x7000c400 0x0 0x100>;
573683 		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
574684 		#address-cells = <1>;
....@@ -583,7 +693,7 @@
583693 	};
584694 
585695 	i2c@7000c500 {
586
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
696
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
587697 		reg = <0x0 0x7000c500 0x0 0x100>;
588698 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
589699 		#address-cells = <1>;
....@@ -598,7 +708,7 @@
598708 	};
599709 
600710 	i2c@7000c700 {
601
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
711
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
602712 		reg = <0x0 0x7000c700 0x0 0x100>;
603713 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
604714 		#address-cells = <1>;
....@@ -616,7 +726,7 @@
616726 	};
617727 
618728 	i2c@7000d000 {
619
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
729
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
620730 		reg = <0x0 0x7000d000 0x0 0x100>;
621731 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
622732 		#address-cells = <1>;
....@@ -631,7 +741,7 @@
631741 	};
632742 
633743 	i2c@7000d100 {
634
-		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
744
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
635745 		reg = <0x0 0x7000d100 0x0 0x100>;
636746 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
637747 		#address-cells = <1>;
....@@ -711,16 +821,20 @@
711821 	rtc@7000e000 {
712822 		compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
713823 		reg = <0x0 0x7000e000 0x0 0x100>;
714
-		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
824
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
825
+		interrupt-parent = <&tegra_pmc>;
715826 		clocks = <&tegra_car TEGRA210_CLK_RTC>;
716827 		clock-names = "rtc";
717828 	};
718829 
719
-	pmc: pmc@7000e400 {
830
+	tegra_pmc: pmc@7000e400 {
720831 		compatible = "nvidia,tegra210-pmc";
721832 		reg = <0x0 0x7000e400 0x0 0x400>;
722833 		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
723834 		clock-names = "pclk", "clk32k_in";
835
+		#clock-cells = <1>;
836
+		#interrupt-cells = <2>;
837
+		interrupt-controller;
724838 
725839 		powergates {
726840 			pd_audio: aud {
....@@ -733,7 +847,9 @@
733847 			pd_sor: sor {
734848 				clocks = <&tegra_car TEGRA210_CLK_SOR0>,
735849 					 <&tegra_car TEGRA210_CLK_SOR1>,
736
-					 <&tegra_car TEGRA210_CLK_CSI>,
850
+					 <&tegra_car TEGRA210_CLK_CILAB>,
851
+					 <&tegra_car TEGRA210_CLK_CILCD>,
852
+					 <&tegra_car TEGRA210_CLK_CILE>,
737853 					 <&tegra_car TEGRA210_CLK_DSIA>,
738854 					 <&tegra_car TEGRA210_CLK_DSIB>,
739855 					 <&tegra_car TEGRA210_CLK_DPAUX>,
....@@ -741,7 +857,6 @@
741857 					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
742858 				resets = <&tegra_car TEGRA210_CLK_SOR0>,
743859 					 <&tegra_car TEGRA210_CLK_SOR1>,
744
-					 <&tegra_car TEGRA210_CLK_CSI>,
745860 					 <&tegra_car TEGRA210_CLK_DSIA>,
746861 					 <&tegra_car TEGRA210_CLK_DSIB>,
747862 					 <&tegra_car TEGRA210_CLK_DPAUX>,
....@@ -775,6 +890,49 @@
775890 				reset-names = "vic";
776891 				#power-domain-cells = <0>;
777892 			};
893
+
894
+			pd_venc: venc {
895
+				clocks = <&tegra_car TEGRA210_CLK_VI>,
896
+					 <&tegra_car TEGRA210_CLK_CSI>;
897
+				resets = <&mc TEGRA210_MC_RESET_VI>,
898
+					 <&tegra_car 20>,
899
+					 <&tegra_car 52>;
900
+				#power-domain-cells = <0>;
901
+			};
902
+		};
903
+
904
+		sdmmc1_3v3: sdmmc1-3v3 {
905
+			pins = "sdmmc1";
906
+			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
907
+		};
908
+
909
+		sdmmc1_1v8: sdmmc1-1v8 {
910
+			pins = "sdmmc1";
911
+			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
912
+		};
913
+
914
+		sdmmc3_3v3: sdmmc3-3v3 {
915
+			pins = "sdmmc3";
916
+			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
917
+		};
918
+
919
+		sdmmc3_1v8: sdmmc3-1v8 {
920
+			pins = "sdmmc3";
921
+			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
922
+		};
923
+
924
+		pex_dpd_disable: pex_en {
925
+			pex-dpd-disable {
926
+				pins = "pex-bias", "pex-clk1", "pex-clk2";
927
+				low-power-disable;
928
+			};
929
+		};
930
+
931
+		pex_dpd_enable: pex_dis {
932
+			pex-dpd-enable {
933
+				pins = "pex-bias", "pex-clk1", "pex-clk2";
934
+				low-power-enable;
935
+			};
778936 		};
779937 	};
780938 
....@@ -796,6 +954,19 @@
796954 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
797955 
798956 		#iommu-cells = <1>;
957
+		#reset-cells = <1>;
958
+	};
959
+
960
+	emc: external-memory-controller@7001b000 {
961
+		compatible = "nvidia,tegra210-emc";
962
+		reg = <0x0 0x7001b000 0x0 0x1000>,
963
+		      <0x0 0x7001e000 0x0 0x1000>,
964
+		      <0x0 0x7001f000 0x0 0x1000>;
965
+		clocks = <&tegra_car TEGRA210_CLK_EMC>;
966
+		clock-names = "emc";
967
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
968
+		nvidia,memory-controller = <&mc>;
969
+		#cooling-cells = <2>;
799970 	};
800971 
801972 	sata@70020000 {
....@@ -844,8 +1015,8 @@
8441015 			 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
8451016 			 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
8461017 			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
847
-			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
8481018 			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1019
+			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
8491020 			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
8501021 			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
8511022 			 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
....@@ -853,12 +1024,14 @@
8531024 			 <&tegra_car TEGRA210_CLK_PLL_E>;
8541025 		clock-names = "xusb_host", "xusb_host_src",
8551026 			      "xusb_falcon_src", "xusb_ss",
856
-			      "xusb_ss_div2", "xusb_ss_src",
1027
+			      "xusb_ss_src", "xusb_ss_div2",
8571028 			      "xusb_hs_src", "xusb_fs_src",
8581029 			      "pll_u_480m", "clk_m", "pll_e";
8591030 		resets = <&tegra_car 89>, <&tegra_car 156>,
8601031 			 <&tegra_car 143>;
8611032 		reset-names = "xusb_host", "xusb_ss", "xusb_src";
1033
+		power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1034
+		power-domain-names = "xusb_host", "xusb_ss";
8621035 
8631036 		nvidia,xusb-padctl = <&padctl>;
8641037 
....@@ -1020,47 +1193,117 @@
10201193 		};
10211194 	};
10221195 
1023
-	sdhci@700b0000 {
1024
-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1196
+	mmc@700b0000 {
1197
+		compatible = "nvidia,tegra210-sdhci";
10251198 		reg = <0x0 0x700b0000 0x0 0x200>;
10261199 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1027
-		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1028
-		clock-names = "sdhci";
1200
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1201
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1202
+		clock-names = "sdhci", "tmclk";
10291203 		resets = <&tegra_car 14>;
10301204 		reset-names = "sdhci";
1205
+		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1206
+				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
1207
+		pinctrl-0 = <&sdmmc1_3v3>;
1208
+		pinctrl-1 = <&sdmmc1_1v8>;
1209
+		pinctrl-2 = <&sdmmc1_3v3_drv>;
1210
+		pinctrl-3 = <&sdmmc1_1v8_drv>;
1211
+		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1212
+		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1213
+		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1214
+		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1215
+		nvidia,default-tap = <0x2>;
1216
+		nvidia,default-trim = <0x4>;
1217
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1218
+				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1219
+				  <&tegra_car TEGRA210_CLK_PLL_C4>;
1220
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1221
+		assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
10311222 		status = "disabled";
10321223 	};
10331224 
1034
-	sdhci@700b0200 {
1035
-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1225
+	mmc@700b0200 {
1226
+		compatible = "nvidia,tegra210-sdhci";
10361227 		reg = <0x0 0x700b0200 0x0 0x200>;
10371228 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1038
-		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1039
-		clock-names = "sdhci";
1229
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1230
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1231
+		clock-names = "sdhci", "tmclk";
10401232 		resets = <&tegra_car 9>;
10411233 		reset-names = "sdhci";
1234
+		pinctrl-names = "sdmmc-1v8-drv";
1235
+		pinctrl-0 = <&sdmmc2_1v8_drv>;
1236
+		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1237
+		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1238
+		nvidia,default-tap = <0x8>;
1239
+		nvidia,default-trim = <0x0>;
10421240 		status = "disabled";
10431241 	};
10441242 
1045
-	sdhci@700b0400 {
1046
-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1243
+	mmc@700b0400 {
1244
+		compatible = "nvidia,tegra210-sdhci";
10471245 		reg = <0x0 0x700b0400 0x0 0x200>;
10481246 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1049
-		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1050
-		clock-names = "sdhci";
1247
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1248
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1249
+		clock-names = "sdhci", "tmclk";
10511250 		resets = <&tegra_car 69>;
10521251 		reset-names = "sdhci";
1252
+		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1253
+				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
1254
+		pinctrl-0 = <&sdmmc3_3v3>;
1255
+		pinctrl-1 = <&sdmmc3_1v8>;
1256
+		pinctrl-2 = <&sdmmc3_3v3_drv>;
1257
+		pinctrl-3 = <&sdmmc3_1v8_drv>;
1258
+		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1259
+		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1260
+		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1261
+		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1262
+		nvidia,default-tap = <0x3>;
1263
+		nvidia,default-trim = <0x3>;
10531264 		status = "disabled";
10541265 	};
10551266 
1056
-	sdhci@700b0600 {
1057
-		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1267
+	mmc@700b0600 {
1268
+		compatible = "nvidia,tegra210-sdhci";
10581269 		reg = <0x0 0x700b0600 0x0 0x200>;
10591270 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1060
-		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1061
-		clock-names = "sdhci";
1271
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1272
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1273
+		clock-names = "sdhci", "tmclk";
10621274 		resets = <&tegra_car 15>;
10631275 		reset-names = "sdhci";
1276
+		pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1277
+		pinctrl-0 = <&sdmmc4_1v8_drv>;
1278
+		pinctrl-1 = <&sdmmc4_1v8_drv>;
1279
+		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1280
+		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1281
+		nvidia,default-tap = <0x8>;
1282
+		nvidia,default-trim = <0x0>;
1283
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1284
+				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1285
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1286
+		nvidia,dqs-trim = <40>;
1287
+		mmc-hs400-1_8v;
1288
+		status = "disabled";
1289
+	};
1290
+
1291
+	usb@700d0000 {
1292
+		compatible = "nvidia,tegra210-xudc";
1293
+		reg = <0x0 0x700d0000 0x0 0x8000>,
1294
+		      <0x0 0x700d8000 0x0 0x1000>,
1295
+		      <0x0 0x700d9000 0x0 0x1000>;
1296
+		reg-names = "base", "fpci", "ipfs";
1297
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1298
+		clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1299
+			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1300
+			 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1301
+			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1302
+			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1303
+		clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1304
+		power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1305
+		power-domain-names = "dev", "ss";
1306
+		nvidia,xusb-padctl = <&padctl>;
10641307 		status = "disabled";
10651308 	};
10661309 
....@@ -1071,6 +1314,24 @@
10711314 		clock-names = "mipi-cal";
10721315 		power-domains = <&pd_sor>;
10731316 		#nvidia,mipi-calibrate-cells = <1>;
1317
+	};
1318
+
1319
+	dfll: clock@70110000 {
1320
+		compatible = "nvidia,tegra210-dfll";
1321
+		reg = <0 0x70110000 0 0x100>, /* DFLL control */
1322
+		      <0 0x70110000 0 0x100>, /* I2C output control */
1323
+		      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1324
+		      <0 0x70110200 0 0x100>; /* Look-up table RAM */
1325
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1326
+		clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1327
+			 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1328
+			 <&tegra_car TEGRA210_CLK_I2C5>;
1329
+		clock-names = "soc", "ref", "i2c";
1330
+		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1331
+		reset-names = "dvco";
1332
+		#clock-cells = <0>;
1333
+		clock-output-names = "dfllCPU_out";
1334
+		status = "disabled";
10741335 	};
10751336 
10761337 	aconnect@702c0000 {
....@@ -1116,7 +1377,7 @@
11161377 			status = "disabled";
11171378 		};
11181379 
1119
-		agic: agic@702f9000 {
1380
+		agic: interrupt-controller@702f9000 {
11201381 			compatible = "nvidia,tegra210-agic";
11211382 			#interrupt-cells = <3>;
11221383 			interrupt-controller;
....@@ -1126,6 +1387,146 @@
11261387 			clocks = <&tegra_car TEGRA210_CLK_APE>;
11271388 			clock-names = "clk";
11281389 			status = "disabled";
1390
+		};
1391
+
1392
+		tegra_ahub: ahub@702d0800 {
1393
+			compatible = "nvidia,tegra210-ahub";
1394
+			reg = <0x702d0800 0x800>;
1395
+			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1396
+			clock-names = "ahub";
1397
+			assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1398
+			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1399
+			#address-cells = <1>;
1400
+			#size-cells = <1>;
1401
+			ranges = <0x702d0000 0x702d0000 0x0000e400>;
1402
+			status = "disabled";
1403
+
1404
+			tegra_admaif: admaif@702d0000 {
1405
+				compatible = "nvidia,tegra210-admaif";
1406
+				reg = <0x702d0000 0x800>;
1407
+				dmas = <&adma 1>,  <&adma 1>,
1408
+				       <&adma 2>,  <&adma 2>,
1409
+				       <&adma 3>,  <&adma 3>,
1410
+				       <&adma 4>,  <&adma 4>,
1411
+				       <&adma 5>,  <&adma 5>,
1412
+				       <&adma 6>,  <&adma 6>,
1413
+				       <&adma 7>,  <&adma 7>,
1414
+				       <&adma 8>,  <&adma 8>,
1415
+				       <&adma 9>,  <&adma 9>,
1416
+				       <&adma 10>, <&adma 10>;
1417
+				dma-names = "rx1",  "tx1",
1418
+					    "rx2",  "tx2",
1419
+					    "rx3",  "tx3",
1420
+					    "rx4",  "tx4",
1421
+					    "rx5",  "tx5",
1422
+					    "rx6",  "tx6",
1423
+					    "rx7",  "tx7",
1424
+					    "rx8",  "tx8",
1425
+					    "rx9",  "tx9",
1426
+					    "rx10", "tx10";
1427
+				status = "disabled";
1428
+			};
1429
+
1430
+			tegra_i2s1: i2s@702d1000 {
1431
+				compatible = "nvidia,tegra210-i2s";
1432
+				reg = <0x702d1000 0x100>;
1433
+				clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1434
+					 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1435
+				clock-names = "i2s", "sync_input";
1436
+				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1437
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1438
+				assigned-clock-rates = <1536000>;
1439
+				sound-name-prefix = "I2S1";
1440
+				status = "disabled";
1441
+			};
1442
+
1443
+			tegra_i2s2: i2s@702d1100 {
1444
+				compatible = "nvidia,tegra210-i2s";
1445
+				reg = <0x702d1100 0x100>;
1446
+				clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1447
+					 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1448
+				clock-names = "i2s", "sync_input";
1449
+				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1450
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1451
+				assigned-clock-rates = <1536000>;
1452
+				sound-name-prefix = "I2S2";
1453
+				status = "disabled";
1454
+			};
1455
+
1456
+			tegra_i2s3: i2s@702d1200 {
1457
+				compatible = "nvidia,tegra210-i2s";
1458
+				reg = <0x702d1200 0x100>;
1459
+				clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1460
+					 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1461
+				clock-names = "i2s", "sync_input";
1462
+				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1463
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1464
+				assigned-clock-rates = <1536000>;
1465
+				sound-name-prefix = "I2S3";
1466
+				status = "disabled";
1467
+			};
1468
+
1469
+			tegra_i2s4: i2s@702d1300 {
1470
+				compatible = "nvidia,tegra210-i2s";
1471
+				reg = <0x702d1300 0x100>;
1472
+				clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1473
+					 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1474
+				clock-names = "i2s", "sync_input";
1475
+				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1476
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1477
+				assigned-clock-rates = <1536000>;
1478
+				sound-name-prefix = "I2S4";
1479
+				status = "disabled";
1480
+			};
1481
+
1482
+			tegra_i2s5: i2s@702d1400 {
1483
+				compatible = "nvidia,tegra210-i2s";
1484
+				reg = <0x702d1400 0x100>;
1485
+				clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1486
+					 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1487
+				clock-names = "i2s", "sync_input";
1488
+				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1489
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1490
+				assigned-clock-rates = <1536000>;
1491
+				sound-name-prefix = "I2S5";
1492
+				status = "disabled";
1493
+			};
1494
+
1495
+			tegra_dmic1: dmic@702d4000 {
1496
+				compatible = "nvidia,tegra210-dmic";
1497
+				reg = <0x702d4000 0x100>;
1498
+				clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1499
+				clock-names = "dmic";
1500
+				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1501
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1502
+				assigned-clock-rates = <3072000>;
1503
+				sound-name-prefix = "DMIC1";
1504
+				status = "disabled";
1505
+			};
1506
+
1507
+			tegra_dmic2: dmic@702d4100 {
1508
+				compatible = "nvidia,tegra210-dmic";
1509
+				reg = <0x702d4100 0x100>;
1510
+				clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1511
+				clock-names = "dmic";
1512
+				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1513
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1514
+				assigned-clock-rates = <3072000>;
1515
+				sound-name-prefix = "DMIC2";
1516
+				status = "disabled";
1517
+			};
1518
+
1519
+			tegra_dmic3: dmic@702d4200 {
1520
+				compatible = "nvidia,tegra210-dmic";
1521
+				reg = <0x702d4200 0x100>;
1522
+				clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1523
+				clock-names = "dmic";
1524
+				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1525
+				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1526
+				assigned-clock-rates = <3072000>;
1527
+				sound-name-prefix = "DMIC3";
1528
+				status = "disabled";
1529
+			};
11291530 		};
11301531 	};
11311532 
....@@ -1227,25 +1628,68 @@
12271628 			device_type = "cpu";
12281629 			compatible = "arm,cortex-a57";
12291630 			reg = <0>;
1631
+			clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1632
+				 <&tegra_car TEGRA210_CLK_PLL_X>,
1633
+				 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1634
+				 <&dfll>;
1635
+			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1636
+			clock-latency = <300000>;
1637
+			cpu-idle-states = <&CPU_SLEEP>;
1638
+			next-level-cache = <&L2>;
12301639 		};
12311640 
12321641 		cpu@1 {
12331642 			device_type = "cpu";
12341643 			compatible = "arm,cortex-a57";
12351644 			reg = <1>;
1645
+			cpu-idle-states = <&CPU_SLEEP>;
1646
+			next-level-cache = <&L2>;
12361647 		};
12371648 
12381649 		cpu@2 {
12391650 			device_type = "cpu";
12401651 			compatible = "arm,cortex-a57";
12411652 			reg = <2>;
1653
+			cpu-idle-states = <&CPU_SLEEP>;
1654
+			next-level-cache = <&L2>;
12421655 		};
12431656 
12441657 		cpu@3 {
12451658 			device_type = "cpu";
12461659 			compatible = "arm,cortex-a57";
12471660 			reg = <3>;
1661
+			cpu-idle-states = <&CPU_SLEEP>;
1662
+			next-level-cache = <&L2>;
12481663 		};
1664
+
1665
+		idle-states {
1666
+			entry-method = "psci";
1667
+
1668
+			CPU_SLEEP: cpu-sleep {
1669
+				compatible = "arm,idle-state";
1670
+				arm,psci-suspend-param = <0x40000007>;
1671
+				entry-latency-us = <100>;
1672
+				exit-latency-us = <30>;
1673
+				min-residency-us = <1000>;
1674
+				wakeup-latency-us = <130>;
1675
+				idle-state-name = "cpu-sleep";
1676
+				status = "disabled";
1677
+			};
1678
+		};
1679
+
1680
+		L2: l2-cache {
1681
+			compatible = "cache";
1682
+		};
1683
+	};
1684
+
1685
+	pmu {
1686
+		compatible = "arm,armv8-pmuv3";
1687
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1688
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1689
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1690
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1691
+		interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1692
+				      &{/cpus/cpu@2} &{/cpus/cpu@3}>;
12491693 	};
12501694 
12511695 	timer {
....@@ -1259,14 +1703,17 @@
12591703 			     <GIC_PPI 10
12601704 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
12611705 		interrupt-parent = <&gic>;
1706
+		arm,no-tick-in-suspend;
12621707 	};
12631708 
12641709 	soctherm: thermal-sensor@700e2000 {
12651710 		compatible = "nvidia,tegra210-soctherm";
1266
-		reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1267
-			0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1711
+		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1712
+		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
12681713 		reg-names = "soctherm-reg", "car-reg";
1269
-		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1714
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1715
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1716
+		interrupt-names = "thermal", "edp";
12701717 		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
12711718 			<&tegra_car TEGRA210_CLK_SOC_THERM>;
12721719 		clock-names = "tsensor", "soctherm";
....@@ -1313,6 +1760,7 @@
13131760 				};
13141761 			};
13151762 		};
1763
+
13161764 		mem {
13171765 			polling-delay-passive = <0>;
13181766 			polling-delay = <0>;
....@@ -1321,6 +1769,18 @@
13211769 				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
13221770 
13231771 			trips {
1772
+				dram_nominal: mem-nominal-trip {
1773
+					temperature = <50000>;
1774
+					hysteresis = <1000>;
1775
+					type = "passive";
1776
+				};
1777
+
1778
+				dram_throttle: mem-throttle-trip {
1779
+					temperature = <70000>;
1780
+					hysteresis = <1000>;
1781
+					type = "active";
1782
+				};
1783
+
13241784 				mem-shutdown-trip {
13251785 					temperature = <103000>;
13261786 					hysteresis = <0>;
....@@ -1329,12 +1789,18 @@
13291789 			};
13301790 
13311791 			cooling-maps {
1332
-				/*
1333
-				 * There are currently no cooling maps,
1334
-				 * because there are no cooling devices.
1335
-				 */
1792
+				dram-passive {
1793
+					cooling-device = <&emc 0 0>;
1794
+					trip = <&dram_nominal>;
1795
+				};
1796
+
1797
+				dram-active {
1798
+					cooling-device = <&emc 1 1>;
1799
+					trip = <&dram_throttle>;
1800
+				};
13361801 			};
13371802 		};
1803
+
13381804 		gpu {
13391805 			polling-delay-passive = <1000>;
13401806 			polling-delay = <0>;
....@@ -1363,6 +1829,7 @@
13631829 				};
13641830 			};
13651831 		};
1832
+
13661833 		pllx {
13671834 			polling-delay-passive = <0>;
13681835 			polling-delay = <0>;