forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a
kernel/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
....@@ -56,7 +56,7 @@
5656 };
5757
5858 memory {
59
- reg = <0 0x40000000 0 0x3F000000>;
59
+ reg = <0 0x40000000 0 0x20000000>;
6060 };
6161
6262 reg_1p8v: regulator-1p8v {
....@@ -83,6 +83,154 @@
8383 regulator-max-microvolt = <5000000>;
8484 regulator-boot-on;
8585 regulator-always-on;
86
+ };
87
+};
88
+
89
+&bch {
90
+ status = "disabled";
91
+};
92
+
93
+&btif {
94
+ status = "okay";
95
+};
96
+
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+&cir {
98
+ pinctrl-names = "default";
99
+ pinctrl-0 = <&irrx_pins>;
100
+ status = "okay";
101
+};
102
+
103
+&eth {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&eth_pins>;
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+ status = "okay";
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+
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+ gmac0: mac@0 {
109
+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
120
+ mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ switch@0 {
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+ compatible = "mediatek,mt7531";
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+ reg = <0>;
127
+ reset-gpios = <&pio 54 0>;
128
+
129
+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan0";
136
+ };
137
+
138
+ port@1 {
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+ reg = <1>;
140
+ label = "lan1";
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+ };
142
+
143
+ port@2 {
144
+ reg = <2>;
145
+ label = "lan2";
146
+ };
147
+
148
+ port@3 {
149
+ reg = <3>;
150
+ label = "lan3";
151
+ };
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+
153
+ port@4 {
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+ reg = <4>;
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+ label = "wan";
156
+ };
157
+
158
+ port@6 {
159
+ reg = <6>;
160
+ label = "cpu";
161
+ ethernet = <&gmac0>;
162
+ phy-mode = "2500base-x";
163
+
164
+ fixed-link {
165
+ speed = <2500>;
166
+ full-duplex;
167
+ pause;
168
+ };
169
+ };
170
+ };
171
+ };
172
+
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+ };
174
+};
175
+
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+&i2c1 {
177
+ pinctrl-names = "default";
178
+ pinctrl-0 = <&i2c1_pins>;
179
+ status = "okay";
180
+};
181
+
182
+&i2c2 {
183
+ pinctrl-names = "default";
184
+ pinctrl-0 = <&i2c2_pins>;
185
+ status = "okay";
186
+};
187
+
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+&mmc0 {
189
+ pinctrl-names = "default", "state_uhs";
190
+ pinctrl-0 = <&emmc_pins_default>;
191
+ pinctrl-1 = <&emmc_pins_uhs>;
192
+ status = "okay";
193
+ bus-width = <8>;
194
+ max-frequency = <50000000>;
195
+ cap-mmc-highspeed;
196
+ mmc-hs200-1_8v;
197
+ vmmc-supply = <&reg_3p3v>;
198
+ vqmmc-supply = <&reg_1p8v>;
199
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
200
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
201
+ non-removable;
202
+};
203
+
204
+&mmc1 {
205
+ pinctrl-names = "default", "state_uhs";
206
+ pinctrl-0 = <&sd0_pins_default>;
207
+ pinctrl-1 = <&sd0_pins_uhs>;
208
+ status = "okay";
209
+ bus-width = <4>;
210
+ max-frequency = <50000000>;
211
+ cap-sd-highspeed;
212
+ r_smpl = <1>;
213
+ cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
214
+ vmmc-supply = <&reg_3p3v>;
215
+ vqmmc-supply = <&reg_3p3v>;
216
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
217
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
218
+};
219
+
220
+&nandc {
221
+ pinctrl-names = "default";
222
+ pinctrl-0 = <&parallel_nand_pins>;
223
+ status = "disabled";
224
+};
225
+
226
+&nor_flash {
227
+ pinctrl-names = "default";
228
+ pinctrl-0 = <&spi_nor_pins>;
229
+ status = "disabled";
230
+
231
+ flash@0 {
232
+ compatible = "jedec,spi-nor";
233
+ reg = <0>;
86234 };
87235 };
88236
....@@ -349,103 +497,6 @@
349497 };
350498 };
351499
352
-&bch {
353
- status = "disabled";
354
-};
355
-
356
-&btif {
357
- status = "okay";
358
-};
359
-
360
-&cir {
361
- pinctrl-names = "default";
362
- pinctrl-0 = <&irrx_pins>;
363
- status = "okay";
364
-};
365
-
366
-&eth {
367
- pinctrl-names = "default";
368
- pinctrl-0 = <&eth_pins>;
369
- status = "okay";
370
-
371
- gmac1: mac@1 {
372
- compatible = "mediatek,eth-mac";
373
- reg = <1>;
374
- phy-handle = <&phy5>;
375
- };
376
-
377
- mdio-bus {
378
- #address-cells = <1>;
379
- #size-cells = <0>;
380
-
381
- phy5: ethernet-phy@5 {
382
- reg = <5>;
383
- phy-mode = "sgmii";
384
- };
385
- };
386
-};
387
-
388
-&i2c1 {
389
- pinctrl-names = "default";
390
- pinctrl-0 = <&i2c1_pins>;
391
- status = "okay";
392
-};
393
-
394
-&i2c2 {
395
- pinctrl-names = "default";
396
- pinctrl-0 = <&i2c2_pins>;
397
- status = "okay";
398
-};
399
-
400
-&mmc0 {
401
- pinctrl-names = "default", "state_uhs";
402
- pinctrl-0 = <&emmc_pins_default>;
403
- pinctrl-1 = <&emmc_pins_uhs>;
404
- status = "okay";
405
- bus-width = <8>;
406
- max-frequency = <50000000>;
407
- cap-mmc-highspeed;
408
- mmc-hs200-1_8v;
409
- vmmc-supply = <&reg_3p3v>;
410
- vqmmc-supply = <&reg_1p8v>;
411
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
412
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
413
- non-removable;
414
-};
415
-
416
-&mmc1 {
417
- pinctrl-names = "default", "state_uhs";
418
- pinctrl-0 = <&sd0_pins_default>;
419
- pinctrl-1 = <&sd0_pins_uhs>;
420
- status = "okay";
421
- bus-width = <4>;
422
- max-frequency = <50000000>;
423
- cap-sd-highspeed;
424
- r_smpl = <1>;
425
- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
426
- vmmc-supply = <&reg_3p3v>;
427
- vqmmc-supply = <&reg_3p3v>;
428
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
429
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
430
-};
431
-
432
-&nandc {
433
- pinctrl-names = "default";
434
- pinctrl-0 = <&parallel_nand_pins>;
435
- status = "disabled";
436
-};
437
-
438
-&nor_flash {
439
- pinctrl-names = "default";
440
- pinctrl-0 = <&spi_nor_pins>;
441
- status = "disabled";
442
-
443
- flash@0 {
444
- compatible = "jedec,spi-nor";
445
- reg = <0>;
446
- };
447
-};
448
-
449500 &pwm {
450501 pinctrl-names = "default";
451502 pinctrl-0 = <&pwm7_pins>;
....@@ -506,3 +557,7 @@
506557 pinctrl-0 = <&watchdog_pins>;
507558 status = "okay";
508559 };
560
+
561
+&wmac {
562
+ status = "okay";
563
+};