~hc/RK356X_SDK_RELEASE.git

..	..	@@ -20,8 +20,11 @@
20	20
21	21	aliases {
22	22	crypto = &crypto;
	23	+ rtc1 = &ftm_alarm0;
23	24	serial0 = &serial0;
24	25	serial1 = &serial1;
	26	+ serial2 = &serial2;
	27	+ serial3 = &serial3;
25	28	};
26	29
27	30	cpu: cpus {
..	..	@@ -76,20 +79,62 @@
76	79	};
77	80
78	81	thermal-zones {
79		- cpu_thermal: cpu-thermal {
	82	+ ddr-controller1 {
80	83	polling-delay-passive = <1000>;
81	84	polling-delay = <5000>;
	85	+ thermal-sensors = <&tmu 1>;
82	86
	87	+ trips {
	88	+ ddr-ctrler1-crit {
	89	+ temperature = <95000>;
	90	+ hysteresis = <2000>;
	91	+ type = "critical";
	92	+ };
	93	+ };
	94	+ };
	95	+
	96	+ ddr-controller2 {
	97	+ polling-delay-passive = <1000>;
	98	+ polling-delay = <5000>;
	99	+ thermal-sensors = <&tmu 2>;
	100	+
	101	+ trips {
	102	+ ddr-ctrler2-crit {
	103	+ temperature = <95000>;
	104	+ hysteresis = <2000>;
	105	+ type = "critical";
	106	+ };
	107	+ };
	108	+ };
	109	+
	110	+ ddr-controller3 {
	111	+ polling-delay-passive = <1000>;
	112	+ polling-delay = <5000>;
	113	+ thermal-sensors = <&tmu 3>;
	114	+
	115	+ trips {
	116	+ ddr-ctrler3-crit {
	117	+ temperature = <95000>;
	118	+ hysteresis = <2000>;
	119	+ type = "critical";
	120	+ };
	121	+ };
	122	+ };
	123	+
	124	+ core-cluster1 {
	125	+ polling-delay-passive = <1000>;
	126	+ polling-delay = <5000>;
83	127	thermal-sensors = <&tmu 4>;
84	128
85	129	trips {
86		- cpu_alert: cpu-alert {
87		- temperature = <75000>;
	130	+ core_cluster1_alert: core-cluster1-alert {
	131	+ temperature = <85000>;
88	132	hysteresis = <2000>;
89	133	type = "passive";
90	134	};
91		- cpu_crit: cpu-crit {
92		- temperature = <85000>;
	135	+
	136	+ core-cluster1-crit {
	137	+ temperature = <95000>;
93	138	hysteresis = <2000>;
94	139	type = "critical";
95	140	};
..	..	@@ -97,28 +142,97 @@
97	142
98	143	cooling-maps {
99	144	map0 {
100		- trip = <&cpu_alert>;
	145	+ trip = <&core_cluster1_alert>;
101	146	cooling-device =
102		- <&cpu0 THERMAL_NO_LIMIT
103		- THERMAL_NO_LIMIT>;
	147	+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	148	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
104	149	};
105		- map1 {
106		- trip = <&cpu_alert>;
107		- cooling-device =
108		- <&cpu2 THERMAL_NO_LIMIT
109		- THERMAL_NO_LIMIT>;
	150	+ };
	151	+ };
	152	+
	153	+ core-cluster2 {
	154	+ polling-delay-passive = <1000>;
	155	+ polling-delay = <5000>;
	156	+ thermal-sensors = <&tmu 5>;
	157	+
	158	+ trips {
	159	+ core_cluster2_alert: core-cluster2-alert {
	160	+ temperature = <85000>;
	161	+ hysteresis = <2000>;
	162	+ type = "passive";
110	163	};
111		- map2 {
112		- trip = <&cpu_alert>;
113		- cooling-device =
114		- <&cpu4 THERMAL_NO_LIMIT
115		- THERMAL_NO_LIMIT>;
	164	+
	165	+ core-cluster2-crit {
	166	+ temperature = <95000>;
	167	+ hysteresis = <2000>;
	168	+ type = "critical";
116	169	};
117		- map3 {
118		- trip = <&cpu_alert>;
	170	+ };
	171	+
	172	+ cooling-maps {
	173	+ map0 {
	174	+ trip = <&core_cluster2_alert>;
119	175	cooling-device =
120		- <&cpu6 THERMAL_NO_LIMIT
121		- THERMAL_NO_LIMIT>;
	176	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	177	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	178	+ };
	179	+ };
	180	+ };
	181	+
	182	+ core-cluster3 {
	183	+ polling-delay-passive = <1000>;
	184	+ polling-delay = <5000>;
	185	+ thermal-sensors = <&tmu 6>;
	186	+
	187	+ trips {
	188	+ core_cluster3_alert: core-cluster3-alert {
	189	+ temperature = <85000>;
	190	+ hysteresis = <2000>;
	191	+ type = "passive";
	192	+ };
	193	+
	194	+ core-cluster3-crit {
	195	+ temperature = <95000>;
	196	+ hysteresis = <2000>;
	197	+ type = "critical";
	198	+ };
	199	+ };
	200	+
	201	+ cooling-maps {
	202	+ map0 {
	203	+ trip = <&core_cluster3_alert>;
	204	+ cooling-device =
	205	+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	206	+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	207	+ };
	208	+ };
	209	+ };
	210	+
	211	+ core-cluster4 {
	212	+ polling-delay-passive = <1000>;
	213	+ polling-delay = <5000>;
	214	+ thermal-sensors = <&tmu 7>;
	215	+
	216	+ trips {
	217	+ core_cluster4_alert: core-cluster4-alert {
	218	+ temperature = <85000>;
	219	+ hysteresis = <2000>;
	220	+ type = "passive";
	221	+ };
	222	+
	223	+ core-cluster4-crit {
	224	+ temperature = <95000>;
	225	+ hysteresis = <2000>;
	226	+ type = "critical";
	227	+ };
	228	+ };
	229	+
	230	+ cooling-maps {
	231	+ map0 {
	232	+ trip = <&core_cluster4_alert>;
	233	+ cooling-device =
	234	+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	235	+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
122	236	};
123	237	};
124	238	};
..	..	@@ -148,6 +262,7 @@
148	262	#address-cells = <2>;
149	263	#size-cells = <2>;
150	264	ranges;
	265	+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
151	266
152	267	clockgen: clocking@1300000 {
153	268	compatible = "fsl,ls2080a-clockgen";
..	..	@@ -221,60 +336,74 @@
221	336	interrupts = <0 32 0x4>; /* Level high type */
222	337	};
223	338
	339	+ serial2: serial@21d0500 {
	340	+ compatible = "fsl,ns16550", "ns16550a";
	341	+ reg = <0x0 0x21d0500 0x0 0x100>;
	342	+ clocks = <&clockgen 4 3>;
	343	+ interrupts = <0 33 0x4>; /* Level high type */
	344	+ };
	345	+
	346	+ serial3: serial@21d0600 {
	347	+ compatible = "fsl,ns16550", "ns16550a";
	348	+ reg = <0x0 0x21d0600 0x0 0x100>;
	349	+ clocks = <&clockgen 4 3>;
	350	+ interrupts = <0 33 0x4>; /* Level high type */
	351	+ };
	352	+
224	353	cluster1_core0_watchdog: wdt@c000000 {
225	354	compatible = "arm,sp805", "arm,primecell";
226	355	reg = <0x0 0xc000000 0x0 0x1000>;
227	356	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
228		- clock-names = "apb_pclk", "wdog_clk";
	357	+ clock-names = "wdog_clk", "apb_pclk";
229	358	};
230	359
231	360	cluster1_core1_watchdog: wdt@c010000 {
232	361	compatible = "arm,sp805", "arm,primecell";
233	362	reg = <0x0 0xc010000 0x0 0x1000>;
234	363	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
235		- clock-names = "apb_pclk", "wdog_clk";
	364	+ clock-names = "wdog_clk", "apb_pclk";
236	365	};
237	366
238	367	cluster2_core0_watchdog: wdt@c100000 {
239	368	compatible = "arm,sp805", "arm,primecell";
240	369	reg = <0x0 0xc100000 0x0 0x1000>;
241	370	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
242		- clock-names = "apb_pclk", "wdog_clk";
	371	+ clock-names = "wdog_clk", "apb_pclk";
243	372	};
244	373
245	374	cluster2_core1_watchdog: wdt@c110000 {
246	375	compatible = "arm,sp805", "arm,primecell";
247	376	reg = <0x0 0xc110000 0x0 0x1000>;
248	377	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
249		- clock-names = "apb_pclk", "wdog_clk";
	378	+ clock-names = "wdog_clk", "apb_pclk";
250	379	};
251	380
252	381	cluster3_core0_watchdog: wdt@c200000 {
253	382	compatible = "arm,sp805", "arm,primecell";
254	383	reg = <0x0 0xc200000 0x0 0x1000>;
255	384	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
256		- clock-names = "apb_pclk", "wdog_clk";
	385	+ clock-names = "wdog_clk", "apb_pclk";
257	386	};
258	387
259	388	cluster3_core1_watchdog: wdt@c210000 {
260	389	compatible = "arm,sp805", "arm,primecell";
261	390	reg = <0x0 0xc210000 0x0 0x1000>;
262	391	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
263		- clock-names = "apb_pclk", "wdog_clk";
	392	+ clock-names = "wdog_clk", "apb_pclk";
264	393	};
265	394
266	395	cluster4_core0_watchdog: wdt@c300000 {
267	396	compatible = "arm,sp805", "arm,primecell";
268	397	reg = <0x0 0xc300000 0x0 0x1000>;
269	398	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
270		- clock-names = "apb_pclk", "wdog_clk";
	399	+ clock-names = "wdog_clk", "apb_pclk";
271	400	};
272	401
273	402	cluster4_core1_watchdog: wdt@c310000 {
274	403	compatible = "arm,sp805", "arm,primecell";
275	404	reg = <0x0 0xc310000 0x0 0x1000>;
276	405	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
277		- clock-names = "apb_pclk", "wdog_clk";
	406	+ clock-names = "wdog_clk", "apb_pclk";
278	407	};
279	408
280	409	crypto: crypto@8000000 {
..	..	@@ -316,11 +445,26 @@
316	445	};
317	446	};
318	447
	448	+ console@8340020 {
	449	+ compatible = "fsl,dpaa2-console";
	450	+ reg = <0x00000000 0x08340020 0 0x2>;
	451	+ };
	452	+
	453	+ ptp-timer@8b95000 {
	454	+ compatible = "fsl,dpaa2-ptp";
	455	+ reg = <0x0 0x8b95000 0x0 0x100>;
	456	+ clocks = <&clockgen 4 1>;
	457	+ little-endian;
	458	+ fsl,extts-fifo;
	459	+ };
	460	+
319	461	fsl_mc: fsl-mc@80c000000 {
320	462	compatible = "fsl,qoriq-mc";
321	463	reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
322	464	<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
323	465	msi-parent = <&its>;
	466	+ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
	467	+ dma-coherent;
324	468	#address-cells = <3>;
325	469	#size-cells = <1>;
326	470
..	..	@@ -424,6 +568,9 @@
424	568	compatible = "arm,mmu-500";
425	569	reg = <0 0x5000000 0 0x800000>;
426	570	#global-interrupts = <12>;
	571	+ #iommu-cells = <1>;
	572	+ stream-match-mask = <0x7C00>;
	573	+ dma-coherent;
427	574	interrupts = <0 13 4>, /* global secure fault */
428	575	<0 14 4>, /* combined secure interrupt */
429	576	<0 15 4>, /* global non-secure fault */
..	..	@@ -466,7 +613,6 @@
466	613	<0 204 4>, <0 205 4>,
467	614	<0 206 4>, <0 207 4>,
468	615	<0 208 4>, <0 209 4>;
469		- mmu-masters = <&fsl_mc 0x300 0>;
470	616	};
471	617
472	618	dspi: spi@2100000 {
..	..	@@ -595,21 +741,20 @@
595	741	};
596	742
597	743	qspi: spi@20c0000 {
598		- status = "disabled";
599		- compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
	744	+ compatible = "fsl,ls2080a-qspi";
600	745	#address-cells = <1>;
601	746	#size-cells = <0>;
602	747	reg = <0x0 0x20c0000 0x0 0x10000>,
603	748	<0x0 0x20000000 0x0 0x10000000>;
604	749	reg-names = "QuadSPI", "QuadSPI-memory";
605		- interrupts = <0 25 0x4>; /* Level high type */
	750	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
606	751	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
607	752	clock-names = "qspi_en", "qspi";
	753	+ status = "disabled";
608	754	};
609	755
610	756	pcie1: pcie@3400000 {
611		- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
612		- "snps,dw-pcie";
	757	+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
613	758	reg-names = "regs", "config";
614	759	interrupts = <0 108 0x4>; /* Level high type */
615	760	interrupt-names = "intr";
..	..	@@ -617,7 +762,7 @@
617	762	#size-cells = <2>;
618	763	device_type = "pci";
619	764	dma-coherent;
620		- num-lanes = <4>;
	765	+ num-viewport = <6>;
621	766	bus-range = <0x0 0xff>;
622	767	msi-parent = <&its>;
623	768	#interrupt-cells = <1>;
..	..	@@ -626,11 +771,12 @@
626	771	<0000 0 0 2 &gic 0 0 0 110 4>,
627	772	<0000 0 0 3 &gic 0 0 0 111 4>,
628	773	<0000 0 0 4 &gic 0 0 0 112 4>;
	774	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	775	+ status = "disabled";
629	776	};
630	777
631	778	pcie2: pcie@3500000 {
632		- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
633		- "snps,dw-pcie";
	779	+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
634	780	reg-names = "regs", "config";
635	781	interrupts = <0 113 0x4>; /* Level high type */
636	782	interrupt-names = "intr";
..	..	@@ -638,7 +784,7 @@
638	784	#size-cells = <2>;
639	785	device_type = "pci";
640	786	dma-coherent;
641		- num-lanes = <4>;
	787	+ num-viewport = <6>;
642	788	bus-range = <0x0 0xff>;
643	789	msi-parent = <&its>;
644	790	#interrupt-cells = <1>;
..	..	@@ -647,11 +793,12 @@
647	793	<0000 0 0 2 &gic 0 0 0 115 4>,
648	794	<0000 0 0 3 &gic 0 0 0 116 4>,
649	795	<0000 0 0 4 &gic 0 0 0 117 4>;
	796	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	797	+ status = "disabled";
650	798	};
651	799
652	800	pcie3: pcie@3600000 {
653		- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
654		- "snps,dw-pcie";
	801	+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
655	802	reg-names = "regs", "config";
656	803	interrupts = <0 118 0x4>; /* Level high type */
657	804	interrupt-names = "intr";
..	..	@@ -659,7 +806,7 @@
659	806	#size-cells = <2>;
660	807	device_type = "pci";
661	808	dma-coherent;
662		- num-lanes = <8>;
	809	+ num-viewport = <256>;
663	810	bus-range = <0x0 0xff>;
664	811	msi-parent = <&its>;
665	812	#interrupt-cells = <1>;
..	..	@@ -668,11 +815,12 @@
668	815	<0000 0 0 2 &gic 0 0 0 120 4>,
669	816	<0000 0 0 3 &gic 0 0 0 121 4>,
670	817	<0000 0 0 4 &gic 0 0 0 122 4>;
	818	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	819	+ status = "disabled";
671	820	};
672	821
673	822	pcie4: pcie@3700000 {
674		- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
675		- "snps,dw-pcie";
	823	+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
676	824	reg-names = "regs", "config";
677	825	interrupts = <0 123 0x4>; /* Level high type */
678	826	interrupt-names = "intr";
..	..	@@ -680,7 +828,7 @@
680	828	#size-cells = <2>;
681	829	device_type = "pci";
682	830	dma-coherent;
683		- num-lanes = <4>;
	831	+ num-viewport = <6>;
684	832	bus-range = <0x0 0xff>;
685	833	msi-parent = <&its>;
686	834	#interrupt-cells = <1>;
..	..	@@ -689,6 +837,8 @@
689	837	<0000 0 0 2 &gic 0 0 0 125 4>,
690	838	<0000 0 0 3 &gic 0 0 0 126 4>,
691	839	<0000 0 0 4 &gic 0 0 0 127 4>;
	840	+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
	841	+ status = "disabled";
692	842	};
693	843
694	844	sata0: sata@3200000 {
..	..	@@ -717,6 +867,7 @@
717	867	dr_mode = "host";
718	868	snps,quirk-frame-length-adjustment = <0x20>;
719	869	snps,dis_rxdet_inp3_quirk;
	870	+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
720	871	};
721	872
722	873	usb1: usb3@3110000 {
..	..	@@ -727,6 +878,7 @@
727	878	dr_mode = "host";
728	879	snps,quirk-frame-length-adjustment = <0x20>;
729	880	snps,dis_rxdet_inp3_quirk;
	881	+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
730	882	};
731	883
732	884	ccn@4000000 {
..	..	@@ -734,6 +886,20 @@
734	886	reg = <0x0 0x04000000 0x0 0x01000000>;
735	887	interrupts = <0 12 4>;
736	888	};
	889	+
	890	+ rcpm: power-controller@1e34040 {
	891	+ compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
	892	+ reg = <0x0 0x1e34040 0x0 0x18>;
	893	+ #fsl,rcpm-wakeup-cells = <6>;
	894	+ little-endian;
	895	+ };
	896	+
	897	+ ftm_alarm0: timer@2800000 {
	898	+ compatible = "fsl,ls208xa-ftm-alarm";
	899	+ reg = <0x0 0x2800000 0x0 0x10000>;
	900	+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
	901	+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	902	+ };
737	903	};
738	904
739	905	ddr1: memory-controller@1080000 {