disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/arm64/boot/dts/exynos/exynos7.dtsi
..
..
@@ -1,6 +1,6 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * SAMSUNG EXYNOS7 SoC device tree source
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+ * Samsung Exynos7 SoC device tree source
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  *
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  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
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  *		http://www.samsung.com
..
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@@ -28,34 +28,51 @@
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 		tmuctrl0 = &tmuctrl_0;
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 	};
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+	arm-pmu {
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+		compatible = "arm,cortex-a57-pmu";
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+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
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+				     <&cpu_atlas2>, <&cpu_atlas3>;
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+	};
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+
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+	fin_pll: clock {
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+		/* XXTI */
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+		compatible = "fixed-clock";
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+		clock-output-names = "fin_pll";
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+		#clock-cells = <0>;
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+	};
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+
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 	cpus {
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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 		cpu_atlas0: cpu@0 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a57", "arm,armv8";
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+			compatible = "arm,cortex-a57";
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 			reg = <0x0>;
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 			enable-method = "psci";
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 		};
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 		cpu_atlas1: cpu@1 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a57", "arm,armv8";
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+			compatible = "arm,cortex-a57";
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 			reg = <0x1>;
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 			enable-method = "psci";
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 		};
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 		cpu_atlas2: cpu@2 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a57", "arm,armv8";
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+			compatible = "arm,cortex-a57";
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 			reg = <0x2>;
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 			enable-method = "psci";
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 		};
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 		cpu_atlas3: cpu@3 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a57", "arm,armv8";
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+			compatible = "arm,cortex-a57";
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 			reg = <0x3>;
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 			enable-method = "psci";
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 		};
..
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@@ -68,7 +85,7 @@
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 		cpu_on = <0xC4000003>;
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 	};
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-	soc: soc {
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+	soc: soc@0 {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
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 		#size-cells = <1>;
..
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@@ -77,12 +94,6 @@
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 		chipid@10000000 {
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 			compatible = "samsung,exynos4210-chipid";
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 			reg = <0x10000000 0x100>;
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-		};
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-
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-		fin_pll: xxti {
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-			compatible = "fixed-clock";
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-			clock-output-names = "fin_pll";
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-			#clock-cells = <0>;
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 		};
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 		gic: interrupt-controller@11001000 {
..
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@@ -96,33 +107,26 @@
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 				<0x11006000 0x2000>;
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 		};
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-		amba {
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-			compatible = "simple-bus";
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-			#address-cells = <1>;
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-			#size-cells = <1>;
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-			ranges;
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+		pdma0: pdma@10e10000 {
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+			compatible = "arm,pl330", "arm,primecell";
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+			reg = <0x10E10000 0x1000>;
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+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock_fsys0 ACLK_PDMA0>;
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+			clock-names = "apb_pclk";
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+			#dma-cells = <1>;
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+			#dma-channels = <8>;
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+			#dma-requests = <32>;
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+		};
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-			pdma0: pdma@10e10000 {
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-				compatible = "arm,pl330", "arm,primecell";
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-				reg = <0x10E10000 0x1000>;
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-				interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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-				clocks = <&clock_fsys0 ACLK_PDMA0>;
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-				clock-names = "apb_pclk";
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-				#dma-cells = <1>;
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-				#dma-channels = <8>;
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-				#dma-requests = <32>;
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-			};
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-
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-			pdma1: pdma@10eb0000 {
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-				compatible = "arm,pl330", "arm,primecell";
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-				reg = <0x10EB0000 0x1000>;
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-				interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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-				clocks = <&clock_fsys0 ACLK_PDMA1>;
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-				clock-names = "apb_pclk";
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-				#dma-cells = <1>;
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-				#dma-channels = <8>;
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-				#dma-requests = <32>;
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-			};
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+		pdma1: pdma@10eb0000 {
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+			compatible = "arm,pl330", "arm,primecell";
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+			reg = <0x10EB0000 0x1000>;
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+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock_fsys0 ACLK_PDMA1>;
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+			clock-names = "apb_pclk";
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+			#dma-cells = <1>;
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+			#dma-channels = <8>;
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+			#dma-requests = <32>;
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 		};
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 		clock_topc: clock-controller@10570000 {
..
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@@ -211,9 +215,14 @@
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 			#clock-cells = <1>;
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 			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
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 				 <&clock_top1 DOUT_SCLK_MMC0>,
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-				 <&clock_top1 DOUT_SCLK_MMC1>;
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+				 <&clock_top1 DOUT_SCLK_MMC1>,
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+				 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
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+				 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
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+				 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
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 			clock-names = "fin_pll", "dout_aclk_fsys1_200",
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-				      "dout_sclk_mmc0", "dout_sclk_mmc1";
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+				      "dout_sclk_mmc0", "dout_sclk_mmc1",
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+				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
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+				      "dout_sclk_phy_fsys1_26m";
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 		};
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 		serial_0: serial@13630000 {
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@@ -471,28 +480,6 @@
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 			status = "disabled";
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 		};
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-		arm-pmu {
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-			compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
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-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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-			interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
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-					     <&cpu_atlas2>, <&cpu_atlas3>;
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-		};
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-
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-		timer {
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-			compatible = "arm,armv8-timer";
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-			interrupts = <GIC_PPI 13
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-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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-				     <GIC_PPI 14
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-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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-				     <GIC_PPI 11
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-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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-				     <GIC_PPI 10
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-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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-		};
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-
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 		pmu_system_controller: system-controller@105c0000 {
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 			compatible = "samsung,exynos7-pmu", "syscon";
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 			reg = <0x105c0000 0x5000>;
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@@ -516,6 +503,17 @@
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 			clock-names = "watchdog";
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 			samsung,syscon-phandle = <&pmu_system_controller>;
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 			status = "disabled";
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+		};
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+
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+		gpu: gpu@14ac0000 {
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+			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
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+			reg = <0x14ac0000 0x5000>;
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+			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "job", "mmu", "gpu";
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+			status = "disabled";
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+			/* TODO: operating points for DVFS, cooling device */
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 		};
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 		mmc_0: mmc@15740000 {
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@@ -571,6 +569,11 @@
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 		pwm: pwm@136c0000 {
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 			compatible = "samsung,exynos4210-pwm";
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 			reg = <0x136c0000 0x100>;
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+			interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
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 			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
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 			#pwm-cells = <3>;
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 			clocks = <&clock_peric0 PCLK_PWM>;
..
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@@ -587,13 +590,38 @@
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 			#thermal-sensor-cells = <0>;
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 		};
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-		thermal-zones {
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-			atlas_thermal: cluster0-thermal {
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-				polling-delay-passive = <0>; /* milliseconds */
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-				polling-delay = <0>; /* milliseconds */
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-				thermal-sensors = <&tmuctrl_0>;
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-				#include "exynos7-trip-points.dtsi"
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-			};
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+		ufs: ufs@15570000 {
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+			compatible = "samsung,exynos7-ufs";
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+			reg = <0x15570000 0x100>,  /* 0: HCI standard */
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+				<0x15570100 0x100>,  /* 1: Vendor specificed */
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+				<0x15571000 0x200>,  /* 2: UNIPRO */
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+				<0x15572000 0x300>;  /* 3: UFS protector */
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+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
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+			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
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+				<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
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+			clock-names = "core_clk", "sclk_unipro_main";
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+			freq-table-hz = <0 0>, <0 0>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
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+			phys = <&ufs_phy>;
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+			phy-names = "ufs-phy";
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+			status = "disabled";
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+		};
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+
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+		ufs_phy: ufs-phy@15571800 {
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+			compatible = "samsung,exynos7-ufs-phy";
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+			reg = <0x15571800 0x240>;
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+			reg-names = "phy-pma";
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+			samsung,pmu-syscon = <&pmu_system_controller>;
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+			#phy-cells = <0>;
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+			clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
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+				 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
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+				 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
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+				 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
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+			clock-names = "ref_clk", "rx1_symbol_clk",
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+				      "rx0_symbol_clk",
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+				      "tx0_symbol_clk";
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 		};
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 		usbdrd_phy: phy@15500000 {
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@@ -630,6 +658,27 @@
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 			};
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 		};
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 	};
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+
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+	thermal-zones {
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+		atlas_thermal: cluster0-thermal {
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+			polling-delay-passive = <0>; /* milliseconds */
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+			polling-delay = <0>; /* milliseconds */
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+			thermal-sensors = <&tmuctrl_0>;
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+			#include "exynos7-trip-points.dtsi"
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+		};
669
+	};
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+
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+	timer {
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+		compatible = "arm,armv8-timer";
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+		interrupts = <GIC_PPI 13
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+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 14
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+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 11
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+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 10
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+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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+	};
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 };
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 #include "exynos7-pinctrl.dtsi"