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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright Altera Corporation (C) 2015. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License along with
14
- * this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 /dts-v1/;
....@@ -24,33 +13,46 @@
2413 	#address-cells = <2>;
2514 	#size-cells = <2>;
2615 
16
+	reserved-memory {
17
+		#address-cells = <2>;
18
+		#size-cells = <2>;
19
+		ranges;
20
+
21
+		service_reserved: svcbuffer@0 {
22
+			compatible = "shared-dma-pool";
23
+			reg = <0x0 0x0 0x0 0x1000000>;
24
+			alignment = <0x1000>;
25
+			no-map;
26
+		};
27
+	};
28
+
2729 	cpus {
2830 		#address-cells = <1>;
2931 		#size-cells = <0>;
3032 
3133 		cpu0: cpu@0 {
32
-			compatible = "arm,cortex-a53", "arm,armv8";
34
+			compatible = "arm,cortex-a53";
3335 			device_type = "cpu";
3436 			enable-method = "psci";
3537 			reg = <0x0>;
3638 		};
3739 
3840 		cpu1: cpu@1 {
39
-			compatible = "arm,cortex-a53", "arm,armv8";
41
+			compatible = "arm,cortex-a53";
4042 			device_type = "cpu";
4143 			enable-method = "psci";
4244 			reg = <0x1>;
4345 		};
4446 
4547 		cpu2: cpu@2 {
46
-			compatible = "arm,cortex-a53", "arm,armv8";
48
+			compatible = "arm,cortex-a53";
4749 			device_type = "cpu";
4850 			enable-method = "psci";
4951 			reg = <0x2>;
5052 		};
5153 
5254 		cpu3: cpu@3 {
53
-			compatible = "arm,cortex-a53", "arm,armv8";
55
+			compatible = "arm,cortex-a53";
5456 			device_type = "cpu";
5557 			enable-method = "psci";
5658 			reg = <0x3>;
....@@ -75,7 +77,7 @@
7577 		method = "smc";
7678 	};
7779 
78
-	intc: intc@fffc1000 {
80
+	intc: interrupt-controller@fffc1000 {
7981 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
8082 		#interrupt-cells = <3>;
8183 		interrupt-controller;
....@@ -92,6 +94,14 @@
9294 		device_type = "soc";
9395 		interrupt-parent = <&intc>;
9496 		ranges = <0 0 0 0xffffffff>;
97
+
98
+		base_fpga_region {
99
+			#address-cells = <0x1>;
100
+			#size-cells = <0x1>;
101
+
102
+			compatible = "fpga-region";
103
+			fpga-mgr = <&fpga_mgr>;
104
+		};
95105 
96106 		clkmgr: clock-controller@ffd10000 {
97107 			compatible = "intel,stratix10-clkmgr";
....@@ -128,53 +138,56 @@
128138 		};
129139 
130140 		gmac0: ethernet@ff800000 {
131
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
141
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
132142 			reg = <0xff800000 0x2000>;
133143 			interrupts = <0 90 4>;
134144 			interrupt-names = "macirq";
135145 			mac-address = [00 00 00 00 00 00];
136146 			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
137147 			reset-names = "stmmaceth", "stmmaceth-ocp";
138
-			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
139
-			clock-names = "stmmaceth";
148
+			clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
149
+			clock-names = "stmmaceth", "ptp_ref";
140150 			tx-fifo-depth = <16384>;
141151 			rx-fifo-depth = <16384>;
142152 			snps,multicast-filter-bins = <256>;
153
+			iommus = <&smmu 1>;
143154 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
144155 			status = "disabled";
145156 		};
146157 
147158 		gmac1: ethernet@ff802000 {
148
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
159
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
149160 			reg = <0xff802000 0x2000>;
150161 			interrupts = <0 91 4>;
151162 			interrupt-names = "macirq";
152163 			mac-address = [00 00 00 00 00 00];
153164 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
154165 			reset-names = "stmmaceth", "stmmaceth-ocp";
155
-			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
156
-			clock-names = "stmmaceth";
166
+			clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
167
+			clock-names = "stmmaceth", "ptp_ref";
157168 			tx-fifo-depth = <16384>;
158169 			rx-fifo-depth = <16384>;
159170 			snps,multicast-filter-bins = <256>;
160
-			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
171
+			iommus = <&smmu 2>;
172
+			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
161173 			status = "disabled";
162174 		};
163175 
164176 		gmac2: ethernet@ff804000 {
165
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
177
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
166178 			reg = <0xff804000 0x2000>;
167179 			interrupts = <0 92 4>;
168180 			interrupt-names = "macirq";
169181 			mac-address = [00 00 00 00 00 00];
170182 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
171183 			reset-names = "stmmaceth", "stmmaceth-ocp";
172
-			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
173
-			clock-names = "stmmaceth";
184
+			clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
185
+			clock-names = "stmmaceth", "ptp_ref";
174186 			tx-fifo-depth = <16384>;
175187 			rx-fifo-depth = <16384>;
176188 			snps,multicast-filter-bins = <256>;
177
-			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
189
+			iommus = <&smmu 3>;
190
+			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
178191 			status = "disabled";
179192 		};
180193 
....@@ -285,6 +298,23 @@
285298 			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
286299 				 <&clkmgr STRATIX10_SDMMC_CLK>;
287300 			clock-names = "biu", "ciu";
301
+			iommus = <&smmu 5>;
302
+			status = "disabled";
303
+		};
304
+
305
+		nand: nand-controller@ffb90000 {
306
+			#address-cells = <1>;
307
+			#size-cells = <0>;
308
+			compatible = "altr,socfpga-denali-nand";
309
+			reg = <0xffb90000 0x10000>,
310
+			      <0xffb80000 0x1000>;
311
+			reg-names = "nand_data", "denali_reg";
312
+			interrupts = <0 97 4>;
313
+			clocks = <&clkmgr STRATIX10_NAND_CLK>,
314
+				 <&clkmgr STRATIX10_NAND_X_CLK>,
315
+				 <&clkmgr STRATIX10_NAND_ECC_CLK>;
316
+			clock-names = "nand", "nand_x", "ecc";
317
+			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
288318 			status = "disabled";
289319 		};
290320 
....@@ -310,13 +340,37 @@
310340 			#dma-requests = <32>;
311341 			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
312342 			clock-names = "apb_pclk";
343
+			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
344
+			reset-names = "dma", "dma-ocp";
313345 		};
314346 
315347 		rst: rstmgr@ffd11000 {
316348 			#reset-cells = <1>;
317
-			compatible = "altr,rst-mgr";
349
+			compatible = "altr,stratix10-rst-mgr";
318350 			reg = <0xffd11000 0x1000>;
319
-			altr,modrst-offset = <0x20>;
351
+		};
352
+
353
+		smmu: iommu@fa000000 {
354
+			compatible = "arm,mmu-500", "arm,smmu-v2";
355
+			reg = <0xfa000000 0x40000>;
356
+			#global-interrupts = <2>;
357
+			#iommu-cells = <1>;
358
+			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
359
+			clock-names = "iommu";
360
+			interrupt-parent = <&intc>;
361
+			interrupts = <0 128 4>,	/* Global Secure Fault */
362
+				<0 129 4>, /* Global Non-secure Fault */
363
+				/* Non-secure Context Interrupts (32) */
364
+				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
365
+				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
366
+				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
367
+				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
368
+				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
369
+				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
370
+				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
371
+				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
372
+			stream-match-mask = <0x7ff0>;
373
+			status = "disabled";
320374 		};
321375 
322376 		spi0: spi@ffda4000 {
....@@ -326,6 +380,7 @@
326380 			reg = <0xffda4000 0x1000>;
327381 			interrupts = <0 99 4>;
328382 			resets = <&rst SPIM0_RESET>;
383
+			reset-names = "spi";
329384 			reg-io-width = <4>;
330385 			num-cs = <4>;
331386 			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
....@@ -339,6 +394,7 @@
339394 			reg = <0xffda5000 0x1000>;
340395 			interrupts = <0 100 4>;
341396 			resets = <&rst SPIM1_RESET>;
397
+			reset-names = "spi";
342398 			reg-io-width = <4>;
343399 			num-cs = <4>;
344400 			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
....@@ -346,7 +402,7 @@
346402 		};
347403 
348404 		sysmgr: sysmgr@ffd12000 {
349
-			compatible = "altr,sys-mgr", "syscon";
405
+			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
350406 			reg = <0xffd12000 0x228>;
351407 		};
352408 
....@@ -391,7 +447,7 @@
391447 			clock-names = "timer";
392448 		};
393449 
394
-		uart0: serial0@ffc02000 {
450
+		uart0: serial@ffc02000 {
395451 			compatible = "snps,dw-apb-uart";
396452 			reg = <0xffc02000 0x100>;
397453 			interrupts = <0 108 4>;
....@@ -402,7 +458,7 @@
402458 			status = "disabled";
403459 		};
404460 
405
-		uart1: serial1@ffc02100 {
461
+		uart1: serial@ffc02100 {
406462 			compatible = "snps,dw-apb-uart";
407463 			reg = <0xffc02100 0x100>;
408464 			interrupts = <0 109 4>;
....@@ -428,6 +484,7 @@
428484 			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
429485 			reset-names = "dwc2", "dwc2-ecc";
430486 			clocks = <&clkmgr STRATIX10_USB_CLK>;
487
+			iommus = <&smmu 6>;
431488 			status = "disabled";
432489 		};
433490 
....@@ -440,6 +497,7 @@
440497 			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
441498 			reset-names = "dwc2", "dwc2-ecc";
442499 			clocks = <&clkmgr STRATIX10_USB_CLK>;
500
+			iommus = <&smmu 7>;
443501 			status = "disabled";
444502 		};
445503 
....@@ -479,16 +537,60 @@
479537 			status = "disabled";
480538 		};
481539 
540
+		sdr: sdr@f8011100 {
541
+			compatible = "altr,sdr-ctl", "syscon";
542
+			reg = <0xf8011100 0xc0>;
543
+		};
544
+
482545 		eccmgr {
483
-			compatible = "altr,socfpga-s10-ecc-manager";
484
-			interrupts = <0 15 4>, <0 95 4>;
546
+			compatible = "altr,socfpga-s10-ecc-manager",
547
+				     "altr,socfpga-a10-ecc-manager";
548
+			altr,sysmgr-syscon = <&sysmgr>;
549
+			#address-cells = <1>;
550
+			#size-cells = <1>;
551
+			interrupts = <0 15 4>;
485552 			interrupt-controller;
486553 			#interrupt-cells = <2>;
554
+			ranges;
487555 
488556 			sdramedac {
489557 				compatible = "altr,sdram-edac-s10";
490
-				interrupts = <16 4>, <48 4>;
558
+				altr,sdr-syscon = <&sdr>;
559
+				interrupts = <16 4>;
491560 			};
561
+
562
+			ocram-ecc@ff8cc000 {
563
+				compatible = "altr,socfpga-s10-ocram-ecc",
564
+					     "altr,socfpga-a10-ocram-ecc";
565
+				reg = <0xff8cc000 0x100>;
566
+				altr,ecc-parent = <&ocram>;
567
+				interrupts = <1 4>;
568
+			};
569
+
570
+			usb0-ecc@ff8c4000 {
571
+				compatible = "altr,socfpga-s10-usb-ecc",
572
+					     "altr,socfpga-usb-ecc";
573
+				reg = <0xff8c4000 0x100>;
574
+				altr,ecc-parent = <&usb0>;
575
+				interrupts = <2 4>;
576
+			};
577
+
578
+			emac0-rx-ecc@ff8c0000 {
579
+				compatible = "altr,socfpga-s10-eth-mac-ecc",
580
+					     "altr,socfpga-eth-mac-ecc";
581
+				reg = <0xff8c0000 0x100>;
582
+				altr,ecc-parent = <&gmac0>;
583
+				interrupts = <4 4>;
584
+			};
585
+
586
+			emac0-tx-ecc@ff8c0400 {
587
+				compatible = "altr,socfpga-s10-eth-mac-ecc",
588
+					     "altr,socfpga-eth-mac-ecc";
589
+				reg = <0xff8c0400 0x100>;
590
+				altr,ecc-parent = <&gmac0>;
591
+				interrupts = <5 4>;
592
+			};
593
+
492594 		};
493595 
494596 		qspi: spi@ff8d2000 {
....@@ -505,5 +607,17 @@
505607 
506608 			status = "disabled";
507609 		};
610
+
611
+		firmware {
612
+			svc {
613
+				compatible = "intel,stratix10-svc";
614
+				method = "smc";
615
+				memory-region = <&service_reserved>;
616
+
617
+				fpga_mgr: fpga-mgr {
618
+					compatible = "intel,stratix10-soc-fpga-mgr";
619
+				};
620
+			};
621
+		};
508622 	};
509623 };