disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/arm/include/asm/io.h
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@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *  arch/arm/include/asm/io.h
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  *
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  *  Copyright (C) 1996-2000 Russell King
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Modifications:
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  *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
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@@ -28,13 +25,11 @@
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 #include <asm/byteorder.h>
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 #include <asm/memory.h>
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 #include <asm-generic/pci_iomap.h>
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-#include <xen/xen.h>
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 /*
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  * ISA I/O bus memory addresses are 1:1 with the physical address.
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  */
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 #define isa_virt_to_bus virt_to_phys
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-#define isa_page_to_bus page_to_phys
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 #define isa_bus_to_virt phys_to_virt
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 /*
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@@ -282,8 +277,6 @@
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 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
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 extern void _memset_io(volatile void __iomem *, int, size_t);
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-#define mmiowb()
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-
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 /*
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  *  Memory access primitives
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  *  ------------------------
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@@ -363,7 +356,6 @@
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  *
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  * Function		Memory type	Cacheability	Cache hint
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  * ioremap()		Device		n/a		n/a
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- * ioremap_nocache()	Device		n/a		n/a
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  * ioremap_cache()	Normal		Writeback	Read allocate
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  * ioremap_wc()		Normal		Non-cacheable	n/a
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  * ioremap_wt()		Normal		Non-cacheable	n/a
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@@ -374,13 +366,6 @@
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  * - number, order and size of accesses are maintained
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  * - unaligned accesses are "unpredictable"
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  * - writes may be delayed before they hit the endpoint device
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- *
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- * ioremap_nocache() is the same as ioremap() as there are too many device
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- * drivers using this for device registers, and documentation which tells
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- * people to use it for such for this to be any different.  This is not a
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- * safe fallback for memory-like mappings, or memory regions where the
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- * compiler may generate unaligned accesses - eg, via inlining its own
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- * memcpy.
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  *
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  * All normal memory mappings have the following properties:
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  * - reads can be repeated with no side effects
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@@ -399,19 +384,12 @@
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  */
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 void __iomem *ioremap(resource_size_t res_cookie, size_t size);
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 #define ioremap ioremap
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-#define ioremap_nocache ioremap
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 /*
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  * Do not use ioremap_cache for mapping memory. Use memremap instead.
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  */
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 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
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 #define ioremap_cache ioremap_cache
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-
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-/*
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- * Do not use ioremap_cached in new code. Provided for the benefit of
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- * the pxa2xx-flash MTD driver only.
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- */
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-void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size);
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 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
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 #define ioremap_wc ioremap_wc
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@@ -459,25 +437,14 @@
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 #include <asm-generic/io.h>
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-/*
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- * can the hardware map this into one segment or not, given no other
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- * constraints.
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- */
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-#define BIOVEC_MERGEABLE(vec1, vec2)	\
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-	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
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-
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-struct bio_vec;
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-extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
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-				      const struct bio_vec *vec2);
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-#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)				\
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-	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&				\
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-	 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
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-
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 #ifdef CONFIG_MMU
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 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
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 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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 extern int devmem_is_allowed(unsigned long pfn);
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+extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
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+					unsigned long flags);
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+#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
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 #endif
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 /*