disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/arm/crypto/sha512-core.S_shipped
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@@ -12,7 +12,7 @@
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 @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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 @ project. The module is, however, dual licensed under OpenSSL and
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 @ CRYPTOGAMS licenses depending on where you obtain it. For further
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-@ details see http://www.openssl.org/~appro/cryptogams/.
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+@ details see https://www.openssl.org/~appro/cryptogams/.
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 @ ====================================================================
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 @ SHA512 block procedure for ARMv4. September 2007.
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@@ -42,7 +42,7 @@
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 @ terms it's 22.6 cycles per byte, which is disappointing result.
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 @ Technical writers asserted that 3-way S4 pipeline can sustain
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 @ multiple NEON instructions per cycle, but dual NEON issue could
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-@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
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+@ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
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 @ for further details. On side note Cortex-A15 processes one byte in
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 @ 16 cycles.
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@@ -79,7 +79,6 @@
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 #else
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 .syntax unified
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 # ifdef __thumb2__
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-#  define adrl adr
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 .thumb
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 # else
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 .code   32
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@@ -543,7 +542,8 @@
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 	dmb				@ errata #451034 on early Cortex A8
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 	add	r2,r1,r2,lsl#7	@ len to point at the end of inp
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 	VFP_ABI_PUSH
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-	adrl	r3,K512
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+	adr	r3,.Lsha512_block_data_order
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+	sub	r3,r3,.Lsha512_block_data_order-K512
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 	vldmia	r0,{d16-d23}		@ load context
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 .Loop_neon:
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 	vshr.u64	d24,d20,#14	@ 0