.. | .. |
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141 | 141 | cooling-maps { |
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142 | 142 | map { |
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143 | 143 | trip = <&cpu_alert>; |
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144 | | - cooling-device = <&cpu0 |
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145 | | - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
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| 144 | + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 145 | + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 146 | + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 147 | + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
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146 | 148 | }; |
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147 | 149 | }; |
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148 | 150 | }; |
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.. | .. |
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155 | 157 | ranges; |
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156 | 158 | interrupt-parent = <&intc>; |
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157 | 159 | |
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158 | | - l2: l2-cache@500c0000 { |
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| 160 | + l2: cache-controller@500c0000 { |
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159 | 161 | compatible = "socionext,uniphier-system-cache"; |
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160 | 162 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, |
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161 | 163 | <0x506c0000 0x400>; |
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.. | .. |
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165 | 167 | cache-sets = <512>; |
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166 | 168 | cache-line-size = <128>; |
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167 | 169 | cache-level = <2>; |
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| 170 | + }; |
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| 171 | + |
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| 172 | + spi0: spi@54006000 { |
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| 173 | + compatible = "socionext,uniphier-scssi"; |
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| 174 | + status = "disabled"; |
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| 175 | + reg = <0x54006000 0x100>; |
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| 176 | + #address-cells = <1>; |
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| 177 | + #size-cells = <0>; |
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| 178 | + interrupts = <0 39 4>; |
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| 179 | + pinctrl-names = "default"; |
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| 180 | + pinctrl-0 = <&pinctrl_spi0>; |
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| 181 | + clocks = <&peri_clk 11>; |
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| 182 | + resets = <&peri_rst 11>; |
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| 183 | + }; |
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| 184 | + |
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| 185 | + spi1: spi@54006100 { |
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| 186 | + compatible = "socionext,uniphier-scssi"; |
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| 187 | + status = "disabled"; |
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| 188 | + reg = <0x54006100 0x100>; |
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| 189 | + #address-cells = <1>; |
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| 190 | + #size-cells = <0>; |
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| 191 | + interrupts = <0 216 4>; |
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| 192 | + pinctrl-names = "default"; |
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| 193 | + pinctrl-0 = <&pinctrl_spi1>; |
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| 194 | + clocks = <&peri_clk 12>; |
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| 195 | + resets = <&peri_rst 12>; |
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168 | 196 | }; |
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169 | 197 | |
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170 | 198 | serial0: serial@54006800 { |
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.. | .. |
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422 | 450 | }; |
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423 | 451 | }; |
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424 | 452 | |
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| 453 | + emmc: mmc@5a000000 { |
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| 454 | + compatible = "socionext,uniphier-sd-v3.1.1"; |
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| 455 | + status = "disabled"; |
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| 456 | + reg = <0x5a000000 0x800>; |
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| 457 | + interrupts = <0 78 4>; |
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| 458 | + pinctrl-names = "default"; |
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| 459 | + pinctrl-0 = <&pinctrl_emmc>; |
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| 460 | + clocks = <&sd_clk 1>; |
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| 461 | + reset-names = "host", "hw"; |
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| 462 | + resets = <&sd_rst 1>, <&sd_rst 6>; |
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| 463 | + bus-width = <8>; |
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| 464 | + cap-mmc-highspeed; |
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| 465 | + cap-mmc-hw-reset; |
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| 466 | + non-removable; |
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| 467 | + }; |
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| 468 | + |
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| 469 | + sd: mmc@5a400000 { |
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| 470 | + compatible = "socionext,uniphier-sd-v3.1.1"; |
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| 471 | + status = "disabled"; |
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| 472 | + reg = <0x5a400000 0x800>; |
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| 473 | + interrupts = <0 76 4>; |
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| 474 | + pinctrl-names = "default", "uhs"; |
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| 475 | + pinctrl-0 = <&pinctrl_sd>; |
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| 476 | + pinctrl-1 = <&pinctrl_sd_uhs>; |
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| 477 | + clocks = <&sd_clk 0>; |
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| 478 | + reset-names = "host"; |
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| 479 | + resets = <&sd_rst 0>; |
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| 480 | + bus-width = <4>; |
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| 481 | + cap-sd-highspeed; |
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| 482 | + sd-uhs-sdr12; |
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| 483 | + sd-uhs-sdr25; |
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| 484 | + sd-uhs-sdr50; |
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| 485 | + }; |
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| 486 | + |
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425 | 487 | soc_glue: soc-glue@5f800000 { |
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426 | 488 | compatible = "socionext,uniphier-pxs2-soc-glue", |
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427 | 489 | "simple-mfd", "syscon"; |
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.. | .. |
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450 | 512 | }; |
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451 | 513 | }; |
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452 | 514 | |
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453 | | - aidet: aidet@5fc20000 { |
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| 515 | + xdmac: dma-controller@5fc10000 { |
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| 516 | + compatible = "socionext,uniphier-xdmac"; |
---|
| 517 | + reg = <0x5fc10000 0x5300>; |
---|
| 518 | + interrupts = <0 188 4>; |
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| 519 | + dma-channels = <16>; |
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| 520 | + #dma-cells = <2>; |
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| 521 | + }; |
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| 522 | + |
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| 523 | + aidet: interrupt-controller@5fc20000 { |
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454 | 524 | compatible = "socionext,uniphier-pxs2-aidet"; |
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455 | 525 | reg = <0x5fc20000 0x200>; |
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456 | 526 | interrupt-controller; |
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.. | .. |
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523 | 593 | }; |
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524 | 594 | }; |
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525 | 595 | |
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526 | | - nand: nand@68000000 { |
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| 596 | + usb0: usb@65a00000 { |
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| 597 | + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; |
---|
| 598 | + status = "disabled"; |
---|
| 599 | + reg = <0x65a00000 0xcd00>; |
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| 600 | + interrupt-names = "dwc_usb3"; |
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| 601 | + interrupts = <0 134 4>; |
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| 602 | + pinctrl-names = "default"; |
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| 603 | + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; |
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| 604 | + clock-names = "ref", "bus_early", "suspend"; |
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| 605 | + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; |
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| 606 | + resets = <&usb0_rst 15>; |
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| 607 | + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, |
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| 608 | + <&usb0_ssphy0>, <&usb0_ssphy1>; |
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| 609 | + dr_mode = "host"; |
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| 610 | + }; |
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| 611 | + |
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| 612 | + usb-glue@65b00000 { |
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| 613 | + compatible = "socionext,uniphier-pxs2-dwc3-glue", |
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| 614 | + "simple-mfd"; |
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| 615 | + #address-cells = <1>; |
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| 616 | + #size-cells = <1>; |
---|
| 617 | + ranges = <0 0x65b00000 0x400>; |
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| 618 | + |
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| 619 | + usb0_rst: reset@0 { |
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| 620 | + compatible = "socionext,uniphier-pxs2-usb3-reset"; |
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| 621 | + reg = <0x0 0x4>; |
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| 622 | + #reset-cells = <1>; |
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| 623 | + clock-names = "link"; |
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| 624 | + clocks = <&sys_clk 14>; |
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| 625 | + reset-names = "link"; |
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| 626 | + resets = <&sys_rst 14>; |
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| 627 | + }; |
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| 628 | + |
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| 629 | + usb0_vbus0: regulator@100 { |
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| 630 | + compatible = "socionext,uniphier-pxs2-usb3-regulator"; |
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| 631 | + reg = <0x100 0x10>; |
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| 632 | + clock-names = "link"; |
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| 633 | + clocks = <&sys_clk 14>; |
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| 634 | + reset-names = "link"; |
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| 635 | + resets = <&sys_rst 14>; |
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| 636 | + }; |
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| 637 | + |
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| 638 | + usb0_vbus1: regulator@110 { |
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| 639 | + compatible = "socionext,uniphier-pxs2-usb3-regulator"; |
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| 640 | + reg = <0x110 0x10>; |
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| 641 | + clock-names = "link"; |
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| 642 | + clocks = <&sys_clk 14>; |
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| 643 | + reset-names = "link"; |
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| 644 | + resets = <&sys_rst 14>; |
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| 645 | + }; |
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| 646 | + |
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| 647 | + usb0_hsphy0: hs-phy@200 { |
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| 648 | + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; |
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| 649 | + reg = <0x200 0x10>; |
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| 650 | + #phy-cells = <0>; |
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| 651 | + clock-names = "link", "phy"; |
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| 652 | + clocks = <&sys_clk 14>, <&sys_clk 16>; |
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| 653 | + reset-names = "link", "phy"; |
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| 654 | + resets = <&sys_rst 14>, <&sys_rst 16>; |
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| 655 | + vbus-supply = <&usb0_vbus0>; |
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| 656 | + }; |
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| 657 | + |
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| 658 | + usb0_hsphy1: hs-phy@210 { |
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| 659 | + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; |
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| 660 | + reg = <0x210 0x10>; |
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| 661 | + #phy-cells = <0>; |
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| 662 | + clock-names = "link", "phy"; |
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| 663 | + clocks = <&sys_clk 14>, <&sys_clk 16>; |
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| 664 | + reset-names = "link", "phy"; |
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| 665 | + resets = <&sys_rst 14>, <&sys_rst 16>; |
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| 666 | + vbus-supply = <&usb0_vbus1>; |
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| 667 | + }; |
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| 668 | + |
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| 669 | + usb0_ssphy0: ss-phy@300 { |
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| 670 | + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; |
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| 671 | + reg = <0x300 0x10>; |
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| 672 | + #phy-cells = <0>; |
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| 673 | + clock-names = "link", "phy"; |
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| 674 | + clocks = <&sys_clk 14>, <&sys_clk 17>; |
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| 675 | + reset-names = "link", "phy"; |
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| 676 | + resets = <&sys_rst 14>, <&sys_rst 17>; |
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| 677 | + vbus-supply = <&usb0_vbus0>; |
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| 678 | + }; |
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| 679 | + |
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| 680 | + usb0_ssphy1: ss-phy@310 { |
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| 681 | + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; |
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| 682 | + reg = <0x310 0x10>; |
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| 683 | + #phy-cells = <0>; |
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| 684 | + clock-names = "link", "phy"; |
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| 685 | + clocks = <&sys_clk 14>, <&sys_clk 18>; |
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| 686 | + reset-names = "link", "phy"; |
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| 687 | + resets = <&sys_rst 14>, <&sys_rst 18>; |
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| 688 | + vbus-supply = <&usb0_vbus1>; |
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| 689 | + }; |
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| 690 | + }; |
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| 691 | + |
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| 692 | + usb1: usb@65c00000 { |
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| 693 | + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; |
---|
| 694 | + status = "disabled"; |
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| 695 | + reg = <0x65c00000 0xcd00>; |
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| 696 | + interrupt-names = "dwc_usb3"; |
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| 697 | + interrupts = <0 137 4>; |
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| 698 | + pinctrl-names = "default"; |
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| 699 | + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; |
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| 700 | + clock-names = "ref", "bus_early", "suspend"; |
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| 701 | + clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; |
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| 702 | + resets = <&usb1_rst 15>; |
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| 703 | + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; |
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| 704 | + dr_mode = "host"; |
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| 705 | + }; |
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| 706 | + |
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| 707 | + usb-glue@65d00000 { |
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| 708 | + compatible = "socionext,uniphier-pxs2-dwc3-glue", |
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| 709 | + "simple-mfd"; |
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| 710 | + #address-cells = <1>; |
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| 711 | + #size-cells = <1>; |
---|
| 712 | + ranges = <0 0x65d00000 0x400>; |
---|
| 713 | + |
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| 714 | + usb1_rst: reset@0 { |
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| 715 | + compatible = "socionext,uniphier-pxs2-usb3-reset"; |
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| 716 | + reg = <0x0 0x4>; |
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| 717 | + #reset-cells = <1>; |
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| 718 | + clock-names = "link"; |
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| 719 | + clocks = <&sys_clk 15>; |
---|
| 720 | + reset-names = "link"; |
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| 721 | + resets = <&sys_rst 15>; |
---|
| 722 | + }; |
---|
| 723 | + |
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| 724 | + usb1_vbus0: regulator@100 { |
---|
| 725 | + compatible = "socionext,uniphier-pxs2-usb3-regulator"; |
---|
| 726 | + reg = <0x100 0x10>; |
---|
| 727 | + clock-names = "link"; |
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| 728 | + clocks = <&sys_clk 15>; |
---|
| 729 | + reset-names = "link"; |
---|
| 730 | + resets = <&sys_rst 15>; |
---|
| 731 | + }; |
---|
| 732 | + |
---|
| 733 | + usb1_vbus1: regulator@110 { |
---|
| 734 | + compatible = "socionext,uniphier-pxs2-usb3-regulator"; |
---|
| 735 | + reg = <0x110 0x10>; |
---|
| 736 | + clock-names = "link"; |
---|
| 737 | + clocks = <&sys_clk 15>; |
---|
| 738 | + reset-names = "link"; |
---|
| 739 | + resets = <&sys_rst 15>; |
---|
| 740 | + }; |
---|
| 741 | + |
---|
| 742 | + usb1_hsphy0: hs-phy@200 { |
---|
| 743 | + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; |
---|
| 744 | + reg = <0x200 0x10>; |
---|
| 745 | + #phy-cells = <0>; |
---|
| 746 | + clock-names = "link", "phy"; |
---|
| 747 | + clocks = <&sys_clk 15>, <&sys_clk 20>; |
---|
| 748 | + reset-names = "link", "phy"; |
---|
| 749 | + resets = <&sys_rst 15>, <&sys_rst 20>; |
---|
| 750 | + vbus-supply = <&usb1_vbus0>; |
---|
| 751 | + }; |
---|
| 752 | + |
---|
| 753 | + usb1_hsphy1: hs-phy@210 { |
---|
| 754 | + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; |
---|
| 755 | + reg = <0x210 0x10>; |
---|
| 756 | + #phy-cells = <0>; |
---|
| 757 | + clock-names = "link", "phy"; |
---|
| 758 | + clocks = <&sys_clk 15>, <&sys_clk 20>; |
---|
| 759 | + reset-names = "link", "phy"; |
---|
| 760 | + resets = <&sys_rst 15>, <&sys_rst 20>; |
---|
| 761 | + vbus-supply = <&usb1_vbus1>; |
---|
| 762 | + }; |
---|
| 763 | + |
---|
| 764 | + usb1_ssphy0: ss-phy@300 { |
---|
| 765 | + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; |
---|
| 766 | + reg = <0x300 0x10>; |
---|
| 767 | + #phy-cells = <0>; |
---|
| 768 | + clock-names = "link", "phy"; |
---|
| 769 | + clocks = <&sys_clk 15>, <&sys_clk 21>; |
---|
| 770 | + reset-names = "link", "phy"; |
---|
| 771 | + resets = <&sys_rst 15>, <&sys_rst 21>; |
---|
| 772 | + vbus-supply = <&usb1_vbus0>; |
---|
| 773 | + }; |
---|
| 774 | + }; |
---|
| 775 | + |
---|
| 776 | + nand: nand-controller@68000000 { |
---|
527 | 777 | compatible = "socionext,uniphier-denali-nand-v5b"; |
---|
528 | 778 | status = "disabled"; |
---|
529 | 779 | reg-names = "nand_data", "denali_reg"; |
---|
530 | 780 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
---|
| 781 | + #address-cells = <1>; |
---|
| 782 | + #size-cells = <0>; |
---|
531 | 783 | interrupts = <0 65 4>; |
---|
532 | 784 | pinctrl-names = "default"; |
---|
533 | | - pinctrl-0 = <&pinctrl_nand2cs>; |
---|
534 | | - clocks = <&sys_clk 2>; |
---|
535 | | - resets = <&sys_rst 2>; |
---|
| 785 | + pinctrl-0 = <&pinctrl_nand>; |
---|
| 786 | + clock-names = "nand", "nand_x", "ecc"; |
---|
| 787 | + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; |
---|
| 788 | + reset-names = "nand", "reg"; |
---|
| 789 | + resets = <&sys_rst 2>, <&sys_rst 2>; |
---|
536 | 790 | }; |
---|
537 | 791 | }; |
---|
538 | 792 | }; |
---|