forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/arm/boot/dts/rk322x.dtsi
....@@ -5,12 +5,7 @@
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
66 #include <dt-bindings/pinctrl/rockchip.h>
77 #include <dt-bindings/clock/rk3228-cru.h>
8
-#include <dt-bindings/power/rk3228-power.h>
9
-#include <dt-bindings/suspend/rockchip-rk322x.h>
10
-#include <dt-bindings/soc/rockchip,boot-mode.h>
118 #include <dt-bindings/thermal/thermal.h>
12
-#include <dt-bindings/soc/rockchip-system-status.h>
13
-#include "rk322x-dram-default-timing.dtsi"
149 
1510 / {
1611 	#address-cells = <1>;
....@@ -20,6 +15,10 @@
2015 
2116 	aliases {
2217 		ethernet0 = &gmac;
18
+		gpio0 = &gpio0;
19
+		gpio1 = &gpio1;
20
+		gpio2 = &gpio2;
21
+		gpio3 = &gpio3;
2322 		serial0 = &uart0;
2423 		serial1 = &uart1;
2524 		serial2 = &uart2;
....@@ -37,7 +36,6 @@
3736 			resets = <&cru SRST_CORE0>;
3837 			operating-points-v2 = <&cpu0_opp_table>;
3938 			#cooling-cells = <2>; /* min followed by max */
40
-			dynamic-power-coefficient = <122>;
4139 			clock-latency = <40000>;
4240 			clocks = <&cru ARMCLK>;
4341 			enable-method = "psci";
....@@ -78,50 +76,31 @@
7876 		compatible = "operating-points-v2";
7977 		opp-shared;
8078 
81
-		clocks = <&cru PLL_APLL>;
82
-		rockchip,max-volt = <1350000>;
83
-		rockchip,leakage-voltage-sel = <
84
-			1   8     0
85
-			9   254   1
86
-		>;
87
-		nvmem-cells = <&cpu_leakage>;
88
-		nvmem-cell-names = "cpu_leakage";
89
-
9079 		opp-408000000 {
9180 			opp-hz = /bits/ 64 <408000000>;
92
-			opp-microvolt = <950000 950000 1275000>;
93
-			opp-microvolt-L0 = <950000 950000 1275000>;
94
-			opp-microvolt-L1 = <950000 950000 1275000>;
81
+			opp-microvolt = <950000>;
9582 			clock-latency-ns = <40000>;
9683 			opp-suspend;
9784 		};
9885 		opp-600000000 {
9986 			opp-hz = /bits/ 64 <600000000>;
100
-			opp-microvolt = <975000 975000 1275000>;
101
-			opp-microvolt-L0 = <975000 975000 1275000>;
102
-			opp-microvolt-L1 = <975000 975000 1275000>;
87
+			opp-microvolt = <975000>;
10388 		};
10489 		opp-816000000 {
10590 			opp-hz = /bits/ 64 <816000000>;
106
-			opp-microvolt = <1000000 1000000 1275000>;
107
-			opp-microvolt-L0 = <1000000 1000000 1275000>;
108
-			opp-microvolt-L1 = <1000000 1000000 1275000>;
91
+			opp-microvolt = <1000000>;
10992 		};
11093 		opp-1008000000 {
11194 			opp-hz = /bits/ 64 <1008000000>;
112
-			opp-microvolt = <1175000 1175000 1275000>;
113
-			opp-microvolt-L0 = <1175000 1175000 1275000>;
114
-			opp-microvolt-L1 = <1125000 1125000 1275000>;
95
+			opp-microvolt = <1175000>;
11596 		};
11697 		opp-1200000000 {
11798 			opp-hz = /bits/ 64 <1200000000>;
118
-			opp-microvolt = <1275000 1275000 1275000>;
119
-			opp-microvolt-L0 = <1275000 1275000 1275000>;
120
-			opp-microvolt-L1 = <1225000 1225000 1275000>;
99
+			opp-microvolt = <1275000>;
121100 		};
122101 	};
123102 
124
-	amba {
103
+	amba: bus {
125104 		compatible = "simple-bus";
126105 		#address-cells = <1>;
127106 		#size-cells = <1>;
....@@ -133,9 +112,9 @@
133112 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134113 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
135114 			#dma-cells = <1>;
115
+			arm,pl330-periph-burst;
136116 			clocks = <&cru ACLK_DMAC>;
137117 			clock-names = "apb_pclk";
138
-			arm,pl330-periph-burst;
139118 		};
140119 	};
141120 
....@@ -148,92 +127,6 @@
148127 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
149128 	};
150129 
151
-	dmc: dmc {
152
-		compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
153
-		clocks = <&cru SCLK_DDRC>;
154
-		clock-names = "dmc_clk";
155
-		operating-points-v2 = <&dmc_opp_table>;
156
-		system-status-freq = <
157
-			/*system status         freq(KHz)*/
158
-			SYS_STATUS_NORMAL       600000
159
-			SYS_STATUS_VIDEO_4K	666000
160
-			SYS_STATUS_VIDEO_4K_10B 786000
161
-		>;
162
-		dram_freq = <786000000>;
163
-		rockchip,dram_timing = <&dram_timing>;
164
-		#cooling-cells = <2>;
165
-		status = "disabled";
166
-
167
-		ddr_power_model: ddr_power_model {
168
-			compatible = "ddr_power_model";
169
-			dynamic-power-coefficient = <120>;
170
-			static-power-coefficient = <200>;
171
-			ts = <32000 4700 (-80) 2>;
172
-			thermal-zone = "soc-thermal";
173
-		};
174
-	};
175
-
176
-	dmc_opp_table: dmc-opp-table {
177
-		compatible = "operating-points-v2";
178
-
179
-		rockchip,leakage-voltage-sel = <
180
-			1   5    0
181
-			6   254  1
182
-		>;
183
-		nvmem-cells = <&logic_leakage>;
184
-		nvmem-cell-names = "ddr_leakage";
185
-
186
-		opp-300000000 {
187
-			opp-hz = /bits/ 64 <300000000>;
188
-			opp-microvolt = <1050000>;
189
-			opp-microvolt-L0 = <1050000>;
190
-			opp-microvolt-L1 = <1000000>;
191
-		};
192
-		opp-400000000 {
193
-			opp-hz = /bits/ 64 <400000000>;
194
-			opp-microvolt = <1050000>;
195
-			opp-microvolt-L0 = <1050000>;
196
-			opp-microvolt-L1 = <1000000>;
197
-		};
198
-		opp-600000000 {
199
-			opp-hz = /bits/ 64 <600000000>;
200
-			opp-microvolt = <1100000>;
201
-			opp-microvolt-L0 = <1100000>;
202
-			opp-microvolt-L1 = <1050000>;
203
-		};
204
-		opp-666000000 {
205
-			opp-hz = /bits/ 64 <666000000>;
206
-			opp-microvolt = <1150000>;
207
-			opp-microvolt-L0 = <1150000>;
208
-			opp-microvolt-L1 = <1100000>;
209
-		};
210
-		opp-700000000 {
211
-			opp-hz = /bits/ 64 <700000000>;
212
-			opp-microvolt = <1150000>;
213
-			opp-microvolt-L0 = <1150000>;
214
-			opp-microvolt-L1 = <1100000>;
215
-		};
216
-		opp-786000000 {
217
-			opp-hz = /bits/ 64 <786000000>;
218
-			opp-microvolt = <1150000>;
219
-			opp-microvolt-L0 = <1150000>;
220
-			opp-microvolt-L1 = <1100000>;
221
-		};
222
-		opp-800000000 {
223
-			opp-hz = /bits/ 64 <800000000>;
224
-			opp-microvolt = <1150000>;
225
-			opp-microvolt-L0 = <1150000>;
226
-			opp-microvolt-L1 = <1100000>;
227
-		};
228
-	};
229
-
230
-	firmware {
231
-		optee: optee {
232
-			compatible = "linaro,optee-tz";
233
-			method = "smc";
234
-		};
235
-	};
236
-
237130 	psci {
238131 		compatible = "arm,psci-1.0", "arm,psci-0.2";
239132 		method = "smc";
....@@ -241,6 +134,7 @@
241134 
242135 	timer {
243136 		compatible = "arm,armv7-timer";
137
+		arm,cpu-registers-not-fw-configured;
244138 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
245139 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
246140 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
....@@ -255,24 +149,15 @@
255149 		#clock-cells = <0>;
256150 	};
257151 
258
-	rng: rng@100a0000 {
259
-		compatible = "rockchip,cryptov1-rng";
260
-		reg = <0x100a0000 0x4000>;
261
-		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_S_CRYPTO>;
262
-		clock-names = "clk_crypto", "hclk_crypto";
263
-		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_S_CRYPTO>;
264
-		assigned-clock-rates = <150000000>, <100000000>;
265
-		resets = <&cru SRST_CRYPTO>;
266
-		reset-names = "reset";
267
-		status = "disabled";
152
+	display_subsystem: display-subsystem {
153
+		compatible = "rockchip,display-subsystem";
154
+		ports = <&vop_out>;
268155 	};
269156 
270157 	i2s1: i2s1@100b0000 {
271158 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
272159 		reg = <0x100b0000 0x4000>;
273160 		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
274
-		#address-cells = <1>;
275
-		#size-cells = <0>;
276161 		clock-names = "i2s_clk", "i2s_hclk";
277162 		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
278163 		dmas = <&pdma 14>, <&pdma 15>;
....@@ -288,8 +173,6 @@
288173 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
289174 		reg = <0x100c0000 0x4000>;
290175 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
291
-		#address-cells = <1>;
292
-		#size-cells = <0>;
293176 		clock-names = "i2s_clk", "i2s_hclk";
294177 		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
295178 		dmas = <&pdma 11>, <&pdma 12>;
....@@ -316,37 +199,12 @@
316199 		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
317200 		reg = <0x100e0000 0x4000>;
318201 		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
319
-		#address-cells = <1>;
320
-		#size-cells = <0>;
321202 		clock-names = "i2s_clk", "i2s_hclk";
322203 		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
323204 		dmas = <&pdma 0>, <&pdma 1>;
324205 		dma-names = "tx", "rx";
325206 		resets = <&cru SRST_I2S2>;
326207 		reset-names = "reset-m";
327
-		status = "disabled";
328
-	};
329
-
330
-	tsp: tsp@100f0000 {
331
-		compatible = "rockchip,rk3228-tsp";
332
-		reg = <0x100f0000 0x10000>;
333
-		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
334
-		interrupt-names = "irq_tsp";
335
-		clocks = <&cru SCLK_TSP>, <&cru HCLK_TSP>, <&cru SCLK_HSADC>;
336
-		clock-names = "clk_tsp", "hclk_tsp", "aclk_tsp";
337
-		pinctrl-names = "default";
338
-		pinctrl-0 = <&tsp_d0
339
-			     &tsp_d1
340
-			     &tsp_d2
341
-			     &tsp_d3
342
-			     &tsp_d4
343
-			     &tsp_d5
344
-			     &tsp_d6
345
-			     &tsp_d7
346
-			     &tsp_sync
347
-			     &tsp_clk
348
-			     &tsp_fail
349
-			     &tsp_valid>;
350208 		status = "disabled";
351209 	};
352210 
....@@ -359,16 +217,6 @@
359217 		io_domains: io-domains {
360218 			compatible = "rockchip,rk3228-io-voltage-domain";
361219 			status = "disabled";
362
-		};
363
-
364
-		reboot_mode: reboot-mode {
365
-			compatible = "syscon-reboot-mode";
366
-			offset = <0x5c8>;
367
-			mode-normal = <BOOT_NORMAL>;
368
-			mode-recovery = <BOOT_RECOVERY>;
369
-			mode-bootloader = <BOOT_FASTBOOT>;
370
-			mode-loader = <BOOT_BL_DOWNLOAD>;
371
-			mode-ums = <BOOT_UMS>;
372220 		};
373221 
374222 		u2phy0: usb2-phy@760 {
....@@ -419,29 +267,6 @@
419267 				interrupt-names = "linestate";
420268 				#phy-cells = <0>;
421269 				status = "disabled";
422
-			};
423
-		};
424
-
425
-		power: power-controller {
426
-			compatible = "rockchip,rk3228-power-controller";
427
-			#power-domain-cells = <1>;
428
-			#address-cells = <1>;
429
-			#size-cells = <0>;
430
-			status = "okay";
431
-
432
-			pd_vpu@RK3228_PD_VPU {
433
-				reg = <RK3228_PD_VPU>;
434
-				clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
435
-				pm_qos = <&qos_vpu>;
436
-			};
437
-
438
-			pd_rkvdec@RK3228_PD_RKVDEC {
439
-				reg = <RK3228_PD_RKVDEC>;
440
-				clocks = <&cru ACLK_RKVDEC>,
441
-					 <&cru HCLK_RKVDEC>,
442
-					 <&cru SCLK_VDEC_CABAC>,
443
-					 <&cru SCLK_VDEC_CORE>;
444
-				pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
445270 			};
446271 		};
447272 	};
....@@ -502,17 +327,6 @@
502327 		};
503328 		cpu_leakage: cpu_leakage@17 {
504329 			reg = <0x17 0x1>;
505
-		};
506
-		logic_leakage: logic-leakage@19 {
507
-			reg = <0x19 0x1>;
508
-		};
509
-		hdmi_phy_flag: hdmi_phy_flag@1d {
510
-			reg = <0x1d 0x1>;
511
-			bits = <1 1>;
512
-		};
513
-		tve_dac: tve_dac@1d {
514
-			reg = <0x1d 0x1>;
515
-			bits = <3 5>;
516330 		};
517331 	};
518332 
....@@ -625,8 +439,7 @@
625439 	pwm3: pwm@110b0030 {
626440 		compatible = "rockchip,rk3288-pwm";
627441 		reg = <0x110b0030 0x10>;
628
-		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
629
-		#pwm-cells = <3>;
442
+		#pwm-cells = <2>;
630443 		clocks = <&cru PCLK_PWM>;
631444 		clock-names = "pwm";
632445 		pinctrl-names = "active";
....@@ -653,36 +466,35 @@
653466 			<&cru PLL_CPLL>, <&cru ACLK_PERI>,
654467 			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
655468 			<&cru ACLK_CPU>, <&cru HCLK_CPU>,
656
-			<&cru PCLK_CPU>, <&cru ACLK_VOP>;
469
+			<&cru PCLK_CPU>;
657470 		assigned-clock-rates =
658
-			<1200000000>, <816000000>,
471
+			<594000000>, <816000000>,
659472 			<500000000>, <150000000>,
660473 			<150000000>, <75000000>,
661474 			<150000000>, <150000000>,
662
-			<75000000>, <400000000>;
475
+			<75000000>;
663476 	};
664477 
665
-	thermal_zones: thermal-zones {
666
-		soc_thermal: soc-thermal {
478
+	thermal-zones {
479
+		cpu_thermal: cpu-thermal {
667480 			polling-delay-passive = <100>; /* milliseconds */
668481 			polling-delay = <5000>; /* milliseconds */
669
-			sustainable-power = <1200>; /* milliwatts */
670482 
671483 			thermal-sensors = <&tsadc 0>;
672484 
673485 			trips {
674
-				threshold: trip-point@0 {
486
+				cpu_alert0: cpu_alert0 {
675487 					temperature = <70000>; /* millicelsius */
676488 					hysteresis = <2000>; /* millicelsius */
677489 					type = "passive";
678490 				};
679
-				target: trip-point@1 {
680
-					temperature = <85000>; /* millicelsius */
491
+				cpu_alert1: cpu_alert1 {
492
+					temperature = <75000>; /* millicelsius */
681493 					hysteresis = <2000>; /* millicelsius */
682494 					type = "passive";
683495 				};
684
-				soc_crit: soc-crit {
685
-					temperature = <115000>; /* millicelsius */
496
+				cpu_crit: cpu_crit {
497
+					temperature = <90000>; /* millicelsius */
686498 					hysteresis = <2000>; /* millicelsius */
687499 					type = "critical";
688500 				};
....@@ -690,28 +502,20 @@
690502 
691503 			cooling-maps {
692504 				map0 {
693
-					trip = <&target>;
505
+					trip = <&cpu_alert0>;
694506 					cooling-device =
695
-					<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
696
-					contribution = <1024>;
507
+						<&cpu0 THERMAL_NO_LIMIT 6>,
508
+						<&cpu1 THERMAL_NO_LIMIT 6>,
509
+						<&cpu2 THERMAL_NO_LIMIT 6>,
510
+						<&cpu3 THERMAL_NO_LIMIT 6>;
697511 				};
698512 				map1 {
699
-					trip = <&target>;
513
+					trip = <&cpu_alert1>;
700514 					cooling-device =
701
-					<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
702
-					contribution = <1024>;
703
-				};
704
-				map2 {
705
-					trip = <&target>;
706
-					cooling-device =
707
-					<&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
708
-					contribution = <1024>;
709
-				};
710
-				map3 {
711
-					trip = <&target>;
712
-					cooling-device =
713
-					<&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
714
-					contribution = <1024>;
515
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
516
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
517
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
518
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
715519 				};
716520 			};
717521 		};
....@@ -728,230 +532,68 @@
728532 		resets = <&cru SRST_TSADC>;
729533 		reset-names = "tsadc-apb";
730534 		pinctrl-names = "gpio", "otpout";
731
-		pinctrl-0 = <&otp_gpio>;
535
+		pinctrl-0 = <&otp_pin>;
732536 		pinctrl-1 = <&otp_out>;
733
-		#thermal-sensor-cells = <0>;
734
-		rockchip,hw-tshut-temp = <120000>;
735
-		status = "disabled";
736
-	};
737
-
738
-	codec: codec@12010000 {
739
-		compatible = "rockchip,rk3228-codec";
740
-		reg = <0x12010000 0x1000>;
741
-		clocks =  <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
742
-		clock-names = "mclk", "pclk", "sclk";
743
-		spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
537
+		#thermal-sensor-cells = <1>;
538
+		rockchip,hw-tshut-temp = <95000>;
744539 		status = "disabled";
745540 	};
746541 
747542 	hdmi_phy: hdmi-phy@12030000 {
748543 		compatible = "rockchip,rk3228-hdmi-phy";
749544 		reg = <0x12030000 0x10000>;
750
-		#phy-cells = <0>;
751
-		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
752
-		clock-names = "sysclk", "refclk";
545
+		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
546
+		clock-names = "sysclk", "refoclk", "refpclk";
753547 		#clock-cells = <0>;
754548 		clock-output-names = "hdmiphy_phy";
755
-		nvmem-cells = <&hdmi_phy_flag>;
756
-		nvmem-cell-names = "hdmi_phy_flag";
549
+		#phy-cells = <0>;
757550 		status = "disabled";
758551 	};
759552 
760553 	gpu: gpu@20000000 {
761
-		compatible = "arm,mali400";
554
+		compatible = "rockchip,rk3228-mali", "arm,mali-400";
762555 		reg = <0x20000000 0x10000>;
763
-
764556 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
765557 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
766558 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
767559 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
768560 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
769561 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
770
-
771
-		interrupt-names = "Mali_GP_IRQ",
772
-				  "Mali_GP_MMU_IRQ",
773
-				  "Mali_PP0_IRQ",
774
-				  "Mali_PP0_MMU_IRQ",
775
-				  "Mali_PP1_IRQ",
776
-				  "Mali_PP1_MMU_IRQ";
777
-		clocks = <&cru ACLK_GPU>;
778
-		#cooling-cells = <2>; /* min followed by max */
779
-		clock-names = "clk_mali";
780
-		operating-points-v2 = <&gpu_opp_table>;
781
-		status = "disabled";
782
-
783
-		gpu_power_model: power_model {
784
-			compatible = "arm,mali-simple-power-model";
785
-			voltage = <900>;
786
-			frequency = <500>;
787
-			static-power = <300>;
788
-			dynamic-power = <396>;
789
-			ts = <32000 4700 (-80) 2>;
790
-			thermal-zone = "soc-thermal";
791
-		};
792
-	};
793
-
794
-	gpu_opp_table: opp-table2 {
795
-		compatible = "operating-points-v2";
796
-
797
-		rockchip,leakage-voltage-sel = <
798
-			1   5    0
799
-			6   254  1
800
-		>;
801
-		nvmem-cells = <&logic_leakage>;
802
-		nvmem-cell-names = "gpu_leakage";
803
-
804
-		opp-200000000 {
805
-			opp-hz = /bits/ 64 <200000000>;
806
-			opp-microvolt = <1050000>;
807
-			opp-microvolt-L0 = <1050000>;
808
-			opp-microvolt-L1 = <1000000>;
809
-		};
810
-		opp-300000000 {
811
-			opp-hz = /bits/ 64 <300000000>;
812
-			opp-microvolt = <1050000>;
813
-			opp-microvolt-L0 = <1050000>;
814
-			opp-microvolt-L1 = <1000000>;
815
-		};
816
-		opp-500000000 {
817
-			opp-hz = /bits/ 64 <500000000>;
818
-			opp-microvolt = <1150000>;
819
-			opp-microvolt-L0 = <1150000>;
820
-			opp-microvolt-L1 = <1100000>;
821
-		};
822
-	};
823
-
824
-	mpp_srv: mpp-srv {
825
-		compatible = "rockchip,mpp-service";
826
-		rockchip,taskqueue-count = <2>;
827
-		rockchip,resetgroup-count = <2>;
828
-		status = "disabled";
829
-	};
830
-
831
-	vepu: vepu@20020000 {
832
-		compatible = "rockchip,vpu-encoder-v2";
833
-		reg = <0x20020000 0x400>;
834
-		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
835
-		interrupt-names = "irq_enc";
836
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
837
-		clock-names = "aclk_vcodec", "hclk_vcodec";
838
-		resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>;
839
-		reset-names = "shared_video_a", "shared_video_h";
840
-		iommus = <&vpu_mmu>;
841
-		power-domains = <&power RK3228_PD_VPU>;
842
-		rockchip,srv = <&mpp_srv>;
843
-		rockchip,taskqueue-node = <0>;
844
-		rockchip,resetgroup-node = <0>;
845
-		status = "disabled";
846
-	};
847
-
848
-	vdpu: vdpu@20020400 {
849
-		compatible = "rockchip,vpu-decoder-v2";
850
-		reg = <0x20020400 0x400>;
851
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
852
-		interrupt-names = "irq_dec";
853
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
854
-		clock-names = "aclk_vcodec", "hclk_vcodec";
855
-		resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>;
856
-		reset-names = "shared_video_a", "shared_video_h";
857
-		iommus = <&vpu_mmu>;
858
-		power-domains = <&power RK3228_PD_VPU>;
859
-		rockchip,srv = <&mpp_srv>;
860
-		rockchip,taskqueue-node = <0>;
861
-		rockchip,resetgroup-node = <0>;
562
+		interrupt-names = "gp",
563
+				  "gpmmu",
564
+				  "pp0",
565
+				  "ppmmu0",
566
+				  "pp1",
567
+				  "ppmmu1";
568
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
569
+		clock-names = "bus", "core";
570
+		resets = <&cru SRST_GPU_A>;
862571 		status = "disabled";
863572 	};
864573 
865574 	vpu_mmu: iommu@20020800 {
866575 		compatible = "rockchip,iommu";
867
-		reg = <0x20020800 0x40>;
576
+		reg = <0x20020800 0x100>;
868577 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
869
-		interrupt-names = "vpu_mmu";
870578 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
871579 		clock-names = "aclk", "iface";
872
-		power-domains = <&power RK3228_PD_VPU>;
873580 		#iommu-cells = <0>;
874581 		status = "disabled";
875582 	};
876583 
877
-	rkvdec: rkvdec@20030000 {
878
-		compatible = "rockchip,rkv-decoder-v1";
879
-		reg = <0x20030000 0x400>;
880
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
881
-		interrupt-names = "irq_dec";
882
-		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
883
-			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
884
-		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
885
-			"clk_core";
886
-		resets = <&cru SRST_RKVDEC_A>, <&cru SRST_RKVDEC_H>,
887
-			<&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>,
888
-			<&cru SRST_RKVDEC_CABAC>, <&cru SRST_RKVDEC_CORE>;
889
-		reset-names = "video_a", "video_h", "niu_a", "niu_h",
890
-			"video_cabac", "video_core";
891
-		iommus = <&rkvdec_mmu>;
892
-		power-domains = <&power RK3228_PD_RKVDEC>;
893
-		rockchip,srv = <&mpp_srv>;
894
-		rockchip,taskqueue-node = <1>;
895
-		rockchip,resetgroup-node = <1>;
896
-		operating-points-v2 = <&rkvdec_opp_table>;
897
-		#cooling-cells = <2>;
898
-		status = "disabled";
899
-
900
-		vcodec_power_model: vcodec_power_model {
901
-			compatible = "vcodec_power_model";
902
-			dynamic-power-coefficient = <120>;
903
-			static-power-coefficient = <200>;
904
-			ts = <32000 4700 (-80) 2>;
905
-			thermal-zone = "soc-thermal";
906
-		};
907
-	};
908
-
909
-	rkvdec_opp_table: rkvdec-opp-table {
910
-		compatible = "operating-points-v2";
911
-
912
-		rockchip,leakage-voltage-sel = <
913
-			1   5    0
914
-			6   254  1
915
-		>;
916
-		nvmem-cells = <&logic_leakage>;
917
-		nvmem-cell-names = "rkvdec_leakage";
918
-
919
-		opp-100000000 {
920
-			opp-hz = /bits/ 64 <100000000>;
921
-			opp-microvolt = <1050000>;
922
-			opp-microvolt-L0 = <1050000>;
923
-			opp-microvolt-L1 = <1000000>;
924
-		};
925
-		opp-200000000 {
926
-			opp-hz = /bits/ 64 <200000000>;
927
-			opp-microvolt = <1050000>;
928
-			opp-microvolt-L0 = <1050000>;
929
-			opp-microvolt-L1 = <1000000>;
930
-		};
931
-		opp-500000000 {
932
-			opp-hz = /bits/ 64 <500000000>;
933
-			opp-microvolt = <1050000>;
934
-			opp-microvolt-L0 = <1050000>;
935
-			opp-microvolt-L1 = <1000000>;
936
-		};
937
-	};
938
-
939
-	rkvdec_mmu: iommu@20030480 {
584
+	vdec_mmu: iommu@20030480 {
940585 		compatible = "rockchip,iommu";
941586 		reg = <0x20030480 0x40>, <0x200304c0 0x40>;
942587 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
943
-		interrupt-names = "rkvdec_mmu";
944588 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
945589 		clock-names = "aclk", "iface";
946
-		power-domains = <&power RK3228_PD_RKVDEC>;
947590 		#iommu-cells = <0>;
948591 		status = "disabled";
949592 	};
950593 
951594 	vop: vop@20050000 {
952
-		compatible = "rockchip,rk3228-vop", "rockchip,rk322x-vop";
595
+		compatible = "rockchip,rk3228-vop";
953596 		reg = <0x20050000 0x1ffc>;
954
-		reg-names = "regs";
955597 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
956598 		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
957599 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
....@@ -968,74 +610,48 @@
968610 				reg = <0>;
969611 				remote-endpoint = <&hdmi_in_vop>;
970612 			};
971
-
972
-			vop_out_tve: endpoint@1 {
973
-				reg = <1>;
974
-				remote-endpoint = <&tve_in_vop>;
975
-			};
976613 		};
977614 	};
978615 
979
-	vop_mmu: iommu@20050300 {
616
+	vop_mmu: iommu@20053f00 {
980617 		compatible = "rockchip,iommu";
981618 		reg = <0x20053f00 0x100>;
982619 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
983
-		interrupt-names = "vop_mmu";
984620 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
985621 		clock-names = "aclk", "iface";
986622 		#iommu-cells = <0>;
987
-		rockchip,disable-device-link-resume;
988623 		status = "disabled";
989624 	};
990625 
991
-	rk_rga: rk_rga@20060000 {
992
-		compatible = "rockchip,rga2";
626
+	rga: rga@20060000 {
627
+		compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
993628 		reg = <0x20060000 0x1000>;
994629 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
995630 		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
996
-		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
997
-		status = "disabled";
998
-	};
999
-
1000
-	iep: iep@20070000 {
1001
-		compatible = "rockchip,iep";
1002
-		iommu_enabled = <1>;
1003
-		iommus = <&iep_mmu>;
1004
-		reg = <0x20070000 0x800>;
1005
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1006
-		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1007
-		clock-names = "aclk_iep", "hclk_iep";
1008
-		version = <3>;
1009
-		allocator = <1>;
1010
-		status = "disabled";
631
+		clock-names = "aclk", "hclk", "sclk";
632
+		resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
633
+		reset-names = "core", "axi", "ahb";
1011634 	};
1012635 
1013636 	iep_mmu: iommu@20070800 {
1014637 		compatible = "rockchip,iommu";
1015
-		reg = <0x20070800 0x40>;
638
+		reg = <0x20070800 0x100>;
1016639 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1017
-		interrupt-names = "iep_mmu";
1018640 		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1019641 		clock-names = "aclk", "iface";
1020642 		#iommu-cells = <0>;
1021643 		status = "disabled";
1022
-	};
1023
-
1024
-	display_subsystem: display-subsystem {
1025
-		compatible = "rockchip,display-subsystem";
1026
-		ports = <&vop_out>;
1027644 	};
1028645 
1029646 	hdmi: hdmi@200a0000 {
1030647 		compatible = "rockchip,rk3228-dw-hdmi";
1031648 		reg = <0x200a0000 0x20000>;
1032649 		reg-io-width = <4>;
1033
-		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1034
-			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1035
-		interrupt-names = "hdmi", "hdmi_wakeup";
1036
-		clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>,
1037
-			 <&cru SCLK_HDMI_CEC>;
1038
-		clock-names = "isfr", "iahb", "cec";
650
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
651
+		assigned-clocks = <&cru SCLK_HDMI_PHY>;
652
+		assigned-clock-parents = <&hdmi_phy>;
653
+		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
654
+		clock-names = "iahb", "isfr", "cec";
1039655 		pinctrl-names = "default";
1040656 		pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
1041657 		resets = <&cru SRST_HDMI_P>;
....@@ -1043,7 +659,6 @@
1043659 		phys = <&hdmi_phy>;
1044660 		phy-names = "hdmi";
1045661 		rockchip,grf = <&grf>;
1046
-		max-tmdsclk = <371250>;
1047662 		status = "disabled";
1048663 
1049664 		ports {
....@@ -1058,35 +673,7 @@
1058673 		};
1059674 	};
1060675 
1061
-	tve: tve@20053e00 {
1062
-		compatible = "rockchip,rk3328-tve";
1063
-		reg = <0x20053e00 0x100>,
1064
-		      <0x12020000 0x10000>;
1065
-		rockchip,saturation = <0x00305b46>;
1066
-		rockchip,brightcontrast = <0x00009900>;
1067
-		rockchip,adjtiming = <0xd6c00880>;
1068
-		rockchip,lumafilter0 = <0x02ff0001>;
1069
-		rockchip,lumafilter1 = <0xf40200fe>;
1070
-		rockchip,lumafilter2 = <0xf332d910>;
1071
-		rockchip,daclevel = <0x15>;
1072
-		rockchip,dac1level = <0x7>;
1073
-		nvmem-cells = <&tve_dac>;
1074
-		nvmem-cell-names = "tve_dac_adj";
1075
-		status = "disabled";
1076
-
1077
-		ports {
1078
-			tve_in: port {
1079
-				#address-cells = <1>;
1080
-				#size-cells = <0>;
1081
-				tve_in_vop: endpoint@0 {
1082
-					reg = <0>;
1083
-					remote-endpoint = <&vop_out_tve>;
1084
-				};
1085
-			};
1086
-		};
1087
-	};
1088
-
1089
-	sdmmc: dwmmc@30000000 {
676
+	sdmmc: mmc@30000000 {
1090677 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1091678 		reg = <0x30000000 0x4000>;
1092679 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1096,11 +683,10 @@
1096683 		fifo-depth = <0x100>;
1097684 		pinctrl-names = "default";
1098685 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
1099
-		cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
1100686 		status = "disabled";
1101687 	};
1102688 
1103
-	sdio: dwmmc@30010000 {
689
+	sdio: mmc@30010000 {
1104690 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1105691 		reg = <0x30010000 0x4000>;
1106692 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1113,7 +699,7 @@
1113699 		status = "disabled";
1114700 	};
1115701 
1116
-	emmc: dwmmc@30020000 {
702
+	emmc: mmc@30020000 {
1117703 		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
1118704 		reg = <0x30020000 0x4000>;
1119705 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1123,22 +709,12 @@
1123709 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1124710 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1125711 		bus-width = <8>;
1126
-		default-sample-phase = <158>;
712
+		rockchip,default-sample-phase = <158>;
1127713 		fifo-depth = <0x100>;
1128714 		pinctrl-names = "default";
1129715 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1130716 		resets = <&cru SRST_EMMC>;
1131717 		reset-names = "reset";
1132
-		status = "disabled";
1133
-	};
1134
-
1135
-	nandc: nandc@30030000 {
1136
-		compatible = "rockchip,rk-nandc";
1137
-		reg = <0x30030000 0x4000>;
1138
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1139
-		nandc_id = <0>;
1140
-		clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
1141
-		clock-names = "clk_nandc", "hclk_nandc";
1142718 		status = "disabled";
1143719 	};
1144720 
....@@ -1153,7 +729,6 @@
1153729 		g-np-tx-fifo-size = <16>;
1154730 		g-rx-fifo-size = <280>;
1155731 		g-tx-fifo-size = <256 128 128 64 32 16>;
1156
-		g-use-dma;
1157732 		phys = <&u2phy0_otg>;
1158733 		phy-names = "usb2-phy";
1159734 		status = "disabled";
....@@ -1164,7 +739,6 @@
1164739 		reg = <0x30080000 0x20000>;
1165740 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1166741 		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
1167
-		clock-names = "usbhost", "utmi";
1168742 		phys = <&u2phy0_host>;
1169743 		phy-names = "usb";
1170744 		status = "disabled";
....@@ -1175,7 +749,6 @@
1175749 		reg = <0x300a0000 0x20000>;
1176750 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1177751 		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
1178
-		clock-names = "usbhost", "utmi";
1179752 		phys = <&u2phy0_host>;
1180753 		phy-names = "usb";
1181754 		status = "disabled";
....@@ -1186,7 +759,6 @@
1186759 		reg = <0x300c0000 0x20000>;
1187760 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1188761 		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
1189
-		clock-names = "usbhost", "utmi";
1190762 		phys = <&u2phy1_otg>;
1191763 		phy-names = "usb";
1192764 		status = "disabled";
....@@ -1197,7 +769,6 @@
1197769 		reg = <0x300e0000 0x20000>;
1198770 		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1199771 		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
1200
-		clock-names = "usbhost", "utmi";
1201772 		phys = <&u2phy1_otg>;
1202773 		phy-names = "usb";
1203774 		status = "disabled";
....@@ -1210,7 +781,6 @@
1210781 		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
1211782 		phys = <&u2phy1_host>;
1212783 		phy-names = "usb";
1213
-		clock-names = "usbhost", "utmi";
1214784 		status = "disabled";
1215785 	};
1216786 
....@@ -1219,7 +789,6 @@
1219789 		reg = <0x30120000 0x20000>;
1220790 		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1221791 		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
1222
-		clock-names = "usbhost", "utmi";
1223792 		phys = <&u2phy1_host>;
1224793 		phy-names = "usb";
1225794 		status = "disabled";
....@@ -1233,30 +802,15 @@
1233802 		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
1234803 			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
1235804 			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
1236
-			<&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
805
+			<&cru PCLK_GMAC>;
1237806 		clock-names = "stmmaceth", "mac_clk_rx",
1238807 			"mac_clk_tx", "clk_mac_ref",
1239808 			"clk_mac_refout", "aclk_mac",
1240
-			"pclk_mac", "clk_macphy";
1241
-		resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
1242
-		reset-names = "stmmaceth", "mac-phy";
809
+			"pclk_mac";
810
+		resets = <&cru SRST_GMAC>;
811
+		reset-names = "stmmaceth";
1243812 		rockchip,grf = <&grf>;
1244813 		status = "disabled";
1245
-	};
1246
-
1247
-	qos_vpu: qos@31040000 {
1248
-		compatible = "syscon";
1249
-		reg = <0x31040000 0x20>;
1250
-	};
1251
-
1252
-	qos_rkvdec_r: qos@31070000 {
1253
-		compatible = "syscon";
1254
-		reg = <0x31070000 0x20>;
1255
-	};
1256
-
1257
-	qos_rkvdec_w: qos@31070080 {
1258
-		compatible = "syscon";
1259
-		reg = <0x31070080 0x20>;
1260814 	};
1261815 
1262816 	gic: interrupt-controller@32010000 {
....@@ -1272,10 +826,6 @@
1272826 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1273827 	};
1274828 
1275
-	rockchip_system_monitor: rockchip-system-monitor {
1276
-		compatible = "rockchip,system-monitor";
1277
-	};
1278
-
1279829 	pinctrl: pinctrl {
1280830 		compatible = "rockchip,rk3228-pinctrl";
1281831 		rockchip,grf = <&grf>;
....@@ -1287,6 +837,7 @@
1287837 			compatible = "rockchip,gpio-bank";
1288838 			reg = <0x11110000 0x100>;
1289839 			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
840
+			clock-names = "bus";
1290841 			clocks = <&cru PCLK_GPIO0>;
1291842 
1292843 			gpio-controller;
....@@ -1300,6 +851,7 @@
1300851 			compatible = "rockchip,gpio-bank";
1301852 			reg = <0x11120000 0x100>;
1302853 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
854
+			clock-names = "bus";
1303855 			clocks = <&cru PCLK_GPIO1>;
1304856 
1305857 			gpio-controller;
....@@ -1313,6 +865,7 @@
1313865 			compatible = "rockchip,gpio-bank";
1314866 			reg = <0x11130000 0x100>;
1315867 			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
868
+			clock-names = "bus";
1316869 			clocks = <&cru PCLK_GPIO2>;
1317870 
1318871 			gpio-controller;
....@@ -1326,6 +879,7 @@
1326879 			compatible = "rockchip,gpio-bank";
1327880 			reg = <0x11140000 0x100>;
1328881 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
882
+			clock-names = "bus";
1329883 			clocks = <&cru PCLK_GPIO3>;
1330884 
1331885 			gpio-controller;
....@@ -1487,45 +1041,6 @@
14871041 			};
14881042 		};
14891043 
1490
-		tsp {
1491
-			tsp_d0: tsp-d0 {
1492
-				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1493
-			};
1494
-			tsp_d1: tsp-d1 {
1495
-				rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1496
-			};
1497
-			tsp_d2: tsp-d2 {
1498
-				rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1499
-			};
1500
-			tsp_d3: tsp-d3 {
1501
-				rockchip,pins = <2 RK_PC0 2 &pcfg_pull_none>;
1502
-			};
1503
-			tsp_d4: tsp-d4 {
1504
-				rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1505
-			};
1506
-			tsp_d5: tsp-d5 {
1507
-				rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1508
-			};
1509
-			tsp_d6: tsp-d6 {
1510
-				rockchip,pins = <2 RK_PB7 2 &pcfg_pull_none>;
1511
-			};
1512
-			tsp_d7: tsp-d7 {
1513
-				rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1514
-			};
1515
-			tsp_sync: tsp-sync {
1516
-				rockchip,pins = <2 RK_PB4 2 &pcfg_pull_none>;
1517
-			};
1518
-			tsp_clk: tsp-clk {
1519
-				rockchip,pins = <2 RK_PB3 2 &pcfg_pull_none>;
1520
-			};
1521
-			tsp_fail: tsp-fail {
1522
-				rockchip,pins = <2 RK_PB2 2 &pcfg_pull_none>;
1523
-			};
1524
-			tsp_valid: tsp-valid {
1525
-				rockchip,pins = <2 RK_PB1 2 &pcfg_pull_none>;
1526
-			};
1527
-		};
1528
-
15291044 		spi0 {
15301045 			spi0_clk: spi0-clk {
15311046 				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
....@@ -1601,8 +1116,8 @@
16011116 				rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
16021117 			};
16031118 
1604
-			pwm2_pin_pull_up: pwm2-pin-pull-up {
1605
-				rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>;
1119
+			pwm2_pin_pull_down: pwm2-pin-pull-down {
1120
+				rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>;
16061121 			};
16071122 		};
16081123 
....@@ -1611,8 +1126,8 @@
16111126 				rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
16121127 			};
16131128 
1614
-			pwm3_pin_pull_up: pwm3-pin-pull-up {
1615
-				rockchip,pins = <1 RK_PB3 2 &pcfg_pull_up>;
1129
+			pwm3_pin_pull_down: pwm3-pin-pull-down {
1130
+				rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>;
16161131 			};
16171132 		};
16181133 
....@@ -1623,7 +1138,7 @@
16231138 		};
16241139 
16251140 		tsadc {
1626
-			otp_gpio: otp-gpio {
1141
+			otp_pin: otp-pin {
16271142 				rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
16281143 			};
16291144 
....@@ -1634,8 +1149,8 @@
16341149 
16351150 		uart0 {
16361151 			uart0_xfer: uart0-xfer {
1637
-				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
1638
-						<2 RK_PD3 1 &pcfg_pull_up>;
1152
+				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1153
+						<2 RK_PD3 1 &pcfg_pull_none>;
16391154 			};
16401155 
16411156 			uart0_cts: uart0-cts {
....@@ -1649,8 +1164,8 @@
16491164 
16501165 		uart1 {
16511166 			uart1_xfer: uart1-xfer {
1652
-				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1653
-						<1 RK_PB2 1 &pcfg_pull_up>;
1167
+				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1168
+						<1 RK_PB2 1 &pcfg_pull_none>;
16541169 			};
16551170 
16561171 			uart1_cts: uart1-cts {
....@@ -1662,34 +1177,15 @@
16621177 			};
16631178 		};
16641179 
1665
-		uart1-1 {
1666
-			uart11_xfer: uart11-xfer {
1667
-				rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
1668
-						<3 RK_PB5 1 &pcfg_pull_up>;
1669
-			};
1670
-
1671
-			uart11_cts: uart11-cts {
1672
-				rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
1673
-			};
1674
-
1675
-			uart11_rts: uart11-rts {
1676
-				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
1677
-			};
1678
-
1679
-			uart11_rts_gpio: uart11-rts-gpio {
1680
-				rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1681
-			};
1682
-		};
1683
-
16841180 		uart2 {
16851181 			uart2_xfer: uart2-xfer {
16861182 				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1687
-						<1 RK_PC3 2 &pcfg_pull_up>;
1183
+						<1 RK_PC3 2 &pcfg_pull_none>;
16881184 			};
16891185 
16901186 			uart21_xfer: uart21-xfer {
16911187 				rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1692
-						<1 RK_PB1 2 &pcfg_pull_up>;
1188
+						<1 RK_PB1 2 &pcfg_pull_none>;
16931189 			};
16941190 
16951191 			uart2_cts: uart2-cts {
....@@ -1700,17 +1196,5 @@
17001196 				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
17011197 			};
17021198 		};
1703
-	};
1704
-
1705
-	rockchip_suspend: rockchip-suspend {
1706
-		compatible = "rockchip,pm-rk322x";
1707
-		status = "disabled";
1708
-		rockchip,virtual-poweroff = <0>;
1709
-		rockchip,sleep-mode-config = <
1710
-			(0
1711
-			|RKPM_CTR_GTCLKS
1712
-			|RKPM_CTR_IDLESRAM_MD
1713
-			)
1714
-		>;
17151199 	};
17161200 };