.. | .. |
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36 | 36 | spi1 = &ecspi2; |
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37 | 37 | spi3 = &ecspi3; |
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38 | 38 | spi4 = &ecspi4; |
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| 39 | + usb0 = &usbotg1; |
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| 40 | + usb1 = &usbotg2; |
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39 | 41 | usbphy0 = &usbphy1; |
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40 | 42 | usbphy1 = &usbphy2; |
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41 | 43 | }; |
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.. | .. |
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49 | 51 | device_type = "cpu"; |
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50 | 52 | reg = <0>; |
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51 | 53 | next-level-cache = <&L2>; |
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52 | | - operating-points = < |
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| 54 | + operating-points = |
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53 | 55 | /* kHz uV */ |
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54 | | - 996000 1275000 |
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55 | | - 792000 1175000 |
---|
56 | | - 396000 1075000 |
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57 | | - 198000 975000 |
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58 | | - >; |
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59 | | - fsl,soc-operating-points = < |
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| 56 | + <996000 1275000>, |
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| 57 | + <792000 1175000>, |
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| 58 | + <396000 1075000>, |
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| 59 | + <198000 975000>; |
---|
| 60 | + fsl,soc-operating-points = |
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60 | 61 | /* ARM kHz SOC-PU uV */ |
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61 | | - 996000 1175000 |
---|
62 | | - 792000 1175000 |
---|
63 | | - 396000 1175000 |
---|
64 | | - 198000 1175000 |
---|
65 | | - >; |
---|
| 62 | + <996000 1175000>, |
---|
| 63 | + <792000 1175000>, |
---|
| 64 | + <396000 1175000>, |
---|
| 65 | + <198000 1175000>; |
---|
66 | 66 | clock-latency = <61036>; /* two CLK32 periods */ |
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67 | 67 | #cooling-cells = <2>; |
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68 | 68 | clocks = <&clks IMX6SLL_CLK_ARM>, |
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.. | .. |
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552 | 552 | reg = <0x020ca000 0x1000>; |
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553 | 553 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
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554 | 554 | clocks = <&clks IMX6SLL_CLK_USBPHY2>; |
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555 | | - phy-reg_3p0-supply = <®_3p0>; |
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| 555 | + phy-3p0-supply = <®_3p0>; |
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556 | 556 | fsl,anatop = <&anatop>; |
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557 | 557 | }; |
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558 | 558 | |
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