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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/arch/arm/boot/dts/dra7xx-clocks.dtsi
....@@ -1,35 +1,32 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Device Tree Source for DRA7xx clock data
34  *
45  * Copyright (C) 2013 Texas Instruments, Inc.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 &cm_core_aon_clocks {
118 	atl_clkin0_ck: atl_clkin0_ck {
129 		#clock-cells = <0>;
1310 		compatible = "ti,dra7-atl-clock";
14
-		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
11
+		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
1512 	};
1613 
1714 	atl_clkin1_ck: atl_clkin1_ck {
1815 		#clock-cells = <0>;
1916 		compatible = "ti,dra7-atl-clock";
20
-		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
17
+		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2118 	};
2219 
2320 	atl_clkin2_ck: atl_clkin2_ck {
2421 		#clock-cells = <0>;
2522 		compatible = "ti,dra7-atl-clock";
26
-		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
23
+		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2724 	};
2825 
2926 	atl_clkin3_ck: atl_clkin3_ck {
3027 		#clock-cells = <0>;
3128 		compatible = "ti,dra7-atl-clock";
32
-		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
29
+		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
3330 	};
3431 
3532 	hdmi_clkin_ck: hdmi_clkin_ck {
....@@ -799,16 +796,6 @@
799796 		clock-div = <1>;
800797 	};
801798 
802
-	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
803
-		#clock-cells = <0>;
804
-		compatible = "ti,mux-clock";
805
-		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
806
-		ti,bit-shift = <24>;
807
-		reg = <0x0520>;
808
-		assigned-clocks = <&ipu1_gfclk_mux>;
809
-		assigned-clock-parents = <&dpll_core_h22x2_ck>;
810
-	};
811
-
812799 	dummy_ck: dummy_ck {
813800 		#clock-cells = <0>;
814801 		compatible = "fixed-clock";
....@@ -1526,44 +1513,98 @@
15261513 };
15271514 
15281515 &cm_core_aon {
1529
-	mpu_cm: mpu_cm@300 {
1516
+	mpu_cm: mpu-cm@300 {
15301517 		compatible = "ti,omap4-cm";
15311518 		reg = <0x300 0x100>;
15321519 		#address-cells = <1>;
15331520 		#size-cells = <1>;
15341521 		ranges = <0 0x300 0x100>;
15351522 
1536
-		mpu_clkctrl: clk@20 {
1523
+		mpu_clkctrl: mpu-clkctrl@20 {
15371524 			compatible = "ti,clkctrl";
15381525 			reg = <0x20 0x4>;
15391526 			#clock-cells = <2>;
15401527 		};
1528
+
15411529 	};
15421530 
1543
-	ipu_cm: ipu_cm@500 {
1531
+	dsp1_cm: dsp1-cm@400 {
1532
+		compatible = "ti,omap4-cm";
1533
+		reg = <0x400 0x100>;
1534
+		#address-cells = <1>;
1535
+		#size-cells = <1>;
1536
+		ranges = <0 0x400 0x100>;
1537
+
1538
+		dsp1_clkctrl: dsp1-clkctrl@20 {
1539
+			compatible = "ti,clkctrl";
1540
+			reg = <0x20 0x4>;
1541
+			#clock-cells = <2>;
1542
+		};
1543
+
1544
+	};
1545
+
1546
+	ipu_cm: ipu-cm@500 {
15441547 		compatible = "ti,omap4-cm";
15451548 		reg = <0x500 0x100>;
15461549 		#address-cells = <1>;
15471550 		#size-cells = <1>;
15481551 		ranges = <0 0x500 0x100>;
15491552 
1550
-		ipu_clkctrl: clk@40 {
1553
+		ipu1_clkctrl: ipu1-clkctrl@20 {
15511554 			compatible = "ti,clkctrl";
1552
-			reg = <0x40 0x44>;
1555
+			reg = <0x20 0x4>;
1556
+			#clock-cells = <2>;
1557
+			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
1558
+			assigned-clock-parents = <&dpll_core_h22x2_ck>;
1559
+		};
1560
+
1561
+		ipu_clkctrl: ipu-clkctrl@50 {
1562
+			compatible = "ti,clkctrl";
1563
+			reg = <0x50 0x34>;
1564
+			#clock-cells = <2>;
1565
+		};
1566
+
1567
+	};
1568
+
1569
+	dsp2_cm: dsp2-cm@600 {
1570
+		compatible = "ti,omap4-cm";
1571
+		reg = <0x600 0x100>;
1572
+		#address-cells = <1>;
1573
+		#size-cells = <1>;
1574
+		ranges = <0 0x600 0x100>;
1575
+
1576
+		dsp2_clkctrl: dsp2-clkctrl@20 {
1577
+			compatible = "ti,clkctrl";
1578
+			reg = <0x20 0x4>;
1579
+			#clock-cells = <2>;
1580
+		};
1581
+
1582
+	};
1583
+
1584
+	rtc_cm: rtc-cm@700 {
1585
+		compatible = "ti,omap4-cm";
1586
+		reg = <0x700 0x60>;
1587
+		#address-cells = <1>;
1588
+		#size-cells = <1>;
1589
+		ranges = <0 0x700 0x60>;
1590
+
1591
+		rtc_clkctrl: rtc-clkctrl@20 {
1592
+			compatible = "ti,clkctrl";
1593
+			reg = <0x20 0x28>;
15531594 			#clock-cells = <2>;
15541595 		};
15551596 	};
15561597 
1557
-	rtc_cm: rtc_cm@700 {
1598
+	vpe_cm: vpe-cm@760 {
15581599 		compatible = "ti,omap4-cm";
1559
-		reg = <0x700 0x100>;
1600
+		reg = <0x760 0xc>;
15601601 		#address-cells = <1>;
15611602 		#size-cells = <1>;
1562
-		ranges = <0 0x700 0x100>;
1603
+		ranges = <0 0x760 0xc>;
15631604 
1564
-		rtc_clkctrl: clk@40 {
1605
+		vpe_clkctrl: vpe-clkctrl@0 {
15651606 			compatible = "ti,clkctrl";
1566
-			reg = <0x40 0x8>;
1607
+			reg = <0x0 0xc>;
15671608 			#clock-cells = <2>;
15681609 		};
15691610 	};
....@@ -1571,160 +1612,235 @@
15711612 };
15721613 
15731614 &cm_core {
1574
-	coreaon_cm: coreaon_cm@600 {
1615
+	coreaon_cm: coreaon-cm@600 {
15751616 		compatible = "ti,omap4-cm";
15761617 		reg = <0x600 0x100>;
15771618 		#address-cells = <1>;
15781619 		#size-cells = <1>;
15791620 		ranges = <0 0x600 0x100>;
15801621 
1581
-		coreaon_clkctrl: clk@20 {
1622
+		coreaon_clkctrl: coreaon-clkctrl@20 {
15821623 			compatible = "ti,clkctrl";
15831624 			reg = <0x20 0x1c>;
15841625 			#clock-cells = <2>;
15851626 		};
15861627 	};
15871628 
1588
-	l3main1_cm: l3main1_cm@700 {
1629
+	l3main1_cm: l3main1-cm@700 {
15891630 		compatible = "ti,omap4-cm";
15901631 		reg = <0x700 0x100>;
15911632 		#address-cells = <1>;
15921633 		#size-cells = <1>;
15931634 		ranges = <0 0x700 0x100>;
15941635 
1595
-		l3main1_clkctrl: clk@20 {
1636
+		l3main1_clkctrl: l3main1-clkctrl@20 {
15961637 			compatible = "ti,clkctrl";
15971638 			reg = <0x20 0x74>;
15981639 			#clock-cells = <2>;
15991640 		};
1641
+
16001642 	};
16011643 
1602
-	dma_cm: dma_cm@a00 {
1644
+	ipu2_cm: ipu2-cm@900 {
1645
+		compatible = "ti,omap4-cm";
1646
+		reg = <0x900 0x100>;
1647
+		#address-cells = <1>;
1648
+		#size-cells = <1>;
1649
+		ranges = <0 0x900 0x100>;
1650
+
1651
+		ipu2_clkctrl: ipu2-clkctrl@20 {
1652
+			compatible = "ti,clkctrl";
1653
+			reg = <0x20 0x4>;
1654
+			#clock-cells = <2>;
1655
+		};
1656
+
1657
+	};
1658
+
1659
+	dma_cm: dma-cm@a00 {
16031660 		compatible = "ti,omap4-cm";
16041661 		reg = <0xa00 0x100>;
16051662 		#address-cells = <1>;
16061663 		#size-cells = <1>;
16071664 		ranges = <0 0xa00 0x100>;
16081665 
1609
-		dma_clkctrl: clk@20 {
1666
+		dma_clkctrl: dma-clkctrl@20 {
16101667 			compatible = "ti,clkctrl";
16111668 			reg = <0x20 0x4>;
16121669 			#clock-cells = <2>;
16131670 		};
16141671 	};
16151672 
1616
-	emif_cm: emif_cm@b00 {
1673
+	emif_cm: emif-cm@b00 {
16171674 		compatible = "ti,omap4-cm";
16181675 		reg = <0xb00 0x100>;
16191676 		#address-cells = <1>;
16201677 		#size-cells = <1>;
16211678 		ranges = <0 0xb00 0x100>;
16221679 
1623
-		emif_clkctrl: clk@20 {
1680
+		emif_clkctrl: emif-clkctrl@20 {
16241681 			compatible = "ti,clkctrl";
16251682 			reg = <0x20 0x4>;
16261683 			#clock-cells = <2>;
16271684 		};
16281685 	};
16291686 
1630
-	atl_cm: atl_cm@c00 {
1687
+	atl_cm: atl-cm@c00 {
16311688 		compatible = "ti,omap4-cm";
16321689 		reg = <0xc00 0x100>;
16331690 		#address-cells = <1>;
16341691 		#size-cells = <1>;
16351692 		ranges = <0 0xc00 0x100>;
16361693 
1637
-		atl_clkctrl: clk@0 {
1694
+		atl_clkctrl: atl-clkctrl@0 {
16381695 			compatible = "ti,clkctrl";
16391696 			reg = <0x0 0x4>;
16401697 			#clock-cells = <2>;
16411698 		};
16421699 	};
16431700 
1644
-	l4cfg_cm: l4cfg_cm@d00 {
1701
+	l4cfg_cm: l4cfg-cm@d00 {
16451702 		compatible = "ti,omap4-cm";
16461703 		reg = <0xd00 0x100>;
16471704 		#address-cells = <1>;
16481705 		#size-cells = <1>;
16491706 		ranges = <0 0xd00 0x100>;
16501707 
1651
-		l4cfg_clkctrl: clk@20 {
1708
+		l4cfg_clkctrl: l4cfg-clkctrl@20 {
16521709 			compatible = "ti,clkctrl";
16531710 			reg = <0x20 0x84>;
16541711 			#clock-cells = <2>;
16551712 		};
16561713 	};
16571714 
1658
-	l3instr_cm: l3instr_cm@e00 {
1715
+	l3instr_cm: l3instr-cm@e00 {
16591716 		compatible = "ti,omap4-cm";
16601717 		reg = <0xe00 0x100>;
16611718 		#address-cells = <1>;
16621719 		#size-cells = <1>;
16631720 		ranges = <0 0xe00 0x100>;
16641721 
1665
-		l3instr_clkctrl: clk@20 {
1722
+		l3instr_clkctrl: l3instr-clkctrl@20 {
16661723 			compatible = "ti,clkctrl";
16671724 			reg = <0x20 0xc>;
16681725 			#clock-cells = <2>;
16691726 		};
16701727 	};
16711728 
1672
-	dss_cm: dss_cm@1100 {
1729
+	cam_cm: cam-cm@1000 {
1730
+		compatible = "ti,omap4-cm";
1731
+		reg = <0x1000 0x100>;
1732
+		#address-cells = <1>;
1733
+		#size-cells = <1>;
1734
+		ranges = <0 0x1000 0x100>;
1735
+
1736
+		cam_clkctrl: cam-clkctrl@20 {
1737
+			compatible = "ti,clkctrl";
1738
+			reg = <0x20 0x2c>;
1739
+			#clock-cells = <2>;
1740
+		};
1741
+	};
1742
+
1743
+	dss_cm: dss-cm@1100 {
16731744 		compatible = "ti,omap4-cm";
16741745 		reg = <0x1100 0x100>;
16751746 		#address-cells = <1>;
16761747 		#size-cells = <1>;
16771748 		ranges = <0 0x1100 0x100>;
16781749 
1679
-		dss_clkctrl: clk@20 {
1750
+		dss_clkctrl: dss-clkctrl@20 {
16801751 			compatible = "ti,clkctrl";
16811752 			reg = <0x20 0x14>;
16821753 			#clock-cells = <2>;
16831754 		};
16841755 	};
16851756 
1686
-	l3init_cm: l3init_cm@1300 {
1757
+	gpu_cm: gpu-cm@1200 {
1758
+		compatible = "ti,omap4-cm";
1759
+		reg = <0x1200 0x100>;
1760
+		#address-cells = <1>;
1761
+		#size-cells = <1>;
1762
+		ranges = <0 0x1200 0x100>;
1763
+
1764
+		gpu_clkctrl: gpu-clkctrl@20 {
1765
+			compatible = "ti,clkctrl";
1766
+			reg = <0x20 0x4>;
1767
+			#clock-cells = <2>;
1768
+		};
1769
+	};
1770
+
1771
+	l3init_cm: l3init-cm@1300 {
16871772 		compatible = "ti,omap4-cm";
16881773 		reg = <0x1300 0x100>;
16891774 		#address-cells = <1>;
16901775 		#size-cells = <1>;
16911776 		ranges = <0 0x1300 0x100>;
16921777 
1693
-		l3init_clkctrl: clk@20 {
1778
+		l3init_clkctrl: l3init-clkctrl@20 {
16941779 			compatible = "ti,clkctrl";
1695
-			reg = <0x20 0xd4>;
1780
+			reg = <0x20 0x6c>, <0xe0 0x14>;
16961781 			#clock-cells = <2>;
16971782 		};
1783
+
1784
+		pcie_clkctrl: pcie-clkctrl@b0 {
1785
+			compatible = "ti,clkctrl";
1786
+			reg = <0xb0 0xc>;
1787
+			#clock-cells = <2>;
1788
+		};
1789
+
1790
+		gmac_clkctrl: gmac-clkctrl@d0 {
1791
+			compatible = "ti,clkctrl";
1792
+			reg = <0xd0 0x4>;
1793
+			#clock-cells = <2>;
1794
+		};
1795
+
16981796 	};
16991797 
1700
-	l4per_cm: l4per_cm@1700 {
1798
+	l4per_cm: l4per-cm@1700 {
17011799 		compatible = "ti,omap4-cm";
17021800 		reg = <0x1700 0x300>;
17031801 		#address-cells = <1>;
17041802 		#size-cells = <1>;
17051803 		ranges = <0 0x1700 0x300>;
17061804 
1707
-		l4per_clkctrl: clk@0 {
1805
+		l4per_clkctrl: l4per-clkctrl@28 {
17081806 			compatible = "ti,clkctrl";
1709
-			reg = <0x0 0x20c>;
1807
+			reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
17101808 			#clock-cells = <2>;
17111809 
1712
-			assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1810
+			assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
17131811 			assigned-clock-parents = <&abe_24m_fclk>;
1812
+		};
1813
+
1814
+		l4sec_clkctrl: l4sec-clkctrl@1a0 {
1815
+			compatible = "ti,clkctrl";
1816
+			reg = <0x1a0 0x2c>;
1817
+			#clock-cells = <2>;
1818
+		};
1819
+
1820
+		l4per2_clkctrl: l4per2-clkctrl@c {
1821
+			compatible = "ti,clkctrl";
1822
+			reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
1823
+			#clock-cells = <2>;
1824
+		};
1825
+
1826
+		l4per3_clkctrl: l4per3-clkctrl@14 {
1827
+			compatible = "ti,clkctrl";
1828
+			reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1829
+			#clock-cells = <2>;
17141830 		};
17151831 	};
17161832 
17171833 };
17181834 
17191835 &prm {
1720
-	wkupaon_cm: wkupaon_cm@1800 {
1836
+	wkupaon_cm: wkupaon-cm@1800 {
17211837 		compatible = "ti,omap4-cm";
17221838 		reg = <0x1800 0x100>;
17231839 		#address-cells = <1>;
17241840 		#size-cells = <1>;
17251841 		ranges = <0 0x1800 0x100>;
17261842 
1727
-		wkupaon_clkctrl: clk@20 {
1843
+		wkupaon_clkctrl: wkupaon-clkctrl@20 {
17281844 			compatible = "ti,clkctrl";
17291845 			reg = <0x20 0x6c>;
17301846 			#clock-cells = <2>;