disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/arch/alpha/include/asm/barrier.h
..
..
@@ -2,64 +2,15 @@
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 #ifndef __BARRIER_H
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 #define __BARRIER_H
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-#include <asm/compiler.h>
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-
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 #define mb()	__asm__ __volatile__("mb": : :"memory")
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 #define rmb()	__asm__ __volatile__("mb": : :"memory")
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 #define wmb()	__asm__ __volatile__("wmb": : :"memory")
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-/**
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- * read_barrier_depends - Flush all pending reads that subsequents reads
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- * depend on.
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- *
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- * No data-dependent reads from memory-like regions are ever reordered
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- * over this barrier.  All reads preceding this primitive are guaranteed
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- * to access memory (but not necessarily other CPUs' caches) before any
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- * reads following this primitive that depend on the data return by
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- * any of the preceding reads.  This primitive is much lighter weight than
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- * rmb() on most CPUs, and is never heavier weight than is
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- * rmb().
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- *
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- * These ordering constraints are respected by both the local CPU
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- * and the compiler.
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- *
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- * Ordering is not guaranteed by anything other than these primitives,
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- * not even by data dependencies.  See the documentation for
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- * memory_barrier() for examples and URLs to more information.
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- *
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- * For example, the following code would force ordering (the initial
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- * value of "a" is zero, "b" is one, and "p" is "&a"):
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- *
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- * <programlisting>
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- *	CPU 0				CPU 1
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- *
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- *	b = 2;
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- *	memory_barrier();
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- *	p = &b;				q = p;
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- *					read_barrier_depends();
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- *					d = *q;
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- * </programlisting>
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- *
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- * because the read of "*q" depends on the read of "p" and these
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- * two reads are separated by a read_barrier_depends().  However,
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- * the following code, with the same initial values for "a" and "b":
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- *
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- * <programlisting>
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- *	CPU 0				CPU 1
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- *
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- *	a = 2;
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- *	memory_barrier();
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- *	b = 3;				y = b;
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- *					read_barrier_depends();
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- *					x = a;
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- * </programlisting>
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- *
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- * does not enforce ordering, since there is no data dependency between
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- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
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- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
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- * in cases like this where there are no data dependencies.
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- */
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-#define read_barrier_depends() __asm__ __volatile__("mb": : :"memory")
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+#define __smp_load_acquire(p)						\
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+({									\
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+	compiletime_assert_atomic_type(*p);				\
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+	__READ_ONCE(*p);						\
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+})
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 #ifdef CONFIG_SMP
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 #define __ASM_SMP_MB	"\tmb\n"