audio ok

hc

2023-12-11 223293205a7265c8b02882461ba8996650048ade

 kernel/include/linux/brcmphy.h
..
..
@@ -15,7 +15,9 @@
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 #define PHY_ID_BCMAC131			0x0143bc70
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 #define PHY_ID_BCM5481			0x0143bca0
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 #define PHY_ID_BCM5395			0x0143bcf0
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+#define PHY_ID_BCM53125			0x03625f20
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 #define PHY_ID_BCM54810			0x03625d00
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+#define PHY_ID_BCM54811			0x03625cc0
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 #define PHY_ID_BCM5482			0x0143bcb0
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 #define PHY_ID_BCM5411			0x00206070
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 #define PHY_ID_BCM5421			0x002060e0
..
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@@ -24,10 +26,13 @@
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 #define PHY_ID_BCM5461			0x002060c0
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 #define PHY_ID_BCM54612E		0x03625e60
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 #define PHY_ID_BCM54616S		0x03625d10
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+#define PHY_ID_BCM54140			0xae025009
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 #define PHY_ID_BCM57780			0x03625d90
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 #define PHY_ID_BCM89610			0x03625cd0
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+#define PHY_ID_BCM72113			0x35905310
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 #define PHY_ID_BCM7250			0xae025280
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+#define PHY_ID_BCM7255			0xae025120
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 #define PHY_ID_BCM7260			0xae025190
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 #define PHY_ID_BCM7268			0xae025090
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 #define PHY_ID_BCM7271			0xae0253b0
..
..
@@ -78,6 +83,7 @@
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 #define MII_BCM54XX_ECR		0x10	/* BCM54xx extended control register */
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 #define MII_BCM54XX_ECR_IM	0x1000	/* Interrupt mask */
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 #define MII_BCM54XX_ECR_IF	0x0800	/* Interrupt force */
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+#define MII_BCM54XX_ECR_FIFOE	0x0001	/* FIFO elasticity */
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87
 
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 #define MII_BCM54XX_ESR		0x11	/* BCM54xx extended status register */
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 #define MII_BCM54XX_ESR_IS	0x1000	/* Interrupt status */
..
..
@@ -112,15 +118,25 @@
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 #define MII_BCM54XX_SHD_VAL(x)	((x & 0x1f) << 10)
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 #define MII_BCM54XX_SHD_DATA(x)	((x & 0x3ff) << 0)
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120
 
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+#define MII_BCM54XX_RDB_ADDR	0x1e
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+#define MII_BCM54XX_RDB_DATA	0x1f
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+
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+/* legacy access control via rdb/expansion register */
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+#define BCM54XX_RDB_REG0087		0x0087
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+#define BCM54XX_EXP_REG7E		(MII_BCM54XX_EXP_SEL_ER + 0x7E)
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+#define BCM54XX_ACCESS_MODE_LEGACY_EN	BIT(15)
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+
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 /*
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  * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
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  */
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 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL	0x00
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 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB		0x0400
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 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA	0x0800
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+#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN	0x4000
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136
 
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 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC			0x07
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 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN	0x0010
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+#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN	0x0080
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 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN	0x0100
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 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX		0x0200
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 #define MII_BCM54XX_AUXCTL_MISC_WREN			0x8000
..
..
@@ -147,6 +163,22 @@
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 #define BCM_LED_SRC_OFF		0xe	/* Tied high */
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 #define BCM_LED_SRC_ON		0xf	/* Tied low */
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165
 
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+/*
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+ * Broadcom Multicolor LED configurations (expansion register 4)
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+ */
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+#define BCM_EXP_MULTICOLOR		(MII_BCM54XX_EXP_SEL_ER + 0x04)
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+#define BCM_LED_MULTICOLOR_IN_PHASE	BIT(8)
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+#define BCM_LED_MULTICOLOR_LINK_ACT	0x0
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+#define BCM_LED_MULTICOLOR_SPEED	0x1
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+#define BCM_LED_MULTICOLOR_ACT_FLASH	0x2
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+#define BCM_LED_MULTICOLOR_FDX		0x3
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+#define BCM_LED_MULTICOLOR_OFF		0x4
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+#define BCM_LED_MULTICOLOR_ON		0x5
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+#define BCM_LED_MULTICOLOR_ALT		0x6
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+#define BCM_LED_MULTICOLOR_FLASH	0x7
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+#define BCM_LED_MULTICOLOR_LINK		0x8
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+#define BCM_LED_MULTICOLOR_ACT		0x9
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+#define BCM_LED_MULTICOLOR_PROGRAM	0xa
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182
 
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 /*
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  * BCM5482: Shadow registers
..
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@@ -183,9 +215,18 @@
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 #define BCM5482_SHD_SSD		0x14	/* 10100: Secondary SerDes control */
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 #define BCM5482_SHD_SSD_LEDM	0x0008	/* SSD LED Mode enable */
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 #define BCM5482_SHD_SSD_EN	0x0001	/* SSD enable */
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-#define BCM5482_SHD_MODE	0x1f	/* 11111: Mode Control Register */
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-#define BCM5482_SHD_MODE_1000BX	0x0001	/* Enable 1000BASE-X registers */
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218
 
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+/* 10011: SerDes 100-FX Control Register */
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+#define BCM54616S_SHD_100FX_CTRL	0x13
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+#define	BCM54616S_100FX_MODE		BIT(0)	/* 100-FX SerDes Enable */
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+
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+/* 11111: Mode Control Register */
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+#define BCM54XX_SHD_MODE		0x1f
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+#define BCM54XX_SHD_INTF_SEL_MASK	GENMASK(2, 1)	/* INTERF_SEL[1:0] */
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+#define BCM54XX_SHD_INTF_SEL_RGMII	0x02
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+#define BCM54XX_SHD_INTF_SEL_SGMII	0x04
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+#define BCM54XX_SHD_INTF_SEL_GBIC	0x06
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+#define BCM54XX_SHD_MODE_1000BX		BIT(0)	/* Enable 1000-X registers */
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230
 
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 /*
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  * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
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..
@@ -220,6 +261,7 @@
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 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN	(1 << 0)
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 #define BCM54810_SHD_CLK_CTL			0x3
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 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN		(1 << 9)
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+#define BCM54810_SHD_SCR3_TRDDAPD		0x0100
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265
 
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 /* BCM54612E Registers */
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 #define BCM54612E_EXP_SPARE0		(MII_BCM54XX_EXP_SEL_ETC + 0x34)
..
..
@@ -264,4 +306,51 @@
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 #define MII_BRCM_CORE_EXPB0	0xB0
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 #define MII_BRCM_CORE_EXPB1	0xB1
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308
 
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+/* Enhanced Cable Diagnostics */
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+#define BCM54XX_RDB_ECD_CTRL			0x2a0
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+#define BCM54XX_EXP_ECD_CTRL			(MII_BCM54XX_EXP_SEL_ER + 0xc0)
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+
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+#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3	1	/* CAT3 or worse */
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+#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5	0	/* CAT5 or better */
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+#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK	BIT(0)	/* cable type */
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+#define BCM54XX_ECD_CTRL_INVALID		BIT(3)	/* invalid result */
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+#define BCM54XX_ECD_CTRL_UNIT_CM		0	/* centimeters */
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+#define BCM54XX_ECD_CTRL_UNIT_M			1	/* meters */
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+#define BCM54XX_ECD_CTRL_UNIT_MASK		BIT(10)	/* cable length unit */
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+#define BCM54XX_ECD_CTRL_IN_PROGRESS		BIT(11)	/* test in progress */
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+#define BCM54XX_ECD_CTRL_BREAK_LINK		BIT(12)	/* unconnect link
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+							 * during test
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+							 */
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+#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS	BIT(13)	/* disable inter-pair
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+							 * short check
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+							 */
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+#define BCM54XX_ECD_CTRL_RUN			BIT(15)	/* run immediate */
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+
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+#define BCM54XX_RDB_ECD_FAULT_TYPE		0x2a1
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+#define BCM54XX_EXP_ECD_FAULT_TYPE		(MII_BCM54XX_EXP_SEL_ER + 0xc1)
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+#define BCM54XX_ECD_FAULT_TYPE_INVALID		0x0
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+#define BCM54XX_ECD_FAULT_TYPE_OK		0x1
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+#define BCM54XX_ECD_FAULT_TYPE_OPEN		0x2
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+#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT	0x3 /* short same pair */
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+#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT	0x4 /* short different pairs */
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+#define BCM54XX_ECD_FAULT_TYPE_BUSY		0x9
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+#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK	GENMASK(3, 0)
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+#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK	GENMASK(7, 4)
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+#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK	GENMASK(11, 8)
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+#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK	GENMASK(15, 12)
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+#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS	0x2a2
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+#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS	0x2a3
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+#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS	0x2a4
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+#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS	0x2a5
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+
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+#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS	0x2a2
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+#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc2)
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+#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS	0x2a3
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+#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc3)
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+#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS	0x2a4
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+#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc4)
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+#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS	0x2a5
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+#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS	(MII_BCM54XX_EXP_SEL_ER + 0xc5)
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+#define BCM54XX_ECD_LENGTH_RESULTS_INVALID	0xffff
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+
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 #endif /* _LINUX_BRCMPHY_H */