~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,10 +5,14 @@
5	5	#include <linux/console.h>
6	6	#include <linux/io.h>
7	7	#include <linux/iopoll.h>
	8	+#include <linux/irq.h>
8	9	#include <linux/module.h>
9	10	#include <linux/of.h>
10	11	#include <linux/of_device.h>
	12	+#include <linux/pm_opp.h>
11	13	#include <linux/platform_device.h>
	14	+#include <linux/pm_runtime.h>
	15	+#include <linux/pm_wakeirq.h>
12	16	#include <linux/qcom-geni-se.h>
13	17	#include <linux/serial.h>
14	18	#include <linux/serial_core.h>
..	..	@@ -18,6 +22,7 @@
18	22
19	23	/* UART specific GENI registers */
20	24	#define SE_UART_LOOPBACK_CFG 0x22c
	25	+#define SE_UART_IO_MACRO_CTRL 0x240
21	26	#define SE_UART_TX_TRANS_CFG 0x25c
22	27	#define SE_UART_TX_WORD_LEN 0x268
23	28	#define SE_UART_TX_STOP_BIT_LEN 0x26c
..	..	@@ -86,31 +91,52 @@
86	91	#define DEF_TX_WM 2
87	92	#define DEF_FIFO_WIDTH_BITS 32
88	93	#define UART_RX_WM 2
89		-#define MAX_LOOPBACK_CFG 3
90	94
91		-#ifdef CONFIG_CONSOLE_POLL
92		-#define RX_BYTES_PW 1
93		-#else
94		-#define RX_BYTES_PW 4
95		-#endif
	95	+/* SE_UART_LOOPBACK_CFG */
	96	+#define RX_TX_SORTED BIT(0)
	97	+#define CTS_RTS_SORTED BIT(1)
	98	+#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED \| CTS_RTS_SORTED)
	99	+
	100	+/* UART pin swap value */
	101	+#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
	102	+#define IO_MACRO_IO0_SEL 0x3
	103	+#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
	104	+#define IO_MACRO_IO2_IO3_SWAP 0x4640
	105	+
	106	+/* We always configure 4 bytes per FIFO word */
	107	+#define BYTES_PER_FIFO_WORD 4
	108	+
	109	+struct qcom_geni_private_data {
	110	+ /* NOTE: earlycon port will have NULL here */
	111	+ struct uart_driver *drv;
	112	+
	113	+ u32 poll_cached_bytes;
	114	+ unsigned int poll_cached_bytes_cnt;
	115	+
	116	+ u32 write_cached_bytes;
	117	+ unsigned int write_cached_bytes_cnt;
	118	+};
96	119
97	120	struct qcom_geni_serial_port {
98	121	struct uart_port uport;
99	122	struct geni_se se;
100		- char name[20];
	123	+ const char *name;
101	124	u32 tx_fifo_depth;
102	125	u32 tx_fifo_width;
103	126	u32 rx_fifo_depth;
104	127	bool setup;
105	128	int (handle_rx)(struct uart_port uport, u32 bytes, bool drop);
106	129	unsigned int baud;
107		- unsigned int tx_bytes_pw;
108		- unsigned int rx_bytes_pw;
109		- u32 *rx_fifo;
	130	+ void *rx_fifo;
110	131	u32 loopback;
111	132	bool brk;
112	133
113	134	unsigned int tx_remaining;
	135	+ int wakeup_irq;
	136	+ bool rx_tx_swap;
	137	+ bool cts_rts_swap;
	138	+
	139	+ struct qcom_geni_private_data private_data;
114	140	};
115	141
116	142	static const struct uart_ops qcom_geni_console_pops;
..	..	@@ -124,9 +150,10 @@
124	150	static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
125	151
126	152	static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
127		- 32000000, 48000000, 64000000, 80000000,
128		- 96000000, 100000000, 102400000,
129		- 112000000, 120000000, 128000000};
	153	+ 32000000, 48000000, 51200000, 64000000,
	154	+ 80000000, 96000000, 100000000,
	155	+ 102400000, 112000000, 120000000,
	156	+ 128000000};
130	157
131	158	#define to_dev_port(ptr, member) \
132	159	container_of(ptr, struct qcom_geni_serial_port, member)
..	..	@@ -158,32 +185,6 @@
158	185	},
159	186	};
160	187
161		-static ssize_t loopback_show(struct device *dev,
162		- struct device_attribute attr, char buf)
163		-{
164		- struct platform_device *pdev = to_platform_device(dev);
165		- struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
166		-
167		- return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
168		-}
169		-
170		-static ssize_t loopback_store(struct device *dev,
171		- struct device_attribute attr, const char buf,
172		- size_t size)
173		-{
174		- struct platform_device *pdev = to_platform_device(dev);
175		- struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
176		- u32 loopback;
177		-
178		- if (kstrtoint(buf, 0, &loopback) \|\| loopback > MAX_LOOPBACK_CFG) {
179		- dev_err(dev, "Invalid input\n");
180		- return -EINVAL;
181		- }
182		- port->loopback = loopback;
183		- return size;
184		-}
185		-static DEVICE_ATTR_RW(loopback);
186		-
187	188	static struct qcom_geni_serial_port qcom_geni_console_port = {
188	189	.uport = {
189	190	.iotype = UPIO_MEM,
..	..	@@ -197,10 +198,8 @@
197	198	{
198	199	struct platform_device *pdev = to_platform_device(uport->dev);
199	200	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
200		- struct resource *res;
201	201
202		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
203		- uport->membase = devm_ioremap_resource(&pdev->dev, res);
	202	+ uport->membase = devm_platform_ioremap_resource(pdev, 0);
204	203	if (IS_ERR(uport->membase))
205	204	return PTR_ERR(uport->membase);
206	205	port->se.base = uport->membase;
..	..	@@ -235,11 +234,15 @@
235	234	unsigned int mctrl)
236	235	{
237	236	u32 uart_manual_rfr = 0;
	237	+ struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
238	238
239	239	if (uart_console(uport))
240	240	return;
241	241
242		- if (!(mctrl & TIOCM_RTS))
	242	+ if (mctrl & TIOCM_LOOP)
	243	+ port->loopback = RX_TX_CTS_RTS_SORTED;
	244	+
	245	+ if (!(mctrl & TIOCM_RTS) && !uport->suspended)
243	246	uart_manual_rfr = UART_MANUAL_RFR_EN \| UART_RFR_NOT_READY;
244	247	writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
245	248	}
..	..	@@ -269,8 +272,9 @@
269	272	unsigned int baud;
270	273	unsigned int fifo_bits;
271	274	unsigned long timeout_us = 20000;
	275	+ struct qcom_geni_private_data *private_data = uport->private_data;
272	276
273		- if (uport->private_data) {
	277	+ if (private_data->drv) {
274	278	port = to_dev_port(uport, uport);
275	279	baud = port->baud;
276	280	if (!baud)
..	..	@@ -336,23 +340,47 @@
336	340	}
337	341
338	342	#ifdef CONFIG_CONSOLE_POLL
	343	+
339	344	static int qcom_geni_serial_get_char(struct uart_port *uport)
340	345	{
341		- u32 rx_fifo;
	346	+ struct qcom_geni_private_data *private_data = uport->private_data;
342	347	u32 status;
	348	+ u32 word_cnt;
	349	+ int ret;
343	350
344		- status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
345		- writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
	351	+ if (!private_data->poll_cached_bytes_cnt) {
	352	+ status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
	353	+ writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
346	354
347		- status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
348		- writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
	355	+ status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
	356	+ writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
349	357
350		- status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
351		- if (!(status & RX_FIFO_WC_MSK))
352		- return NO_POLL_CHAR;
	358	+ status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
	359	+ word_cnt = status & RX_FIFO_WC_MSK;
	360	+ if (!word_cnt)
	361	+ return NO_POLL_CHAR;
353	362
354		- rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
355		- return rx_fifo & 0xff;
	363	+ if (word_cnt == 1 && (status & RX_LAST))
	364	+ /*
	365	+ * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
	366	+ * treated as if it was BYTES_PER_FIFO_WORD.
	367	+ */
	368	+ private_data->poll_cached_bytes_cnt =
	369	+ (status & RX_LAST_BYTE_VALID_MSK) >>
	370	+ RX_LAST_BYTE_VALID_SHFT;
	371	+
	372	+ if (private_data->poll_cached_bytes_cnt == 0)
	373	+ private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
	374	+
	375	+ private_data->poll_cached_bytes =
	376	+ readl(uport->membase + SE_GENI_RX_FIFOn);
	377	+ }
	378	+
	379	+ private_data->poll_cached_bytes_cnt--;
	380	+ ret = private_data->poll_cached_bytes & 0xff;
	381	+ private_data->poll_cached_bytes >>= 8;
	382	+
	383	+ return ret;
356	384	}
357	385
358	386	static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
..	..	@@ -371,13 +399,25 @@
371	399	#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
372	400	static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
373	401	{
374		- writel(ch, uport->membase + SE_GENI_TX_FIFOn);
	402	+ struct qcom_geni_private_data *private_data = uport->private_data;
	403	+
	404	+ private_data->write_cached_bytes =
	405	+ (private_data->write_cached_bytes >> 8) \| (ch << 24);
	406	+ private_data->write_cached_bytes_cnt++;
	407	+
	408	+ if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
	409	+ writel(private_data->write_cached_bytes,
	410	+ uport->membase + SE_GENI_TX_FIFOn);
	411	+ private_data->write_cached_bytes_cnt = 0;
	412	+ }
375	413	}
376	414
377	415	static void
378	416	__qcom_geni_serial_console_write(struct uart_port uport, const char s,
379	417	unsigned int count)
380	418	{
	419	+ struct qcom_geni_private_data *private_data = uport->private_data;
	420	+
381	421	int i;
382	422	u32 bytes_to_send = count;
383	423
..	..	@@ -412,6 +452,15 @@
412	452	SE_GENI_M_IRQ_CLEAR);
413	453	i += chars_to_write;
414	454	}
	455	+
	456	+ if (private_data->write_cached_bytes_cnt) {
	457	+ private_data->write_cached_bytes >>= BITS_PER_BYTE *
	458	+ (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
	459	+ writel(private_data->write_cached_bytes,
	460	+ uport->membase + SE_GENI_TX_FIFOn);
	461	+ private_data->write_cached_bytes_cnt = 0;
	462	+ }
	463	+
415	464	qcom_geni_serial_poll_tx_done(uport);
416	465	}
417	466
..	..	@@ -484,7 +533,7 @@
484	533	tport = &uport->state->port;
485	534	for (i = 0; i < bytes; ) {
486	535	int c;
487		- int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
	536	+ int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
488	537
489	538	ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
490	539	i += chunk;
..	..	@@ -501,7 +550,8 @@
501	550	continue;
502	551	}
503	552
504		- sysrq = uart_handle_sysrq_char(uport, buf[c]);
	553	+ sysrq = uart_prepare_sysrq_char(uport, buf[c]);
	554	+
505	555	if (!sysrq)
506	556	tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
507	557	}
..	..	@@ -520,7 +570,6 @@
520	570
521	571	static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
522	572	{
523		- unsigned char *buf;
524	573	struct tty_port *tport;
525	574	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
526	575	u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
..	..	@@ -532,8 +581,7 @@
532	581	if (drop)
533	582	return 0;
534	583
535		- buf = (unsigned char *)port->rx_fifo;
536		- ret = tty_insert_flip_string(tport, buf, bytes);
	584	+ ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
537	585	if (ret != bytes) {
538	586	dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
539	587	__func__, ret, bytes);
..	..	@@ -665,11 +713,11 @@
665	713
666	714	if (!word_cnt)
667	715	return;
668		- total_bytes = port->rx_bytes_pw * (word_cnt - 1);
	716	+ total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
669	717	if (last_word_partial && last_word_byte_cnt)
670	718	total_bytes += last_word_byte_cnt;
671	719	else
672		- total_bytes += port->rx_bytes_pw;
	720	+ total_bytes += BYTES_PER_FIFO_WORD;
673	721	port->handle_rx(uport, total_bytes, drop);
674	722	}
675	723
..	..	@@ -702,7 +750,7 @@
702	750	}
703	751
704	752	avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
705		- avail *= port->tx_bytes_pw;
	753	+ avail *= BYTES_PER_FIFO_WORD;
706	754
707	755	tail = xmit->tail;
708	756	chunk = min(avail, pending);
..	..	@@ -725,8 +773,8 @@
725	773	u8 buf[sizeof(u32)];
726	774	int c;
727	775
728		- memset(buf, 0, ARRAY_SIZE(buf));
729		- tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
	776	+ memset(buf, 0, sizeof(buf));
	777	+ tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
730	778
731	779	for (c = 0; c < tx_bytes ; c++) {
732	780	buf[c] = xmit->buf[tail++];
..	..	@@ -765,12 +813,12 @@
765	813
766	814	static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
767	815	{
768		- unsigned int m_irq_status;
769		- unsigned int s_irq_status;
770		- unsigned int geni_status;
	816	+ u32 m_irq_en;
	817	+ u32 m_irq_status;
	818	+ u32 s_irq_status;
	819	+ u32 geni_status;
771	820	struct uart_port *uport = dev;
772	821	unsigned long flags;
773		- unsigned int m_irq_en;
774	822	bool drop_rx = false;
775	823	struct tty_port *tport = &uport->state->port;
776	824	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
..	..	@@ -813,7 +861,8 @@
813	861	qcom_geni_serial_handle_rx(uport, drop_rx);
814	862
815	863	out_unlock:
816		- spin_unlock_irqrestore(&uport->lock, flags);
	864	+ uart_unlock_and_check_sysrq(uport, flags);
	865	+
817	866	return IRQ_HANDLED;
818	867	}
819	868
..	..	@@ -832,30 +881,15 @@
832	881
833	882	static void qcom_geni_serial_shutdown(struct uart_port *uport)
834	883	{
835		- unsigned long flags;
836		-
837		- /* Stop the console before stopping the current tx */
838		- if (uart_console(uport))
839		- console_stop(uport->cons);
840		-
841		- free_irq(uport->irq, uport);
842		- spin_lock_irqsave(&uport->lock, flags);
843		- qcom_geni_serial_stop_tx(uport);
844		- qcom_geni_serial_stop_rx(uport);
845		- spin_unlock_irqrestore(&uport->lock, flags);
	884	+ disable_irq(uport->irq);
846	885	}
847	886
848	887	static int qcom_geni_serial_port_setup(struct uart_port *uport)
849	888	{
850	889	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
851		- unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
	890	+ u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
852	891	u32 proto;
853		-
854		- if (uart_console(uport))
855		- port->tx_bytes_pw = 1;
856		- else
857		- port->tx_bytes_pw = 4;
858		- port->rx_bytes_pw = RX_BYTES_PW;
	892	+ u32 pin_swap;
859	893
860	894	proto = geni_se_read_proto(&port->se);
861	895	if (proto != GENI_SE_UART) {
..	..	@@ -868,24 +902,30 @@
868	902	get_tx_fifo_size(port);
869	903
870	904	writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
	905	+
	906	+ pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
	907	+ if (port->rx_tx_swap) {
	908	+ pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
	909	+ pin_swap \|= IO_MACRO_IO2_IO3_SWAP;
	910	+ }
	911	+ if (port->cts_rts_swap) {
	912	+ pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
	913	+ pin_swap \|= IO_MACRO_IO0_SEL;
	914	+ }
	915	+ /* Configure this register if RX-TX, CTS-RTS pins are swapped */
	916	+ if (port->rx_tx_swap \|\| port->cts_rts_swap)
	917	+ writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
	918	+
871	919	/*
872	920	* Make an unconditional cancel on the main sequencer to reset
873	921	* it else we could end up in data loss scenarios.
874	922	*/
875	923	if (uart_console(uport))
876	924	qcom_geni_serial_poll_tx_done(uport);
877		- geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
878		- false, true, false);
879		- geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
880		- false, false, true);
	925	+ geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
	926	+ false, true, true);
881	927	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
882	928	geni_se_select_mode(&port->se, GENI_SE_FIFO);
883		- if (!uart_console(uport)) {
884		- port->rx_fifo = devm_kcalloc(uport->dev,
885		- port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
886		- if (!port->rx_fifo)
887		- return -ENOMEM;
888		- }
889	929	port->setup = true;
890	930
891	931	return 0;
..	..	@@ -896,21 +936,14 @@
896	936	int ret;
897	937	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
898	938
899		- scnprintf(port->name, sizeof(port->name),
900		- "qcom_serial_%s%d",
901		- (uart_console(uport) ? "console" : "uart"), uport->line);
902		-
903	939	if (!port->setup) {
904	940	ret = qcom_geni_serial_port_setup(uport);
905	941	if (ret)
906	942	return ret;
907	943	}
	944	+ enable_irq(uport->irq);
908	945
909		- ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
910		- port->name, uport);
911		- if (ret)
912		- dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
913		- return ret;
	946	+ return 0;
914	947	}
915	948
916	949	static unsigned long get_clk_cfg(unsigned long clk_freq)
..	..	@@ -924,12 +957,13 @@
924	957	return 0;
925	958	}
926	959
927		-static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
	960	+static unsigned long get_clk_div_rate(unsigned int baud,
	961	+ unsigned int sampling_rate, unsigned int *clk_div)
928	962	{
929	963	unsigned long ser_clk;
930	964	unsigned long desired_clk;
931	965
932		- desired_clk = baud * UART_OVERSAMPLING;
	966	+ desired_clk = baud * sampling_rate;
933	967	ser_clk = get_clk_cfg(desired_clk);
934	968	if (!ser_clk) {
935	969	pr_err("%s: Can't find matching DFS entry for baud %d\n",
..	..	@@ -945,29 +979,48 @@
945	979	struct ktermios termios, struct ktermios old)
946	980	{
947	981	unsigned int baud;
948		- unsigned int bits_per_char;
949		- unsigned int tx_trans_cfg;
950		- unsigned int tx_parity_cfg;
951		- unsigned int rx_trans_cfg;
952		- unsigned int rx_parity_cfg;
953		- unsigned int stop_bit_len;
	982	+ u32 bits_per_char;
	983	+ u32 tx_trans_cfg;
	984	+ u32 tx_parity_cfg;
	985	+ u32 rx_trans_cfg;
	986	+ u32 rx_parity_cfg;
	987	+ u32 stop_bit_len;
954	988	unsigned int clk_div;
955		- unsigned long ser_clk_cfg;
	989	+ u32 ser_clk_cfg;
956	990	struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
957	991	unsigned long clk_rate;
	992	+ u32 ver, sampling_rate;
	993	+ unsigned int avg_bw_core;
958	994
959	995	qcom_geni_serial_stop_rx(uport);
960	996	/* baud rate */
961	997	baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
962	998	port->baud = baud;
963		- clk_rate = get_clk_div_rate(baud, &clk_div);
	999	+
	1000	+ sampling_rate = UART_OVERSAMPLING;
	1001	+ /* Sampling rate is halved for IP versions >= 2.5 */
	1002	+ ver = geni_se_get_qup_hw_version(&port->se);
	1003	+ if (ver >= QUP_SE_VERSION_2_5)
	1004	+ sampling_rate /= 2;
	1005	+
	1006	+ clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
964	1007	if (!clk_rate)
965	1008	goto out_restart_rx;
966	1009
967	1010	uport->uartclk = clk_rate;
968		- clk_set_rate(port->se.clk, clk_rate);
	1011	+ dev_pm_opp_set_rate(uport->dev, clk_rate);
969	1012	ser_clk_cfg = SER_CLK_EN;
970	1013	ser_clk_cfg \|= clk_div << CLK_DIV_SHFT;
	1014	+
	1015	+ /*
	1016	+ * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
	1017	+ * only.
	1018	+ */
	1019	+ avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
	1020	+ : GENI_DEFAULT_BW;
	1021	+ port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
	1022	+ port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
	1023	+ geni_icc_set_bw(&port->se);
971	1024
972	1025	/* parity */
973	1026	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
..	..	@@ -1054,7 +1107,7 @@
1054	1107	{
1055	1108	struct uart_port *uport;
1056	1109	struct qcom_geni_serial_port *port;
1057		- int baud = 9600;
	1110	+ int baud = 115200;
1058	1111	int bits = 8;
1059	1112	int parity = 'n';
1060	1113	int flow = 'n';
..	..	@@ -1094,6 +1147,38 @@
1094	1147	__qcom_geni_serial_console_write(&dev->port, s, n);
1095	1148	}
1096	1149
	1150	+#ifdef CONFIG_CONSOLE_POLL
	1151	+static int qcom_geni_serial_earlycon_read(struct console *con,
	1152	+ char *s, unsigned int n)
	1153	+{
	1154	+ struct earlycon_device *dev = con->data;
	1155	+ struct uart_port *uport = &dev->port;
	1156	+ int num_read = 0;
	1157	+ int ch;
	1158	+
	1159	+ while (num_read < n) {
	1160	+ ch = qcom_geni_serial_get_char(uport);
	1161	+ if (ch == NO_POLL_CHAR)
	1162	+ break;
	1163	+ s[num_read++] = ch;
	1164	+ }
	1165	+
	1166	+ return num_read;
	1167	+}
	1168	+
	1169	+static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
	1170	+ struct console *con)
	1171	+{
	1172	+ geni_se_setup_s_cmd(se, UART_START_READ, 0);
	1173	+ con->read = qcom_geni_serial_earlycon_read;
	1174	+}
	1175	+#else
	1176	+static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
	1177	+ struct console *con) { }
	1178	+#endif
	1179	+
	1180	+static struct qcom_geni_private_data earlycon_private_data;
	1181	+
1097	1182	static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1098	1183	const char *opt)
1099	1184	{
..	..	@@ -1108,6 +1193,8 @@
1108	1193
1109	1194	if (!uport->membase)
1110	1195	return -EINVAL;
	1196	+
	1197	+ uport->private_data = &earlycon_private_data;
1111	1198
1112	1199	memset(&se, 0, sizeof(se));
1113	1200	se.base = uport->membase;
..	..	@@ -1126,7 +1213,8 @@
1126	1213	*/
1127	1214	qcom_geni_serial_poll_tx_done(uport);
1128	1215	qcom_geni_serial_abort_rx(uport);
1129		- geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
	1216	+ geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
	1217	+ false, true, true);
1130	1218	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1131	1219	geni_se_select_mode(&se, GENI_SE_FIFO);
1132	1220
..	..	@@ -1140,6 +1228,8 @@
1140	1228
1141	1229	dev->con->write = qcom_geni_serial_earlycon_write;
1142	1230	dev->con->setup = NULL;
	1231	+ qcom_geni_serial_enable_early_read(&se, dev->con);
	1232	+
1143	1233	return 0;
1144	1234	}
1145	1235	OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
..	..	@@ -1199,11 +1289,14 @@
1199	1289	if (old_state == UART_PM_STATE_UNDEFINED)
1200	1290	old_state = UART_PM_STATE_OFF;
1201	1291
1202		- if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
	1292	+ if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
	1293	+ geni_icc_enable(&port->se);
1203	1294	geni_se_resources_on(&port->se);
1204		- else if (new_state == UART_PM_STATE_OFF &&
1205		- old_state == UART_PM_STATE_ON)
	1295	+ } else if (new_state == UART_PM_STATE_OFF &&
	1296	+ old_state == UART_PM_STATE_ON) {
1206	1297	geni_se_resources_off(&port->se);
	1298	+ geni_icc_disable(&port->se);
	1299	+ }
1207	1300	}
1208	1301
1209	1302	static const struct uart_ops qcom_geni_console_pops = {
..	..	@@ -1256,14 +1349,12 @@
1256	1349	if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1257	1350	console = true;
1258	1351
1259		- if (pdev->dev.of_node) {
1260		- if (console) {
1261		- drv = &qcom_geni_console_driver;
1262		- line = of_alias_get_id(pdev->dev.of_node, "serial");
1263		- } else {
1264		- drv = &qcom_geni_uart_driver;
1265		- line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1266		- }
	1352	+ if (console) {
	1353	+ drv = &qcom_geni_console_driver;
	1354	+ line = of_alias_get_id(pdev->dev.of_node, "serial");
	1355	+ } else {
	1356	+ drv = &qcom_geni_uart_driver;
	1357	+ line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1267	1358	}
1268	1359
1269	1360	port = get_port_from_line(line, console);
..	..	@@ -1296,73 +1387,148 @@
1296	1387	port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1297	1388	port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1298	1389
1299		- irq = platform_get_irq(pdev, 0);
1300		- if (irq < 0) {
1301		- dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1302		- return irq;
	1390	+ if (!console) {
	1391	+ port->rx_fifo = devm_kcalloc(uport->dev,
	1392	+ port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
	1393	+ if (!port->rx_fifo)
	1394	+ return -ENOMEM;
1303	1395	}
1304		- uport->irq = irq;
1305	1396
1306		- uport->private_data = drv;
	1397	+ ret = geni_icc_get(&port->se, NULL);
	1398	+ if (ret)
	1399	+ return ret;
	1400	+ port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
	1401	+ port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
	1402	+
	1403	+ /* Set BW for register access */
	1404	+ ret = geni_icc_set_bw(&port->se);
	1405	+ if (ret)
	1406	+ return ret;
	1407	+
	1408	+ port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
	1409	+ "qcom_geni_serial_%s%d",
	1410	+ uart_console(uport) ? "console" : "uart", uport->line);
	1411	+ if (!port->name)
	1412	+ return -ENOMEM;
	1413	+
	1414	+ irq = platform_get_irq(pdev, 0);
	1415	+ if (irq < 0)
	1416	+ return irq;
	1417	+ uport->irq = irq;
	1418	+ uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
	1419	+
	1420	+ if (!console)
	1421	+ port->wakeup_irq = platform_get_irq_optional(pdev, 1);
	1422	+
	1423	+ if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
	1424	+ port->rx_tx_swap = true;
	1425	+
	1426	+ if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
	1427	+ port->cts_rts_swap = true;
	1428	+
	1429	+ port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
	1430	+ if (IS_ERR(port->se.opp_table))
	1431	+ return PTR_ERR(port->se.opp_table);
	1432	+ /* OPP table is optional */
	1433	+ ret = dev_pm_opp_of_add_table(&pdev->dev);
	1434	+ if (ret && ret != -ENODEV) {
	1435	+ dev_err(&pdev->dev, "invalid OPP table in device tree\n");
	1436	+ goto put_clkname;
	1437	+ }
	1438	+
	1439	+ port->private_data.drv = drv;
	1440	+ uport->private_data = &port->private_data;
1307	1441	platform_set_drvdata(pdev, port);
1308	1442	port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1309		- if (!console)
1310		- device_create_file(uport->dev, &dev_attr_loopback);
1311		- return uart_add_one_port(drv, uport);
	1443	+
	1444	+ ret = uart_add_one_port(drv, uport);
	1445	+ if (ret)
	1446	+ goto err;
	1447	+
	1448	+ irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
	1449	+ ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
	1450	+ IRQF_TRIGGER_HIGH, port->name, uport);
	1451	+ if (ret) {
	1452	+ dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
	1453	+ uart_remove_one_port(drv, uport);
	1454	+ goto err;
	1455	+ }
	1456	+
	1457	+ /*
	1458	+ * Set pm_runtime status as ACTIVE so that wakeup_irq gets
	1459	+ * enabled/disabled from dev_pm_arm_wake_irq during system
	1460	+ * suspend/resume respectively.
	1461	+ */
	1462	+ pm_runtime_set_active(&pdev->dev);
	1463	+
	1464	+ if (port->wakeup_irq > 0) {
	1465	+ device_init_wakeup(&pdev->dev, true);
	1466	+ ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
	1467	+ port->wakeup_irq);
	1468	+ if (ret) {
	1469	+ device_init_wakeup(&pdev->dev, false);
	1470	+ uart_remove_one_port(drv, uport);
	1471	+ goto err;
	1472	+ }
	1473	+ }
	1474	+
	1475	+ return 0;
	1476	+err:
	1477	+ dev_pm_opp_of_remove_table(&pdev->dev);
	1478	+put_clkname:
	1479	+ dev_pm_opp_put_clkname(port->se.opp_table);
	1480	+ return ret;
1312	1481	}
1313	1482
1314	1483	static int qcom_geni_serial_remove(struct platform_device *pdev)
1315	1484	{
1316	1485	struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1317		- struct uart_driver *drv = port->uport.private_data;
	1486	+ struct uart_driver *drv = port->private_data.drv;
1318	1487
	1488	+ dev_pm_opp_of_remove_table(&pdev->dev);
	1489	+ dev_pm_opp_put_clkname(port->se.opp_table);
	1490	+ dev_pm_clear_wake_irq(&pdev->dev);
	1491	+ device_init_wakeup(&pdev->dev, false);
1319	1492	uart_remove_one_port(drv, &port->uport);
	1493	+
1320	1494	return 0;
1321	1495	}
1322	1496
1323		-static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
	1497	+static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1324	1498	{
1325	1499	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1326	1500	struct uart_port *uport = &port->uport;
	1501	+ struct qcom_geni_private_data *private_data = uport->private_data;
1327	1502
	1503	+ /*
	1504	+ * This is done so we can hit the lowest possible state in suspend
	1505	+ * even with no_console_suspend
	1506	+ */
1328	1507	if (uart_console(uport)) {
1329		- uart_suspend_port(uport->private_data, uport);
1330		- } else {
1331		- struct uart_state *state = uport->state;
1332		- /*
1333		- * If the port is open, deny system suspend.
1334		- */
1335		- if (state->pm_state == UART_PM_STATE_ON)
1336		- return -EBUSY;
	1508	+ geni_icc_set_tag(&port->se, 0x3);
	1509	+ geni_icc_set_bw(&port->se);
1337	1510	}
1338		-
1339		- return 0;
	1511	+ return uart_suspend_port(private_data->drv, uport);
1340	1512	}
1341	1513
1342		-static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
	1514	+static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1343	1515	{
	1516	+ int ret;
1344	1517	struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1345	1518	struct uart_port *uport = &port->uport;
	1519	+ struct qcom_geni_private_data *private_data = uport->private_data;
1346	1520
1347		- if (uart_console(uport) &&
1348		- console_suspend_enabled && uport->suspended) {
1349		- uart_resume_port(uport->private_data, uport);
1350		- /*
1351		- * uart_suspend_port() invokes port shutdown which in turn
1352		- * frees the irq. uart_resume_port invokes port startup which
1353		- * performs request_irq. The request_irq auto-enables the IRQ.
1354		- * In addition, resume_noirq implicitly enables the IRQ and
1355		- * leads to an unbalanced IRQ enable warning. Disable the IRQ
1356		- * before returning so that the warning is suppressed.
1357		- */
1358		- disable_irq(uport->irq);
	1521	+ ret = uart_resume_port(private_data->drv, uport);
	1522	+ if (uart_console(uport)) {
	1523	+ geni_icc_set_tag(&port->se, 0x7);
	1524	+ geni_icc_set_bw(&port->se);
1359	1525	}
1360		- return 0;
	1526	+ return ret;
1361	1527	}
1362	1528
1363	1529	static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1364		- SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1365		- qcom_geni_serial_sys_resume_noirq)
	1530	+ SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
	1531	+ qcom_geni_serial_sys_resume)
1366	1532	};
1367	1533
1368	1534	static const struct of_device_id qcom_geni_serial_match_table[] = {