forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 223293205a7265c8b02882461ba8996650048ade 
 kernel/drivers/media/platform/rockchip/cif/hw.c
....@@ -17,14 +17,17 @@
1717 #include <linux/pm_runtime.h>
1818 #include <linux/pinctrl/consumer.h>
1919 #include <linux/regmap.h>
20
+#include <media/videobuf2-cma-sg.h>
2021 #include <media/videobuf2-dma-contig.h>
22
+#include <media/videobuf2-dma-sg.h>
2123 #include <media/v4l2-fwnode.h>
2224 #include <linux/iommu.h>
2325 #include <dt-bindings/soc/rockchip-system-status.h>
2426 #include <soc/rockchip/rockchip-system-status.h>
2527 #include <linux/io.h>
2628 #include <linux/mfd/syscon.h>
27
-#include "dev.h"
29
+#include <soc/rockchip/rockchip_iommu.h>
30
+#include "common.h"
2831 
2932 static const struct cif_reg px30_cif_regs[] = {
3033 	[CIF_REG_DVP_CTRL] = CIF_REG(CIF_CTRL),
....@@ -597,6 +600,365 @@
597600 	[CIF_REG_GRF_CIFIO_CON1] = CIF_REG(CIF_GRF_VI_CON1),
598601 };
599602 
603
+static const char * const rk3588_cif_clks[] = {
604
+	"aclk_cif",
605
+	"hclk_cif",
606
+	"dclk_cif",
607
+	"iclk_host0",
608
+	"iclk_host1",
609
+};
610
+
611
+static const char * const rk3588_cif_rsts[] = {
612
+	"rst_cif_a",
613
+	"rst_cif_h",
614
+	"rst_cif_d",
615
+	"rst_cif_host0",
616
+	"rst_cif_host1",
617
+	"rst_cif_host2",
618
+	"rst_cif_host3",
619
+	"rst_cif_host4",
620
+	"rst_cif_host5",
621
+};
622
+
623
+static const struct cif_reg rk3588_cif_regs[] = {
624
+	[CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
625
+	[CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
626
+	[CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
627
+	[CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
628
+	[CIF_REG_DVP_MULTI_ID] = CIF_REG(DVP_MULTI_ID),
629
+	[CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
630
+	[CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
631
+	[CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
632
+	[CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
633
+	[CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
634
+	[CIF_REG_DVP_FRM0_ADDR_Y_ID1] = CIF_REG(DVP_FRM0_ADDR_Y_ID1),
635
+	[CIF_REG_DVP_FRM0_ADDR_UV_ID1] = CIF_REG(DVP_FRM0_ADDR_UV_ID1),
636
+	[CIF_REG_DVP_FRM1_ADDR_Y_ID1] = CIF_REG(DVP_FRM1_ADDR_Y_ID1),
637
+	[CIF_REG_DVP_FRM1_ADDR_UV_ID1] = CIF_REG(DVP_FRM1_ADDR_UV_ID1),
638
+	[CIF_REG_DVP_FRM0_ADDR_Y_ID2] = CIF_REG(DVP_FRM0_ADDR_Y_ID2),
639
+	[CIF_REG_DVP_FRM0_ADDR_UV_ID2] = CIF_REG(DVP_FRM0_ADDR_UV_ID2),
640
+	[CIF_REG_DVP_FRM1_ADDR_Y_ID2] = CIF_REG(DVP_FRM1_ADDR_Y_ID2),
641
+	[CIF_REG_DVP_FRM1_ADDR_UV_ID2] = CIF_REG(DVP_FRM1_ADDR_UV_ID2),
642
+	[CIF_REG_DVP_FRM0_ADDR_Y_ID3] = CIF_REG(DVP_FRM0_ADDR_Y_ID3),
643
+	[CIF_REG_DVP_FRM0_ADDR_UV_ID3] = CIF_REG(DVP_FRM0_ADDR_UV_ID3),
644
+	[CIF_REG_DVP_FRM1_ADDR_Y_ID3] = CIF_REG(DVP_FRM1_ADDR_Y_ID3),
645
+	[CIF_REG_DVP_FRM1_ADDR_UV_ID3] = CIF_REG(DVP_FRM1_ADDR_UV_ID3),
646
+	[CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
647
+	[CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
648
+	[CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
649
+	[CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
650
+	[CIF_REG_DVP_LINE_INT_NUM1] = CIF_REG(DVP_LINE_INT_NUM_23),
651
+	[CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_INT_NUM_01),
652
+	[CIF_REG_DVP_LINE_CNT1] = CIF_REG(DVP_LINE_INT_NUM_23),
653
+
654
+	[CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
655
+	[CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
656
+	[CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
657
+	[CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
658
+	[CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
659
+	[CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
660
+	[CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
661
+	[CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
662
+	[CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
663
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
664
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
665
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
666
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
667
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
668
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
669
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
670
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
671
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
672
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
673
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
674
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
675
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
676
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
677
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
678
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
679
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
680
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
681
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
682
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
683
+	[CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
684
+	[CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
685
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
686
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
687
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
688
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
689
+	[CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
690
+	[CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
691
+	[CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
692
+	[CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
693
+	[CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
694
+	[CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
695
+	[CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
696
+	[CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
697
+	[CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
698
+	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
699
+	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
700
+	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
701
+	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
702
+
703
+	[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
704
+	[CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
705
+	[CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
706
+
707
+	[CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
708
+	[CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
709
+	[CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
710
+	[CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
711
+	[CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
712
+	[CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
713
+	[CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
714
+	[CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
715
+	[CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
716
+	[CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
717
+	[CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
718
+	[CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
719
+	[CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
720
+	[CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
721
+	[CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
722
+	[CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
723
+	[CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
724
+	[CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
725
+	[CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
726
+	[CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
727
+	[CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
728
+	[CIF_REG_TOISP1_CTRL] = CIF_REG(TOISP1_CH_CTRL),
729
+	[CIF_REG_TOISP1_SIZE] = CIF_REG(TOISP1_CROP_SIZE),
730
+	[CIF_REG_TOISP1_CROP] = CIF_REG(TOISP1_CROP),
731
+	[CIF_REG_GRF_CIFIO_CON] = CIF_REG(CIF_GRF_SOC_CON2),
732
+};
733
+
734
+static const char * const rv1106_cif_clks[] = {
735
+	"aclk_cif",
736
+	"hclk_cif",
737
+	"dclk_cif",
738
+	"pclk_cif",
739
+	"i0clk_cif",
740
+	"i1clk_cif",
741
+	"rx0clk_cif",
742
+	"rx1clk_cif",
743
+	"isp0clk_cif",
744
+	"sclk_m0_cif",
745
+	"sclk_m1_cif",
746
+	"pclk_vepu_cif",
747
+};
748
+
749
+static const char * const rv1106_cif_rsts[] = {
750
+	"rst_cif_a",
751
+	"rst_cif_h",
752
+	"rst_cif_d",
753
+	"rst_cif_p",
754
+	"rst_cif_i0",
755
+	"rst_cif_i1",
756
+	"rst_cif_rx0",
757
+	"rst_cif_rx1",
758
+	"rst_cif_isp0",
759
+	"rst_cif_pclk_vepu",
760
+};
761
+
762
+static const struct cif_reg rv1106_cif_regs[] = {
763
+	[CIF_REG_DVP_CTRL] = CIF_REG(DVP_CTRL),
764
+	[CIF_REG_DVP_INTEN] = CIF_REG(DVP_INTEN),
765
+	[CIF_REG_DVP_INTSTAT] = CIF_REG(DVP_INTSTAT),
766
+	[CIF_REG_DVP_FOR] = CIF_REG(DVP_FOR),
767
+	[CIF_REG_DVP_SAV_EAV] = CIF_REG(DVP_SAV_EAV),
768
+	[CIF_REG_DVP_FRM0_ADDR_Y] = CIF_REG(DVP_FRM0_ADDR_Y_ID0),
769
+	[CIF_REG_DVP_FRM0_ADDR_UV] = CIF_REG(DVP_FRM0_ADDR_UV_ID0),
770
+	[CIF_REG_DVP_FRM1_ADDR_Y] = CIF_REG(DVP_FRM1_ADDR_Y_ID0),
771
+	[CIF_REG_DVP_FRM1_ADDR_UV] = CIF_REG(DVP_FRM1_ADDR_UV_ID0),
772
+	[CIF_REG_DVP_VIR_LINE_WIDTH] = CIF_REG(DVP_VIR_LINE_WIDTH),
773
+	[CIF_REG_DVP_SET_SIZE] = CIF_REG(DVP_CROP_SIZE),
774
+	[CIF_REG_DVP_CROP] = CIF_REG(DVP_CROP),
775
+	[CIF_REG_DVP_LINE_INT_NUM] = CIF_REG(DVP_LINE_INT_NUM_01),
776
+	[CIF_REG_DVP_LINE_CNT] = CIF_REG(DVP_LINE_CNT_01),
777
+
778
+	[CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
779
+	[CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
780
+	[CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
781
+	[CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
782
+	[CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
783
+	[CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
784
+	[CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
785
+	[CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
786
+	[CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
787
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
788
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
789
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
790
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
791
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
792
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
793
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
794
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
795
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
796
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
797
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
798
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
799
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
800
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
801
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
802
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
803
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
804
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
805
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
806
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
807
+	[CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
808
+	[CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
809
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
810
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
811
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
812
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
813
+	[CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
814
+	[CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
815
+	[CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
816
+	[CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
817
+	[CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
818
+	[CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
819
+	[CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
820
+	[CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
821
+	[CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
822
+	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
823
+	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
824
+	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
825
+	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
826
+	[CIF_REG_LVDS_ID0_CTRL0] = CIF_REG(CIF_LVDS0_ID0_CTRL0),
827
+	[CIF_REG_LVDS_ID1_CTRL0] = CIF_REG(CIF_LVDS0_ID1_CTRL0),
828
+	[CIF_REG_LVDS_ID2_CTRL0] = CIF_REG(CIF_LVDS0_ID2_CTRL0),
829
+	[CIF_REG_LVDS_ID3_CTRL0] = CIF_REG(CIF_LVDS0_ID3_CTRL0),
830
+	[CIF_REG_LVDS_SAV_EAV_ACT0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID0_RV1106),
831
+	[CIF_REG_LVDS_SAV_EAV_BLK0_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID0_RV1106),
832
+	[CIF_REG_LVDS_SAV_EAV_ACT1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID0_RV1106),
833
+	[CIF_REG_LVDS_SAV_EAV_BLK1_ID0] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID0_RV1106),
834
+	[CIF_REG_LVDS_SAV_EAV_ACT0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID1_RV1106),
835
+	[CIF_REG_LVDS_SAV_EAV_BLK0_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID1_RV1106),
836
+	[CIF_REG_LVDS_SAV_EAV_ACT1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID1_RV1106),
837
+	[CIF_REG_LVDS_SAV_EAV_BLK1_ID1] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID1_RV1106),
838
+	[CIF_REG_LVDS_SAV_EAV_ACT0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID2_RV1106),
839
+	[CIF_REG_LVDS_SAV_EAV_BLK0_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID2_RV1106),
840
+	[CIF_REG_LVDS_SAV_EAV_ACT1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID2_RV1106),
841
+	[CIF_REG_LVDS_SAV_EAV_BLK1_ID2] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID2_RV1106),
842
+	[CIF_REG_LVDS_SAV_EAV_ACT0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT0_ID3_RV1106),
843
+	[CIF_REG_LVDS_SAV_EAV_BLK0_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK0_ID3_RV1106),
844
+	[CIF_REG_LVDS_SAV_EAV_ACT1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_ACT1_ID3_RV1106),
845
+	[CIF_REG_LVDS_SAV_EAV_BLK1_ID3] = CIF_REG(CIF_LVDS_SAV_EAV_BLK1_ID3_RV1106),
846
+	[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
847
+	[CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
848
+	[CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
849
+
850
+	[CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
851
+	[CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
852
+	[CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
853
+	[CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
854
+	[CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
855
+	[CIF_REG_SCL_FRM0_ADDR_CH1] = CIF_REG(SCL_FRM0_ADDR_CH1),
856
+	[CIF_REG_SCL_FRM1_ADDR_CH1] = CIF_REG(SCL_FRM1_ADDR_CH1),
857
+	[CIF_REG_SCL_VLW_CH1] = CIF_REG(SCL_VLW_CH1),
858
+	[CIF_REG_SCL_FRM0_ADDR_CH2] = CIF_REG(SCL_FRM0_ADDR_CH2),
859
+	[CIF_REG_SCL_FRM1_ADDR_CH2] = CIF_REG(SCL_FRM1_ADDR_CH2),
860
+	[CIF_REG_SCL_VLW_CH2] = CIF_REG(SCL_VLW_CH2),
861
+	[CIF_REG_SCL_FRM0_ADDR_CH3] = CIF_REG(SCL_FRM0_ADDR_CH3),
862
+	[CIF_REG_SCL_FRM1_ADDR_CH3] = CIF_REG(SCL_FRM1_ADDR_CH3),
863
+	[CIF_REG_SCL_VLW_CH3] = CIF_REG(SCL_VLW_CH3),
864
+	[CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
865
+	[CIF_REG_SCL_BLC_CH1] = CIF_REG(SCL_BLC_CH1),
866
+	[CIF_REG_SCL_BLC_CH2] = CIF_REG(SCL_BLC_CH2),
867
+	[CIF_REG_SCL_BLC_CH3] = CIF_REG(SCL_BLC_CH3),
868
+
869
+	[CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
870
+	[CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
871
+	[CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
872
+	[CIF_REG_GRF_CIFIO_CON] = CIF_REG(RV1106_CIF_GRF_VI_CON),
873
+	[CIF_REG_GRF_CIFIO_VENC] = CIF_REG(RV1106_CIF_GRF_VENC_WRAPPER),
874
+};
875
+
876
+static const char * const rk3562_cif_clks[] = {
877
+	"aclk_cif",
878
+	"hclk_cif",
879
+	"dclk_cif",
880
+	"csirx0_data",
881
+	"csirx1_data",
882
+	"csirx2_data",
883
+	"csirx3_data",
884
+};
885
+
886
+static const char * const rk3562_cif_rsts[] = {
887
+	"rst_cif_a",
888
+	"rst_cif_h",
889
+	"rst_cif_d",
890
+	"rst_cif_i0",
891
+	"rst_cif_i1",
892
+	"rst_cif_i2",
893
+	"rst_cif_i3",
894
+};
895
+
896
+static const struct cif_reg rk3562_cif_regs[] = {
897
+	[CIF_REG_MIPI_LVDS_ID0_CTRL0] = CIF_REG(CSI_MIPI0_ID0_CTRL0),
898
+	[CIF_REG_MIPI_LVDS_ID0_CTRL1] = CIF_REG(CSI_MIPI0_ID0_CTRL1),
899
+	[CIF_REG_MIPI_LVDS_ID1_CTRL0] = CIF_REG(CSI_MIPI0_ID1_CTRL0),
900
+	[CIF_REG_MIPI_LVDS_ID1_CTRL1] = CIF_REG(CSI_MIPI0_ID1_CTRL1),
901
+	[CIF_REG_MIPI_LVDS_ID2_CTRL0] = CIF_REG(CSI_MIPI0_ID2_CTRL0),
902
+	[CIF_REG_MIPI_LVDS_ID2_CTRL1] = CIF_REG(CSI_MIPI0_ID2_CTRL1),
903
+	[CIF_REG_MIPI_LVDS_ID3_CTRL0] = CIF_REG(CSI_MIPI0_ID3_CTRL0),
904
+	[CIF_REG_MIPI_LVDS_ID3_CTRL1] = CIF_REG(CSI_MIPI0_ID3_CTRL1),
905
+	[CIF_REG_MIPI_LVDS_CTRL] = CIF_REG(CSI_MIPI0_CTRL),
906
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID0),
907
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID0),
908
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID0),
909
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID0),
910
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0] = CIF_REG(CSI_MIPI0_VLW_ID0),
911
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID1),
912
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID1),
913
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID1),
914
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID1),
915
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1] = CIF_REG(CSI_MIPI0_VLW_ID1),
916
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID2),
917
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID2),
918
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID2),
919
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID2),
920
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2] = CIF_REG(CSI_MIPI0_VLW_ID2),
921
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_Y_ID3),
922
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_Y_ID3),
923
+	[CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM0_ADDR_UV_ID3),
924
+	[CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3] = CIF_REG(CSI_MIPI0_FRM1_ADDR_UV_ID3),
925
+	[CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3] = CIF_REG(CSI_MIPI0_VLW_ID3),
926
+	[CIF_REG_MIPI_LVDS_INTEN] = CIF_REG(CSI_MIPI0_INTEN),
927
+	[CIF_REG_MIPI_LVDS_INTSTAT] = CIF_REG(CSI_MIPI0_INTSTAT),
928
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID0_1),
929
+	[CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3] = CIF_REG(CSI_MIPI0_LINE_INT_NUM_ID2_3),
930
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1] = CIF_REG(CSI_MIPI0_LINE_CNT_ID0_1),
931
+	[CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3] = CIF_REG(CSI_MIPI0_LINE_CNT_ID2_3),
932
+	[CIF_REG_MIPI_LVDS_ID0_CROP_START] = CIF_REG(CSI_MIPI0_ID0_CROP_START),
933
+	[CIF_REG_MIPI_LVDS_ID1_CROP_START] = CIF_REG(CSI_MIPI0_ID1_CROP_START),
934
+	[CIF_REG_MIPI_LVDS_ID2_CROP_START] = CIF_REG(CSI_MIPI0_ID2_CROP_START),
935
+	[CIF_REG_MIPI_LVDS_ID3_CROP_START] = CIF_REG(CSI_MIPI0_ID3_CROP_START),
936
+	[CIF_REG_MIPI_FRAME_NUM_VC0] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC0),
937
+	[CIF_REG_MIPI_FRAME_NUM_VC1] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC1),
938
+	[CIF_REG_MIPI_FRAME_NUM_VC2] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC2),
939
+	[CIF_REG_MIPI_FRAME_NUM_VC3] = CIF_REG(CSI_MIPI0_FRAME_NUM_VC3),
940
+	[CIF_REG_MIPI_EFFECT_CODE_ID0] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID0),
941
+	[CIF_REG_MIPI_EFFECT_CODE_ID1] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID1),
942
+	[CIF_REG_MIPI_EFFECT_CODE_ID2] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID2),
943
+	[CIF_REG_MIPI_EFFECT_CODE_ID3] = CIF_REG(CSI_MIPI0_EFFECT_CODE_ID3),
944
+	[CIF_REG_MIPI_ON_PAD] = CIF_REG(CSI_MIPI0_ON_PAD),
945
+
946
+	[CIF_REG_GLB_CTRL] = CIF_REG(GLB_CTRL),
947
+	[CIF_REG_GLB_INTEN] = CIF_REG(GLB_INTEN),
948
+	[CIF_REG_GLB_INTST] = CIF_REG(GLB_INTST),
949
+
950
+	[CIF_REG_SCL_CH_CTRL] = CIF_REG(SCL_CH_CTRL),
951
+	[CIF_REG_SCL_CTRL] = CIF_REG(SCL_CTRL),
952
+	[CIF_REG_SCL_FRM0_ADDR_CH0] = CIF_REG(SCL_FRM0_ADDR_CH0),
953
+	[CIF_REG_SCL_FRM1_ADDR_CH0] = CIF_REG(SCL_FRM1_ADDR_CH0),
954
+	[CIF_REG_SCL_VLW_CH0] = CIF_REG(SCL_VLW_CH0),
955
+	[CIF_REG_SCL_BLC_CH0] = CIF_REG(SCL_BLC_CH0),
956
+
957
+	[CIF_REG_TOISP0_CTRL] = CIF_REG(TOISP0_CH_CTRL),
958
+	[CIF_REG_TOISP0_SIZE] = CIF_REG(TOISP0_CROP_SIZE),
959
+	[CIF_REG_TOISP0_CROP] = CIF_REG(TOISP0_CROP),
960
+};
961
+
600962 static const struct rkcif_hw_match_data px30_cif_match_data = {
601963 	.chip_id = CHIP_PX30_CIF,
602964 	.clks = px30_cif_clks,
....@@ -678,6 +1040,32 @@
6781040 	.cif_regs = rk3568_cif_regs,
6791041 };
6801042 
1043
+static const struct rkcif_hw_match_data rk3588_cif_match_data = {
1044
+	.chip_id = CHIP_RK3588_CIF,
1045
+	.clks = rk3588_cif_clks,
1046
+	.clks_num = ARRAY_SIZE(rk3588_cif_clks),
1047
+	.rsts = rk3588_cif_rsts,
1048
+	.rsts_num = ARRAY_SIZE(rk3588_cif_rsts),
1049
+	.cif_regs = rk3588_cif_regs,
1050
+};
1051
+
1052
+static const struct rkcif_hw_match_data rv1106_cif_match_data = {
1053
+	.chip_id = CHIP_RV1106_CIF,
1054
+	.clks = rv1106_cif_clks,
1055
+	.clks_num = ARRAY_SIZE(rv1106_cif_clks),
1056
+	.rsts = rv1106_cif_rsts,
1057
+	.rsts_num = ARRAY_SIZE(rv1106_cif_rsts),
1058
+	.cif_regs = rv1106_cif_regs,
1059
+};
1060
+
1061
+static const struct rkcif_hw_match_data rk3562_cif_match_data = {
1062
+	.chip_id = CHIP_RK3562_CIF,
1063
+	.clks = rk3562_cif_clks,
1064
+	.clks_num = ARRAY_SIZE(rk3562_cif_clks),
1065
+	.rsts = rk3562_cif_rsts,
1066
+	.rsts_num = ARRAY_SIZE(rk3562_cif_rsts),
1067
+	.cif_regs = rk3562_cif_regs,
1068
+};
6811069 
6821070 static const struct of_device_id rkcif_plat_of_match[] = {
6831071 #ifdef CONFIG_CPU_PX30
....@@ -722,6 +1110,12 @@
7221110 		.data = &rk3568_cif_match_data,
7231111 	},
7241112 #endif
1113
+#ifdef CONFIG_CPU_RK3588
1114
+	{
1115
+		.compatible = "rockchip,rk3588-cif",
1116
+		.data = &rk3588_cif_match_data,
1117
+	},
1118
+#endif
7251119 #ifdef CONFIG_CPU_RV1126
7261120 	{
7271121 		.compatible = "rockchip,rv1126-cif",
....@@ -732,6 +1126,18 @@
7321126 		.data = &rv1126_cif_lite_match_data,
7331127 	},
7341128 #endif
1129
+#ifdef CONFIG_CPU_RV1106
1130
+	{
1131
+		.compatible = "rockchip,rv1106-cif",
1132
+		.data = &rv1106_cif_match_data,
1133
+	},
1134
+#endif
1135
+#ifdef CONFIG_CPU_RK3562
1136
+	{
1137
+		.compatible = "rockchip,rk3562-cif",
1138
+		.data = &rk3562_cif_match_data,
1139
+	},
1140
+#endif
7351141 	{},
7361142 };
7371143 
....@@ -739,16 +1145,32 @@
7391145 {
7401146 	struct device *dev = ctx;
7411147 	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
1148
+	unsigned int intstat_glb = 0;
1149
+	u64 irq_start, irq_stop;
7421150 	int i;
743
-	struct rkcif_device *tmp_dev = NULL;
7441151 
745
-	for (i = 0; i < cif_hw->dev_num; i++) {
746
-		tmp_dev = cif_hw->cif_dev[i];
747
-		if (tmp_dev->isr_hdl &&
748
-		    (atomic_read(&tmp_dev->pipe.stream_cnt) != 0))
749
-			tmp_dev->isr_hdl(irq, tmp_dev);
1152
+	irq_start = ktime_get_ns();
1153
+	if (cif_hw->chip_id >= CHIP_RK3588_CIF) {
1154
+		intstat_glb = rkcif_irq_global(cif_hw->cif_dev[0]);
1155
+		if (intstat_glb)
1156
+			rkcif_write_register(cif_hw->cif_dev[0], CIF_REG_GLB_INTST, intstat_glb);
7501157 	}
7511158 
1159
+	for (i = 0; i < cif_hw->dev_num; i++) {
1160
+		if (cif_hw->cif_dev[i]->isr_hdl) {
1161
+			cif_hw->cif_dev[i]->isr_hdl(irq, cif_hw->cif_dev[i]);
1162
+			if (cif_hw->cif_dev[i]->err_state &&
1163
+			    (!work_busy(&cif_hw->cif_dev[i]->err_state_work.work))) {
1164
+				cif_hw->cif_dev[i]->err_state_work.err_state = cif_hw->cif_dev[i]->err_state;
1165
+				cif_hw->cif_dev[i]->err_state = 0;
1166
+				schedule_work(&cif_hw->cif_dev[i]->err_state_work.work);
1167
+			}
1168
+			if (cif_hw->chip_id >= CHIP_RK3588_CIF && intstat_glb)
1169
+				rkcif_irq_handle_toisp(cif_hw->cif_dev[i], intstat_glb);
1170
+		}
1171
+	}
1172
+	irq_stop = ktime_get_ns();
1173
+	cif_hw->irq_time = irq_stop - irq_start;
7521174 	return IRQ_HANDLED;
7531175 }
7541176 
....@@ -783,17 +1205,14 @@
7831205 
7841206 static void rkcif_iommu_cleanup(struct rkcif_hw *cif_hw)
7851207 {
786
-	if (cif_hw->domain)
787
-		iommu_detach_device(cif_hw->domain, cif_hw->dev);
1208
+	if (cif_hw->iommu_en)
1209
+		rockchip_iommu_disable(cif_hw->dev);
7881210 }
7891211 
7901212 static void rkcif_iommu_enable(struct rkcif_hw *cif_hw)
7911213 {
792
-	if (!cif_hw->domain)
793
-		cif_hw->domain = iommu_get_domain_for_dev(cif_hw->dev);
794
-
795
-	if (cif_hw->domain)
796
-		iommu_attach_device(cif_hw->domain, cif_hw->dev);
1214
+	if (cif_hw->iommu_en)
1215
+		rockchip_iommu_enable(cif_hw->dev);
7971216 }
7981217 
7991218 static inline bool is_iommu_enable(struct device *dev)
....@@ -833,83 +1252,6 @@
8331252 		rkcif_iommu_enable(cif_hw);
8341253 }
8351254 
836
-static char *rkcif_get_monitor_mode(enum rkcif_monitor_mode mode)
837
-{
838
-	switch (mode) {
839
-	case RKCIF_MONITOR_MODE_IDLE:
840
-		return "idle";
841
-	case RKCIF_MONITOR_MODE_CONTINUE:
842
-		return "continue";
843
-	case RKCIF_MONITOR_MODE_TRIGGER:
844
-		return "trigger";
845
-	case RKCIF_MONITOR_MODE_HOTPLUG:
846
-		return "hotplug";
847
-	default:
848
-		return "unknown";
849
-	}
850
-}
851
-
852
-static void rkcif_init_reset_timer(struct rkcif_hw *hw)
853
-{
854
-	struct device_node *node = hw->dev->of_node;
855
-	struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
856
-	u32 para[8];
857
-	int i;
858
-
859
-	if (!of_property_read_u32_array(node,
860
-					OF_CIF_MONITOR_PARA,
861
-					para,
862
-					CIF_MONITOR_PARA_NUM)) {
863
-		for (i = 0; i < CIF_MONITOR_PARA_NUM; i++) {
864
-			if (i == 0) {
865
-				hw_timer->monitor_mode = para[0];
866
-				dev_info(hw->dev,
867
-					 "%s: timer monitor mode:%s\n",
868
-					 __func__, rkcif_get_monitor_mode(hw_timer->monitor_mode));
869
-			}
870
-
871
-			if (i == 1) {
872
-				hw_timer->monitor_cycle = para[1];
873
-				dev_info(hw->dev,
874
-					 "timer of monitor cycle:%d\n",
875
-					 hw_timer->monitor_cycle);
876
-			}
877
-
878
-			if (i == 2) {
879
-				hw_timer->err_time_interval = para[2];
880
-				dev_info(hw->dev,
881
-					 "timer err time for keeping:%d ms\n",
882
-					 hw_timer->err_time_interval);
883
-			}
884
-
885
-			if (i == 3) {
886
-				hw_timer->err_ref_cnt = para[3];
887
-				dev_info(hw->dev,
888
-					 "timer err ref val for resetting:%d\n",
889
-					 hw_timer->err_ref_cnt);
890
-			}
891
-
892
-			if (i == 4) {
893
-				hw_timer->is_reset_by_user = para[4];
894
-				dev_info(hw->dev,
895
-					 "reset by user:%d\n",
896
-					 hw_timer->is_reset_by_user);
897
-			}
898
-		}
899
-	} else {
900
-		hw_timer->monitor_mode = RKCIF_MONITOR_MODE_IDLE;
901
-		hw_timer->err_time_interval = 0xffffffff;
902
-		hw_timer->monitor_cycle = 0xffffffff;
903
-		hw_timer->err_ref_cnt = 0xffffffff;
904
-		hw_timer->is_reset_by_user = 0;
905
-	}
906
-
907
-	hw_timer->is_running = false;
908
-	spin_lock_init(&hw_timer->timer_lock);
909
-	hw->reset_info.is_need_reset = 0;
910
-	timer_setup(&hw_timer->timer, rkcif_reset_watchdog_timer_handler, 0);
911
-}
912
-
9131255 static int rkcif_plat_hw_probe(struct platform_device *pdev)
9141256 {
9151257 	const struct of_device_id *match;
....@@ -921,6 +1263,8 @@
9211263 	const struct rkcif_hw_match_data *data;
9221264 	struct resource *res;
9231265 	int i, ret, irq;
1266
+	bool is_mem_reserved = false;
1267
+	struct notifier_block *notifier;
9241268 
9251269 	match = of_match_node(rkcif_plat_of_match, node);
9261270 	if (IS_ERR(match))
....@@ -949,10 +1293,7 @@
9491293 	cif_hw->irq = irq;
9501294 	cif_hw->match_data = data;
9511295 	cif_hw->chip_id = data->chip_id;
952
-	if (data->chip_id == CHIP_RK1808_CIF ||
953
-	    data->chip_id == CHIP_RV1126_CIF ||
954
-	    data->chip_id == CHIP_RV1126_CIF_LITE ||
955
-	    data->chip_id == CHIP_RK3568_CIF) {
1296
+	if (data->chip_id >= CHIP_RK1808_CIF) {
9561297 		res = platform_get_resource_byname(pdev,
9571298 						   IORESOURCE_MEM,
9581299 						   "cif_regs");
....@@ -972,6 +1313,11 @@
9721313 		cif_hw->base_addr = devm_ioremap_resource(dev, res);
9731314 		if (IS_ERR(cif_hw->base_addr))
9741315 			return PTR_ERR(cif_hw->base_addr);
1316
+	}
1317
+
1318
+	if (of_property_read_bool(np, "rockchip,android-usb-camerahal-enable")) {
1319
+		dev_info(dev, "config cif adapt to android usb camera hal!\n");
1320
+		cif_hw->adapt_to_usbcamerahal = true;
9751321 	}
9761322 
9771323 	cif_hw->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
....@@ -1003,25 +1349,32 @@
10031349 		if (data->rsts[i])
10041350 			rst = devm_reset_control_get(dev, data->rsts[i]);
10051351 		if (IS_ERR(rst)) {
1352
+			cif_hw->cif_rst[i] = NULL;
10061353 			dev_err(dev, "failed to get %s\n", data->rsts[i]);
1007
-			return PTR_ERR(rst);
1354
+		} else {
1355
+			cif_hw->cif_rst[i] = rst;
10081356 		}
1009
-		cif_hw->cif_rst[i] = rst;
10101357 	}
10111358 
10121359 	cif_hw->cif_regs = data->cif_regs;
10131360 
1014
-	cif_hw->iommu_en = is_iommu_enable(dev);
1015
-	if (!cif_hw->iommu_en) {
1016
-		ret = of_reserved_mem_device_init(dev);
1017
-		if (ret)
1018
-			dev_info(dev, "No reserved memory region assign to CIF\n");
1019
-	}
1361
+	cif_hw->is_dma_sg_ops = true;
1362
+	cif_hw->is_dma_contig = true;
1363
+	mutex_init(&cif_hw->dev_lock);
1364
+	spin_lock_init(&cif_hw->group_lock);
1365
+	atomic_set(&cif_hw->power_cnt, 0);
10201366 
1021
-	if (data->chip_id != CHIP_RK1808_CIF &&
1022
-	    data->chip_id != CHIP_RV1126_CIF &&
1023
-	    data->chip_id != CHIP_RV1126_CIF_LITE &&
1024
-	    data->chip_id != CHIP_RK3568_CIF) {
1367
+	cif_hw->iommu_en = is_iommu_enable(dev);
1368
+	ret = of_reserved_mem_device_init(dev);
1369
+	if (ret) {
1370
+		is_mem_reserved = false;
1371
+		dev_info(dev, "No reserved memory region assign to CIF\n");
1372
+	}
1373
+	if (cif_hw->iommu_en && !is_mem_reserved)
1374
+		cif_hw->is_dma_contig = false;
1375
+	cif_hw->mem_ops = &vb2_cma_sg_memops;
1376
+
1377
+	if (data->chip_id < CHIP_RK1808_CIF) {
10251378 		cif_dev = devm_kzalloc(dev, sizeof(*cif_dev), GFP_KERNEL);
10261379 		if (!cif_dev)
10271380 			return -ENOMEM;
....@@ -1036,20 +1389,20 @@
10361389 			return ret;
10371390 	}
10381391 
1039
-	rkcif_hw_soft_reset(cif_hw, true);
1040
-
10411392 	mutex_init(&cif_hw->dev_lock);
1042
-	spin_lock_init(&cif_hw->spin_lock);
10431393 
10441394 	pm_runtime_enable(&pdev->dev);
1045
-	rkcif_init_reset_timer(cif_hw);
10461395 
1047
-	if (data->chip_id == CHIP_RK1808_CIF ||
1048
-	    data->chip_id == CHIP_RV1126_CIF ||
1049
-	    data->chip_id == CHIP_RK3568_CIF) {
1396
+	if (data->chip_id >= CHIP_RK1808_CIF &&
1397
+	    data->chip_id != CHIP_RV1126_CIF_LITE) {
10501398 		platform_driver_register(&rkcif_plat_drv);
10511399 		platform_driver_register(&rkcif_subdev_driver);
10521400 	}
1401
+
1402
+	notifier = &cif_hw->reset_notifier;
1403
+	notifier->priority = 1;
1404
+	notifier->notifier_call = rkcif_reset_notifier;
1405
+	rkcif_csi2_register_notifier(notifier);
10531406 
10541407 	return 0;
10551408 }
....@@ -1063,19 +1416,53 @@
10631416 		rkcif_iommu_cleanup(cif_hw);
10641417 
10651418 	mutex_destroy(&cif_hw->dev_lock);
1066
-	if (cif_hw->chip_id != CHIP_RK1808_CIF &&
1067
-	    cif_hw->chip_id != CHIP_RV1126_CIF &&
1068
-	    cif_hw->chip_id != CHIP_RV1126_CIF_LITE &&
1069
-	    cif_hw->chip_id != CHIP_RK3568_CIF)
1419
+	if (cif_hw->chip_id < CHIP_RK1808_CIF)
10701420 		rkcif_plat_uninit(cif_hw->cif_dev[0]);
1071
-	del_timer_sync(&cif_hw->hw_timer.timer);
1421
+
1422
+	rkcif_csi2_unregister_notifier(&cif_hw->reset_notifier);
1423
+
10721424 	return 0;
1425
+}
1426
+
1427
+static void rkcif_hw_shutdown(struct platform_device *pdev)
1428
+{
1429
+	struct rkcif_hw *cif_hw = platform_get_drvdata(pdev);
1430
+	struct rkcif_device *cif_dev = NULL;
1431
+	int i = 0;
1432
+
1433
+	if (pm_runtime_get_if_in_use(&pdev->dev) <= 0)
1434
+		return;
1435
+
1436
+	if (cif_hw->chip_id == CHIP_RK3588_CIF ||
1437
+	    cif_hw->chip_id == CHIP_RV1106_CIF ||
1438
+	    cif_hw->chip_id == CHIP_RK3562_CIF) {
1439
+		write_cif_reg(cif_hw->base_addr, 0, 0);
1440
+	} else {
1441
+		for (i = 0; i < cif_hw->dev_num; i++) {
1442
+			cif_dev = cif_hw->cif_dev[i];
1443
+			if (atomic_read(&cif_dev->pipe.stream_cnt)) {
1444
+				if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
1445
+					rkcif_write_register(cif_dev,
1446
+							     CIF_REG_MIPI_LVDS_CTRL,
1447
+							     0);
1448
+				else
1449
+					rkcif_write_register(cif_dev,
1450
+							     CIF_REG_DVP_CTRL,
1451
+							     0);
1452
+			}
1453
+		}
1454
+	}
1455
+	if (cif_hw->irq > 0)
1456
+		disable_irq(cif_hw->irq);
1457
+	pm_runtime_put(&pdev->dev);
10731458 }
10741459 
10751460 static int __maybe_unused rkcif_runtime_suspend(struct device *dev)
10761461 {
10771462 	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
10781463 
1464
+	if (atomic_dec_return(&cif_hw->power_cnt))
1465
+		return 0;
10791466 	rkcif_disable_sys_clk(cif_hw);
10801467 
10811468 	return pinctrl_pm_select_sleep_state(dev);
....@@ -1086,17 +1473,18 @@
10861473 	struct rkcif_hw *cif_hw = dev_get_drvdata(dev);
10871474 	int ret;
10881475 
1476
+	if (atomic_inc_return(&cif_hw->power_cnt) > 1)
1477
+		return 0;
10891478 	ret = pinctrl_pm_select_default_state(dev);
10901479 	if (ret < 0)
10911480 		return ret;
10921481 	rkcif_enable_sys_clk(cif_hw);
1482
+	rkcif_hw_soft_reset(cif_hw, true);
10931483 
10941484 	return 0;
10951485 }
10961486 
10971487 static const struct dev_pm_ops rkcif_plat_pm_ops = {
1098
-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1099
-				pm_runtime_force_resume)
11001488 	SET_RUNTIME_PM_OPS(rkcif_runtime_suspend, rkcif_runtime_resume, NULL)
11011489 };
11021490 
....@@ -1108,9 +1496,10 @@
11081496 	},
11091497 	.probe = rkcif_plat_hw_probe,
11101498 	.remove = rkcif_plat_remove,
1499
+	.shutdown = rkcif_hw_shutdown,
11111500 };
11121501 
1113
-static int __init rk_cif_plat_drv_init(void)
1502
+int rk_cif_plat_drv_init(void)
11141503 {
11151504 	int ret;
11161505 
....@@ -1126,7 +1515,13 @@
11261515 	rkcif_csi2_plat_drv_exit();
11271516 }
11281517 
1518
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1519
+subsys_initcall(rk_cif_plat_drv_init);
1520
+#else
1521
+#if !defined(CONFIG_VIDEO_REVERSE_IMAGE)
11291522 module_init(rk_cif_plat_drv_init);
1523
+#endif
1524
+#endif
11301525 module_exit(rk_cif_plat_drv_exit);
11311526 
11321527 MODULE_AUTHOR("Rockchip Camera/ISP team");