forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-11 223293205a7265c8b02882461ba8996650048ade 
 kernel/drivers/gpu/drm/i915/gvt/gtt.c
....@@ -53,20 +53,28 @@
5353  */
5454 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
5555 {
56
-	if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
57
-			&& !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
58
-		gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
59
-				addr, size);
60
-		return false;
61
-	}
62
-	return true;
56
+	if (size == 0)
57
+		return vgpu_gmadr_is_valid(vgpu, addr);
58
+
59
+	if (vgpu_gmadr_is_aperture(vgpu, addr) &&
60
+	    vgpu_gmadr_is_aperture(vgpu, addr + size - 1))
61
+		return true;
62
+	else if (vgpu_gmadr_is_hidden(vgpu, addr) &&
63
+		 vgpu_gmadr_is_hidden(vgpu, addr + size - 1))
64
+		return true;
65
+
66
+	gvt_dbg_mm("Invalid ggtt range at 0x%llx, size: 0x%x\n",
67
+		     addr, size);
68
+	return false;
6369 }
6470 
6571 /* translate a guest gmadr to host gmadr */
6672 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
6773 {
68
-	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
69
-		 "invalid guest gmadr %llx\n", g_addr))
74
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
75
+
76
+	if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
77
+		     "invalid guest gmadr %llx\n", g_addr))
7078 		return -EACCES;
7179 
7280 	if (vgpu_gmadr_is_aperture(vgpu, g_addr))
....@@ -81,8 +89,10 @@
8189 /* translate a host gmadr to guest gmadr */
8290 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
8391 {
84
-	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
85
-		 "invalid host gmadr %llx\n", h_addr))
92
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
93
+
94
+	if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
95
+		     "invalid host gmadr %llx\n", h_addr))
8696 		return -EACCES;
8797 
8898 	if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
....@@ -269,24 +279,23 @@
269279 	return gtt_type_table[type].pse_entry_type;
270280 }
271281 
272
-static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
282
+static u64 read_pte64(struct i915_ggtt *ggtt, unsigned long index)
273283 {
274
-	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
284
+	void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
275285 
276286 	return readq(addr);
277287 }
278288 
279
-static void ggtt_invalidate(struct drm_i915_private *dev_priv)
289
+static void ggtt_invalidate(struct intel_gt *gt)
280290 {
281
-	mmio_hw_access_pre(dev_priv);
282
-	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
283
-	mmio_hw_access_post(dev_priv);
291
+	mmio_hw_access_pre(gt);
292
+	intel_uncore_write(gt->uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
293
+	mmio_hw_access_post(gt);
284294 }
285295 
286
-static void write_pte64(struct drm_i915_private *dev_priv,
287
-		unsigned long index, u64 pte)
296
+static void write_pte64(struct i915_ggtt *ggtt, unsigned long index, u64 pte)
288297 {
289
-	void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
298
+	void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
290299 
291300 	writeq(pte, addr);
292301 }
....@@ -309,7 +318,7 @@
309318 		if (WARN_ON(ret))
310319 			return ret;
311320 	} else if (!pt) {
312
-		e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
321
+		e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
313322 	} else {
314323 		e->val64 = *((u64 *)pt + index);
315324 	}
....@@ -334,7 +343,7 @@
334343 		if (WARN_ON(ret))
335344 			return ret;
336345 	} else if (!pt) {
337
-		write_pte64(vgpu->gvt->dev_priv, index, e->val64);
346
+		write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
338347 	} else {
339348 		*((u64 *)pt + index) = e->val64;
340349 	}
....@@ -728,7 +737,7 @@
728737 
729738 static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
730739 {
731
-	struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
740
+	struct device *kdev = &spt->vgpu->gvt->gt->i915->drm.pdev->dev;
732741 
733742 	trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
734743 
....@@ -750,14 +759,20 @@
750759 
751760 static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
752761 {
753
-	struct intel_vgpu_ppgtt_spt *spt;
762
+	struct intel_vgpu_ppgtt_spt *spt, *spn;
754763 	struct radix_tree_iter iter;
755
-	void **slot;
764
+	LIST_HEAD(all_spt);
765
+	void __rcu **slot;
756766 
767
+	rcu_read_lock();
757768 	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
758769 		spt = radix_tree_deref_slot(slot);
759
-		ppgtt_free_spt(spt);
770
+		list_move(&spt->post_shadow_list, &all_spt);
760771 	}
772
+	rcu_read_unlock();
773
+
774
+	list_for_each_entry_safe(spt, spn, &all_spt, post_shadow_list)
775
+		ppgtt_free_spt(spt);
761776 }
762777 
763778 static int ppgtt_handle_guest_write_page_table_bytes(
....@@ -805,9 +820,9 @@
805820 
806821 /* Allocate shadow page table without guest page. */
807822 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
808
-		struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type)
823
+		struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type)
809824 {
810
-	struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
825
+	struct device *kdev = &vgpu->gvt->gt->i915->drm.pdev->dev;
811826 	struct intel_vgpu_ppgtt_spt *spt = NULL;
812827 	dma_addr_t daddr;
813828 	int ret;
....@@ -855,7 +870,7 @@
855870 
856871 /* Allocate shadow page table associated with specific gfn. */
857872 static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
858
-		struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type,
873
+		struct intel_vgpu *vgpu, enum intel_gvt_gtt_type type,
859874 		unsigned long gfn, bool guest_pde_ips)
860875 {
861876 	struct intel_vgpu_ppgtt_spt *spt;
....@@ -928,15 +943,27 @@
928943 static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
929944 		struct intel_gvt_gtt_entry *e)
930945 {
946
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
931947 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
932948 	struct intel_vgpu_ppgtt_spt *s;
933
-	intel_gvt_gtt_type_t cur_pt_type;
949
+	enum intel_gvt_gtt_type cur_pt_type;
934950 
935951 	GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
936952 
937953 	if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
938954 		&& e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
939
-		cur_pt_type = get_next_pt_type(e->type) + 1;
955
+		cur_pt_type = get_next_pt_type(e->type);
956
+
957
+		if (!gtt_type_is_pt(cur_pt_type) ||
958
+				!gtt_type_is_pt(cur_pt_type + 1)) {
959
+			drm_WARN(&i915->drm, 1,
960
+				 "Invalid page table type, cur_pt_type is: %d\n",
961
+				 cur_pt_type);
962
+			return -EINVAL;
963
+		}
964
+
965
+		cur_pt_type += 1;
966
+
940967 		if (ops->get_pfn(e) ==
941968 			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
942969 			return 0;
....@@ -1023,7 +1050,7 @@
10231050 
10241051 static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
10251052 {
1026
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1053
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
10271054 
10281055 	if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
10291056 		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
....@@ -1070,6 +1097,11 @@
10701097 	} else {
10711098 		int type = get_next_pt_type(we->type);
10721099 
1100
+		if (!gtt_type_is_pt(type)) {
1101
+			ret = -EINVAL;
1102
+			goto err;
1103
+		}
1104
+
10731105 		spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
10741106 		if (IS_ERR(spt)) {
10751107 			ret = PTR_ERR(spt);
....@@ -1091,6 +1123,7 @@
10911123 
10921124 err_free_spt:
10931125 	ppgtt_free_spt(spt);
1126
+	spt = NULL;
10941127 err:
10951128 	gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
10961129 		     spt, we->val64, we->type);
....@@ -1113,6 +1146,10 @@
11131146 }
11141147 
11151148 /**
1149
+ * Check if can do 2M page
1150
+ * @vgpu: target vgpu
1151
+ * @entry: target pfn's gtt entry
1152
+ *
11161153  * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
11171154  * negtive if found err.
11181155  */
....@@ -1122,7 +1159,7 @@
11221159 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
11231160 	unsigned long pfn;
11241161 
1125
-	if (!HAS_PAGE_SIZES(vgpu->gvt->dev_priv, I915_GTT_PAGE_SIZE_2M))
1162
+	if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
11261163 		return 0;
11271164 
11281165 	pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
....@@ -1251,7 +1288,7 @@
12511288 		return -EINVAL;
12521289 	default:
12531290 		GEM_BUG_ON(1);
1254
-	};
1291
+	}
12551292 
12561293 	/* direct shadow */
12571294 	ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, page_size,
....@@ -1845,7 +1882,7 @@
18451882  * Zero on success, negative error code in pointer if failed.
18461883  */
18471884 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1848
-		intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
1885
+		enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
18491886 {
18501887 	struct intel_gvt *gvt = vgpu->gvt;
18511888 	struct intel_vgpu_mm *mm;
....@@ -1863,6 +1900,7 @@
18631900 
18641901 	INIT_LIST_HEAD(&mm->ppgtt_mm.list);
18651902 	INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
1903
+	INIT_LIST_HEAD(&mm->ppgtt_mm.link);
18661904 
18671905 	if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
18681906 		mm->ppgtt_mm.guest_pdps[0] = pdps[0];
....@@ -1878,7 +1916,11 @@
18781916 	}
18791917 
18801918 	list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1919
+
1920
+	mutex_lock(&gvt->gtt.ppgtt_mm_lock);
18811921 	list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1922
+	mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1923
+
18821924 	return mm;
18831925 }
18841926 
....@@ -1901,7 +1943,6 @@
19011943 		vgpu_free_mm(mm);
19021944 		return ERR_PTR(-ENOMEM);
19031945 	}
1904
-	mm->ggtt_mm.last_partial_off = -1UL;
19051946 
19061947 	return mm;
19071948 }
....@@ -1922,11 +1963,14 @@
19221963 
19231964 	if (mm->type == INTEL_GVT_MM_PPGTT) {
19241965 		list_del(&mm->ppgtt_mm.list);
1966
+
1967
+		mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
19251968 		list_del(&mm->ppgtt_mm.lru_list);
1969
+		mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1970
+
19261971 		invalidate_ppgtt_mm(mm);
19271972 	} else {
19281973 		vfree(mm->ggtt_mm.virtual_ggtt);
1929
-		mm->ggtt_mm.last_partial_off = -1UL;
19301974 	}
19311975 
19321976 	vgpu_free_mm(mm);
....@@ -1945,7 +1989,7 @@
19451989 
19461990 /**
19471991  * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1948
- * @vgpu: a vGPU
1992
+ * @mm: target vgpu mm
19491993  *
19501994  * This function is called when user wants to use a vGPU mm object. If this
19511995  * mm object hasn't been shadowed yet, the shadow will be populated at this
....@@ -1965,9 +2009,10 @@
19652009 		if (ret)
19662010 			return ret;
19672011 
2012
+		mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
19682013 		list_move_tail(&mm->ppgtt_mm.lru_list,
19692014 			       &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1970
-
2015
+		mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
19712016 	}
19722017 
19732018 	return 0;
....@@ -1978,6 +2023,8 @@
19782023 	struct intel_vgpu_mm *mm;
19792024 	struct list_head *pos, *n;
19802025 
2026
+	mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2027
+
19812028 	list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
19822029 		mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
19832030 
....@@ -1985,9 +2032,11 @@
19852032 			continue;
19862033 
19872034 		list_del_init(&mm->ppgtt_mm.lru_list);
2035
+		mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
19882036 		invalidate_ppgtt_mm(mm);
19892037 		return 1;
19902038 	}
2039
+	mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
19912040 	return 0;
19922041 }
19932042 
....@@ -2103,10 +2152,19 @@
21032152 	struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
21042153 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
21052154 	unsigned long index = off >> info->gtt_entry_size_shift;
2155
+	unsigned long gma;
21062156 	struct intel_gvt_gtt_entry e;
21072157 
21082158 	if (bytes != 4 && bytes != 8)
21092159 		return -EINVAL;
2160
+
2161
+	gma = index << I915_GTT_PAGE_SHIFT;
2162
+	if (!intel_gvt_ggtt_validate_range(vgpu,
2163
+					   gma, 1 << I915_GTT_PAGE_SHIFT)) {
2164
+		gvt_dbg_mm("read invalid ggtt at 0x%lx\n", gma);
2165
+		memset(p_data, 0, bytes);
2166
+		return 0;
2167
+	}
21102168 
21112169 	ggtt_get_guest_entry(ggtt_mm, &e, index);
21122170 	memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
....@@ -2165,6 +2223,8 @@
21652223 	struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
21662224 	dma_addr_t dma_addr;
21672225 	int ret;
2226
+	struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2227
+	bool partial_update = false;
21682228 
21692229 	if (bytes != 4 && bytes != 8)
21702230 		return -EINVAL;
....@@ -2175,68 +2235,57 @@
21752235 	if (!vgpu_gmadr_is_valid(vgpu, gma))
21762236 		return 0;
21772237 
2178
-	ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
2179
-
2238
+	e.type = GTT_TYPE_GGTT_PTE;
21802239 	memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
21812240 			bytes);
21822241 
21832242 	/* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2184
-	 * write, we assume the two 4 bytes writes are consecutive.
2185
-	 * Otherwise, we abort and report error
2243
+	 * write, save the first 4 bytes in a list and update virtual
2244
+	 * PTE. Only update shadow PTE when the second 4 bytes comes.
21862245 	 */
21872246 	if (bytes < info->gtt_entry_size) {
2188
-		if (ggtt_mm->ggtt_mm.last_partial_off == -1UL) {
2189
-			/* the first partial part*/
2190
-			ggtt_mm->ggtt_mm.last_partial_off = off;
2191
-			ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2192
-			return 0;
2193
-		} else if ((g_gtt_index ==
2194
-				(ggtt_mm->ggtt_mm.last_partial_off >>
2195
-				info->gtt_entry_size_shift)) &&
2196
-			(off !=	ggtt_mm->ggtt_mm.last_partial_off)) {
2197
-			/* the second partial part */
2247
+		bool found = false;
21982248 
2199
-			int last_off = ggtt_mm->ggtt_mm.last_partial_off &
2200
-				(info->gtt_entry_size - 1);
2249
+		list_for_each_entry_safe(pos, n,
2250
+				&ggtt_mm->ggtt_mm.partial_pte_list, list) {
2251
+			if (g_gtt_index == pos->offset >>
2252
+					info->gtt_entry_size_shift) {
2253
+				if (off != pos->offset) {
2254
+					/* the second partial part*/
2255
+					int last_off = pos->offset &
2256
+						(info->gtt_entry_size - 1);
22012257 
2202
-			memcpy((void *)&e.val64 + last_off,
2203
-				(void *)&ggtt_mm->ggtt_mm.last_partial_data +
2204
-				last_off, bytes);
2258
+					memcpy((void *)&e.val64 + last_off,
2259
+						(void *)&pos->data + last_off,
2260
+						bytes);
22052261 
2206
-			ggtt_mm->ggtt_mm.last_partial_off = -1UL;
2207
-		} else {
2208
-			int last_offset;
2262
+					list_del(&pos->list);
2263
+					kfree(pos);
2264
+					found = true;
2265
+					break;
2266
+				}
22092267 
2210
-			gvt_vgpu_err("failed to populate guest ggtt entry: abnormal ggtt entry write sequence, last_partial_off=%lx, offset=%x, bytes=%d, ggtt entry size=%d\n",
2211
-					ggtt_mm->ggtt_mm.last_partial_off, off,
2212
-					bytes, info->gtt_entry_size);
2268
+				/* update of the first partial part */
2269
+				pos->data = e.val64;
2270
+				ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2271
+				return 0;
2272
+			}
2273
+		}
22132274 
2214
-			/* set host ggtt entry to scratch page and clear
2215
-			 * virtual ggtt entry as not present for last
2216
-			 * partially write offset
2217
-			 */
2218
-			last_offset = ggtt_mm->ggtt_mm.last_partial_off &
2219
-					(~(info->gtt_entry_size - 1));
2220
-
2221
-			ggtt_get_host_entry(ggtt_mm, &m, last_offset);
2222
-			ggtt_invalidate_pte(vgpu, &m);
2223
-			ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2224
-			ops->clear_present(&m);
2225
-			ggtt_set_host_entry(ggtt_mm, &m, last_offset);
2226
-			ggtt_invalidate(gvt->dev_priv);
2227
-
2228
-			ggtt_get_guest_entry(ggtt_mm, &e, last_offset);
2229
-			ops->clear_present(&e);
2230
-			ggtt_set_guest_entry(ggtt_mm, &e, last_offset);
2231
-
2232
-			ggtt_mm->ggtt_mm.last_partial_off = off;
2233
-			ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2234
-
2235
-			return 0;
2275
+		if (!found) {
2276
+			/* the first partial part */
2277
+			partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2278
+			if (!partial_pte)
2279
+				return -ENOMEM;
2280
+			partial_pte->offset = off;
2281
+			partial_pte->data = e.val64;
2282
+			list_add_tail(&partial_pte->list,
2283
+				&ggtt_mm->ggtt_mm.partial_pte_list);
2284
+			partial_update = true;
22362285 		}
22372286 	}
22382287 
2239
-	if (ops->test_present(&e)) {
2288
+	if (!partial_update && (ops->test_present(&e))) {
22402289 		gfn = ops->get_pfn(&e);
22412290 		m.val64 = e.val64;
22422291 		m.type = e.type;
....@@ -2261,16 +2310,18 @@
22612310 		} else
22622311 			ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
22632312 	} else {
2264
-		ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
2265
-		ggtt_invalidate_pte(vgpu, &m);
22662313 		ops->set_pfn(&m, gvt->gtt.scratch_mfn);
22672314 		ops->clear_present(&m);
22682315 	}
22692316 
22702317 out:
2271
-	ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2272
-	ggtt_invalidate(gvt->dev_priv);
22732318 	ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2319
+
2320
+	ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2321
+	ggtt_invalidate_pte(vgpu, &e);
2322
+
2323
+	ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2324
+	ggtt_invalidate(gvt->gt);
22742325 	return 0;
22752326 }
22762327 
....@@ -2291,28 +2342,45 @@
22912342 {
22922343 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
22932344 	int ret;
2345
+	struct intel_vgpu_submission *s = &vgpu->submission;
2346
+	struct intel_engine_cs *engine;
2347
+	int i;
22942348 
22952349 	if (bytes != 4 && bytes != 8)
22962350 		return -EINVAL;
22972351 
22982352 	off -= info->gtt_start_offset;
22992353 	ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2354
+
2355
+	/* if ggtt of last submitted context is written,
2356
+	 * that context is probably got unpinned.
2357
+	 * Set last shadowed ctx to invalid.
2358
+	 */
2359
+	for_each_engine(engine, vgpu->gvt->gt, i) {
2360
+		if (!s->last_ctx[i].valid)
2361
+			continue;
2362
+
2363
+		if (s->last_ctx[i].lrca == (off >> info->gtt_entry_size_shift))
2364
+			s->last_ctx[i].valid = false;
2365
+	}
23002366 	return ret;
23012367 }
23022368 
23032369 static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2304
-		intel_gvt_gtt_type_t type)
2370
+		enum intel_gvt_gtt_type type)
23052371 {
2372
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
23062373 	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
23072374 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
23082375 	int page_entry_num = I915_GTT_PAGE_SIZE >>
23092376 				vgpu->gvt->device_info.gtt_entry_size_shift;
23102377 	void *scratch_pt;
23112378 	int i;
2312
-	struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2379
+	struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
23132380 	dma_addr_t daddr;
23142381 
2315
-	if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2382
+	if (drm_WARN_ON(&i915->drm,
2383
+			type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
23162384 		return -EINVAL;
23172385 
23182386 	scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
....@@ -2366,7 +2434,7 @@
23662434 static int release_scratch_page_tree(struct intel_vgpu *vgpu)
23672435 {
23682436 	int i;
2369
-	struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2437
+	struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
23702438 	dma_addr_t daddr;
23712439 
23722440 	for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
....@@ -2428,10 +2496,12 @@
24282496 
24292497 	intel_vgpu_reset_ggtt(vgpu, false);
24302498 
2499
+	INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2500
+
24312501 	return create_scratch_page_tree(vgpu);
24322502 }
24332503 
2434
-static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2504
+void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
24352505 {
24362506 	struct list_head *pos, *n;
24372507 	struct intel_vgpu_mm *mm;
....@@ -2452,6 +2522,15 @@
24522522 
24532523 static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
24542524 {
2525
+	struct intel_gvt_partial_pte *pos, *next;
2526
+
2527
+	list_for_each_entry_safe(pos, next,
2528
+				 &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2529
+				 list) {
2530
+		gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2531
+			pos->offset, pos->data);
2532
+		kfree(pos);
2533
+	}
24552534 	intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
24562535 	vgpu->gtt.ggtt_mm = NULL;
24572536 }
....@@ -2485,6 +2564,7 @@
24852564 	list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
24862565 		oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
24872566 		list_del(&oos_page->list);
2567
+		free_page((unsigned long)oos_page->mem);
24882568 		kfree(oos_page);
24892569 	}
24902570 }
....@@ -2505,6 +2585,12 @@
25052585 			ret = -ENOMEM;
25062586 			goto fail;
25072587 		}
2588
+		oos_page->mem = (void *)__get_free_pages(GFP_KERNEL, 0);
2589
+		if (!oos_page->mem) {
2590
+			ret = -ENOMEM;
2591
+			kfree(oos_page);
2592
+			goto fail;
2593
+		}
25082594 
25092595 		INIT_LIST_HEAD(&oos_page->list);
25102596 		INIT_LIST_HEAD(&oos_page->vm_list);
....@@ -2523,8 +2609,7 @@
25232609 /**
25242610  * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
25252611  * @vgpu: a vGPU
2526
- * @page_table_level: PPGTT page table level
2527
- * @root_entry: PPGTT page table root pointers
2612
+ * @pdps: pdp root array
25282613  *
25292614  * This function is used to find a PPGTT mm object from mm object pool
25302615  *
....@@ -2569,7 +2654,7 @@
25692654  * Zero on success, negative error code if failed.
25702655  */
25712656 struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
2572
-		intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2657
+		enum intel_gvt_gtt_type root_entry_type, u64 pdps[])
25732658 {
25742659 	struct intel_vgpu_mm *mm;
25752660 
....@@ -2621,7 +2706,7 @@
26212706 {
26222707 	int ret;
26232708 	void *page;
2624
-	struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2709
+	struct device *dev = &gvt->gt->i915->drm.pdev->dev;
26252710 	dma_addr_t daddr;
26262711 
26272712 	gvt_dbg_core("init gtt\n");
....@@ -2656,6 +2741,7 @@
26562741 		}
26572742 	}
26582743 	INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2744
+	mutex_init(&gvt->gtt.ppgtt_mm_lock);
26592745 	return 0;
26602746 }
26612747 
....@@ -2669,7 +2755,7 @@
26692755  */
26702756 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
26712757 {
2672
-	struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2758
+	struct device *dev = &gvt->gt->i915->drm.pdev->dev;
26732759 	dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
26742760 					I915_GTT_PAGE_SHIFT);
26752761 
....@@ -2696,7 +2782,9 @@
26962782 	list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
26972783 		mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
26982784 		if (mm->type == INTEL_GVT_MM_PPGTT) {
2785
+			mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
26992786 			list_del_init(&mm->ppgtt_mm.lru_list);
2787
+			mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
27002788 			if (mm->ppgtt_mm.shadowed)
27012789 				invalidate_ppgtt_mm(mm);
27022790 		}
....@@ -2715,7 +2803,6 @@
27152803 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
27162804 {
27172805 	struct intel_gvt *gvt = vgpu->gvt;
2718
-	struct drm_i915_private *dev_priv = gvt->dev_priv;
27192806 	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
27202807 	struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
27212808 	struct intel_gvt_gtt_entry old_entry;
....@@ -2745,7 +2832,7 @@
27452832 		ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
27462833 	}
27472834 
2748
-	ggtt_invalidate(dev_priv);
2835
+	ggtt_invalidate(gvt->gt);
27492836 }
27502837 
27512838 /**