kernel/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
.. .. @@ -7376,8 +7376,6 @@ 7376 7376 #define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e 7377 7377 #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2 7378 7378 7379 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x395d7380 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 27381 7379 7382 7380 // addressBlock: dce_dc_fmt4_dispdec 7383 7381 // base address: 0x2000