~hc/RK356X_SDK_RELEASE.git

..	..	@@ -56,10 +56,10 @@
56	56	"CounterHTOff": "0,1,2,3,4,5,6,7"
57	57	},
58	58	{
59		- "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
	59	+ "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
60	60	"EventCode": "0x24",
61	61	"Counter": "0,1,2,3",
62		- "UMask": "0x41",
	62	+ "UMask": "0xc1",
63	63	"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
64	64	"SampleAfterValue": "200003",
65	65	"BriefDescription": "Demand Data Read requests that hit L2 cache",
..	..	@@ -68,7 +68,7 @@
68	68	{
69	69	"EventCode": "0x24",
70	70	"Counter": "0,1,2,3",
71		- "UMask": "0x42",
	71	+ "UMask": "0xc2",
72	72	"EventName": "L2_RQSTS.RFO_HIT",
73	73	"SampleAfterValue": "200003",
74	74	"BriefDescription": "RFO requests that hit L2 cache.",
..	..	@@ -77,7 +77,7 @@
77	77	{
78	78	"EventCode": "0x24",
79	79	"Counter": "0,1,2,3",
80		- "UMask": "0x44",
	80	+ "UMask": "0xc4",
81	81	"EventName": "L2_RQSTS.CODE_RD_HIT",
82	82	"SampleAfterValue": "200003",
83	83	"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
..	..	@@ -87,7 +87,7 @@
87	87	"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
88	88	"EventCode": "0x24",
89	89	"Counter": "0,1,2,3",
90		- "UMask": "0x50",
	90	+ "UMask": "0xd0",
91	91	"EventName": "L2_RQSTS.L2_PF_HIT",
92	92	"SampleAfterValue": "200003",
93	93	"BriefDescription": "L2 prefetch requests that hit L2 cache",
..	..	@@ -771,2628 +771,2628 @@
771	771	"CounterHTOff": "0,1,2,3,4,5,6,7"
772	772	},
773	773	{
774		- "PublicDescription": "Counts demand data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	774	+ "PublicDescription": "Counts demand data reads have any response type.",
775	775	"EventCode": "0xB7, 0xBB",
776		- "MSRValue": "0x0000010001 ",
	776	+ "MSRValue": "0x0000010001",
777	777	"Counter": "0,1,2,3",
778	778	"UMask": "0x1",
779	779	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
780		- "MSRIndex": "0x1a6,0x1a7",
	780	+ "MSRIndex": "0x1a6, 0x1a7",
781	781	"SampleAfterValue": "100003",
782		- "BriefDescription": "Counts demand data reads that have any response type.",
	782	+ "BriefDescription": "Counts demand data reads have any response type.",
783	783	"Offcore": "1",
784	784	"CounterHTOff": "0,1,2,3"
785	785	},
786	786	{
787		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	787	+ "PublicDescription": "Counts demand data reads",
788	788	"EventCode": "0xB7, 0xBB",
789		- "MSRValue": "0x0080020001 ",
	789	+ "MSRValue": "0x0080020001",
790	790	"Counter": "0,1,2,3",
791	791	"UMask": "0x1",
792	792	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
793		- "MSRIndex": "0x1a6,0x1a7",
	793	+ "MSRIndex": "0x1a6, 0x1a7",
794	794	"SampleAfterValue": "100003",
795		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
	795	+ "BriefDescription": "Counts demand data reads",
796	796	"Offcore": "1",
797	797	"CounterHTOff": "0,1,2,3"
798	798	},
799	799	{
800		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	800	+ "PublicDescription": "Counts demand data reads",
801	801	"EventCode": "0xB7, 0xBB",
802		- "MSRValue": "0x0100020001 ",
	802	+ "MSRValue": "0x0100020001",
803	803	"Counter": "0,1,2,3",
804	804	"UMask": "0x1",
805	805	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
806		- "MSRIndex": "0x1a6,0x1a7",
	806	+ "MSRIndex": "0x1a6, 0x1a7",
807	807	"SampleAfterValue": "100003",
808		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	808	+ "BriefDescription": "Counts demand data reads",
809	809	"Offcore": "1",
810	810	"CounterHTOff": "0,1,2,3"
811	811	},
812	812	{
813		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	813	+ "PublicDescription": "Counts demand data reads",
814	814	"EventCode": "0xB7, 0xBB",
815		- "MSRValue": "0x0200020001 ",
	815	+ "MSRValue": "0x0200020001",
816	816	"Counter": "0,1,2,3",
817	817	"UMask": "0x1",
818	818	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
819		- "MSRIndex": "0x1a6,0x1a7",
	819	+ "MSRIndex": "0x1a6, 0x1a7",
820	820	"SampleAfterValue": "100003",
821		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
	821	+ "BriefDescription": "Counts demand data reads",
822	822	"Offcore": "1",
823	823	"CounterHTOff": "0,1,2,3"
824	824	},
825	825	{
826		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	826	+ "PublicDescription": "Counts demand data reads",
827	827	"EventCode": "0xB7, 0xBB",
828		- "MSRValue": "0x0400020001 ",
	828	+ "MSRValue": "0x0400020001",
829	829	"Counter": "0,1,2,3",
830	830	"UMask": "0x1",
831	831	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
832		- "MSRIndex": "0x1a6,0x1a7",
	832	+ "MSRIndex": "0x1a6, 0x1a7",
833	833	"SampleAfterValue": "100003",
834		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	834	+ "BriefDescription": "Counts demand data reads",
835	835	"Offcore": "1",
836	836	"CounterHTOff": "0,1,2,3"
837	837	},
838	838	{
839		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	839	+ "PublicDescription": "Counts demand data reads",
840	840	"EventCode": "0xB7, 0xBB",
841		- "MSRValue": "0x1000020001 ",
	841	+ "MSRValue": "0x1000020001",
842	842	"Counter": "0,1,2,3",
843	843	"UMask": "0x1",
844	844	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
845		- "MSRIndex": "0x1a6,0x1a7",
	845	+ "MSRIndex": "0x1a6, 0x1a7",
846	846	"SampleAfterValue": "100003",
847		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
	847	+ "BriefDescription": "Counts demand data reads",
848	848	"Offcore": "1",
849	849	"CounterHTOff": "0,1,2,3"
850	850	},
851	851	{
852		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	852	+ "PublicDescription": "Counts demand data reads",
853	853	"EventCode": "0xB7, 0xBB",
854		- "MSRValue": "0x3f80020001 ",
	854	+ "MSRValue": "0x3F80020001",
855	855	"Counter": "0,1,2,3",
856	856	"UMask": "0x1",
857	857	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
858		- "MSRIndex": "0x1a6,0x1a7",
	858	+ "MSRIndex": "0x1a6, 0x1a7",
859	859	"SampleAfterValue": "100003",
860		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
	860	+ "BriefDescription": "Counts demand data reads",
861	861	"Offcore": "1",
862	862	"CounterHTOff": "0,1,2,3"
863	863	},
864	864	{
865		- "PublicDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	865	+ "PublicDescription": "Counts demand data reads",
866	866	"EventCode": "0xB7, 0xBB",
867		- "MSRValue": "0x00803c0001 ",
	867	+ "MSRValue": "0x00803C0001",
868	868	"Counter": "0,1,2,3",
869	869	"UMask": "0x1",
870	870	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
871		- "MSRIndex": "0x1a6,0x1a7",
	871	+ "MSRIndex": "0x1a6, 0x1a7",
872	872	"SampleAfterValue": "100003",
873		- "BriefDescription": "Counts demand data reads that hit in the L3 with no details on snoop-related information.",
	873	+ "BriefDescription": "Counts demand data reads",
874	874	"Offcore": "1",
875	875	"CounterHTOff": "0,1,2,3"
876	876	},
877	877	{
878		- "PublicDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	878	+ "PublicDescription": "Counts demand data reads",
879	879	"EventCode": "0xB7, 0xBB",
880		- "MSRValue": "0x01003c0001 ",
	880	+ "MSRValue": "0x01003C0001",
881	881	"Counter": "0,1,2,3",
882	882	"UMask": "0x1",
883	883	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
884		- "MSRIndex": "0x1a6,0x1a7",
	884	+ "MSRIndex": "0x1a6, 0x1a7",
885	885	"SampleAfterValue": "100003",
886		- "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	886	+ "BriefDescription": "Counts demand data reads",
887	887	"Offcore": "1",
888	888	"CounterHTOff": "0,1,2,3"
889	889	},
890	890	{
891		- "PublicDescription": "Counts demand data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	891	+ "PublicDescription": "Counts demand data reads",
892	892	"EventCode": "0xB7, 0xBB",
893		- "MSRValue": "0x02003c0001 ",
	893	+ "MSRValue": "0x02003C0001",
894	894	"Counter": "0,1,2,3",
895	895	"UMask": "0x1",
896	896	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
897		- "MSRIndex": "0x1a6,0x1a7",
	897	+ "MSRIndex": "0x1a6, 0x1a7",
898	898	"SampleAfterValue": "100003",
899		- "BriefDescription": "Counts demand data reads that hit in the L3 with a snoop miss response.",
	899	+ "BriefDescription": "Counts demand data reads",
900	900	"Offcore": "1",
901	901	"CounterHTOff": "0,1,2,3"
902	902	},
903	903	{
904		- "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	904	+ "PublicDescription": "Counts demand data reads",
905	905	"EventCode": "0xB7, 0xBB",
906		- "MSRValue": "0x04003c0001 ",
	906	+ "MSRValue": "0x04003C0001",
907	907	"Counter": "0,1,2,3",
908	908	"UMask": "0x1",
909	909	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
910		- "MSRIndex": "0x1a6,0x1a7",
	910	+ "MSRIndex": "0x1a6, 0x1a7",
911	911	"SampleAfterValue": "100003",
912		- "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	912	+ "BriefDescription": "Counts demand data reads",
913	913	"Offcore": "1",
914	914	"CounterHTOff": "0,1,2,3"
915	915	},
916	916	{
917		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	917	+ "PublicDescription": "Counts demand data reads",
918	918	"EventCode": "0xB7, 0xBB",
919		- "MSRValue": "0x10003c0001 ",
	919	+ "MSRValue": "0x10003C0001",
920	920	"Counter": "0,1,2,3",
921	921	"UMask": "0x1",
922	922	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
923		- "MSRIndex": "0x1a6,0x1a7",
	923	+ "MSRIndex": "0x1a6, 0x1a7",
924	924	"SampleAfterValue": "100003",
925		- "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM",
	925	+ "BriefDescription": "Counts demand data reads",
926	926	"Offcore": "1",
927	927	"CounterHTOff": "0,1,2,3"
928	928	},
929	929	{
930		- "PublicDescription": "Counts demand data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	930	+ "PublicDescription": "Counts demand data reads",
931	931	"EventCode": "0xB7, 0xBB",
932		- "MSRValue": "0x3f803c0001 ",
	932	+ "MSRValue": "0x3F803C0001",
933	933	"Counter": "0,1,2,3",
934	934	"UMask": "0x1",
935	935	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
936		- "MSRIndex": "0x1a6,0x1a7",
	936	+ "MSRIndex": "0x1a6, 0x1a7",
937	937	"SampleAfterValue": "100003",
938		- "BriefDescription": "Counts demand data reads that hit in the L3.",
	938	+ "BriefDescription": "Counts demand data reads",
939	939	"Offcore": "1",
940	940	"CounterHTOff": "0,1,2,3"
941	941	},
942	942	{
943		- "PublicDescription": "Counts all demand data writes (RFOs) that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	943	+ "PublicDescription": "Counts all demand data writes (RFOs) have any response type.",
944	944	"EventCode": "0xB7, 0xBB",
945		- "MSRValue": "0x0000010002 ",
	945	+ "MSRValue": "0x0000010002",
946	946	"Counter": "0,1,2,3",
947	947	"UMask": "0x1",
948	948	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
949		- "MSRIndex": "0x1a6,0x1a7",
	949	+ "MSRIndex": "0x1a6, 0x1a7",
950	950	"SampleAfterValue": "100003",
951		- "BriefDescription": "Counts all demand data writes (RFOs) that have any response type.",
	951	+ "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
952	952	"Offcore": "1",
953	953	"CounterHTOff": "0,1,2,3"
954	954	},
955	955	{
956		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	956	+ "PublicDescription": "Counts all demand data writes (RFOs)",
957	957	"EventCode": "0xB7, 0xBB",
958		- "MSRValue": "0x00803c0002 ",
	958	+ "MSRValue": "0x00803C0002",
959	959	"Counter": "0,1,2,3",
960	960	"UMask": "0x1",
961	961	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
962		- "MSRIndex": "0x1a6,0x1a7",
	962	+ "MSRIndex": "0x1a6, 0x1a7",
963	963	"SampleAfterValue": "100003",
964		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with no details on snoop-related information.",
	964	+ "BriefDescription": "Counts all demand data writes (RFOs)",
965	965	"Offcore": "1",
966	966	"CounterHTOff": "0,1,2,3"
967	967	},
968	968	{
969		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	969	+ "PublicDescription": "Counts all demand data writes (RFOs)",
970	970	"EventCode": "0xB7, 0xBB",
971		- "MSRValue": "0x01003c0002 ",
	971	+ "MSRValue": "0x01003C0002",
972	972	"Counter": "0,1,2,3",
973	973	"UMask": "0x1",
974	974	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
975		- "MSRIndex": "0x1a6,0x1a7",
	975	+ "MSRIndex": "0x1a6, 0x1a7",
976	976	"SampleAfterValue": "100003",
977		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	977	+ "BriefDescription": "Counts all demand data writes (RFOs)",
978	978	"Offcore": "1",
979	979	"CounterHTOff": "0,1,2,3"
980	980	},
981	981	{
982		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	982	+ "PublicDescription": "Counts all demand data writes (RFOs)",
983	983	"EventCode": "0xB7, 0xBB",
984		- "MSRValue": "0x02003c0002 ",
	984	+ "MSRValue": "0x02003C0002",
985	985	"Counter": "0,1,2,3",
986	986	"UMask": "0x1",
987	987	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
988		- "MSRIndex": "0x1a6,0x1a7",
	988	+ "MSRIndex": "0x1a6, 0x1a7",
989	989	"SampleAfterValue": "100003",
990		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 with a snoop miss response.",
	990	+ "BriefDescription": "Counts all demand data writes (RFOs)",
991	991	"Offcore": "1",
992	992	"CounterHTOff": "0,1,2,3"
993	993	},
994	994	{
995		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	995	+ "PublicDescription": "Counts all demand data writes (RFOs)",
996	996	"EventCode": "0xB7, 0xBB",
997		- "MSRValue": "0x04003c0002 ",
	997	+ "MSRValue": "0x04003C0002",
998	998	"Counter": "0,1,2,3",
999	999	"UMask": "0x1",
1000	1000	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
1001		- "MSRIndex": "0x1a6,0x1a7",
	1001	+ "MSRIndex": "0x1a6, 0x1a7",
1002	1002	"SampleAfterValue": "100003",
1003		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1003	+ "BriefDescription": "Counts all demand data writes (RFOs)",
1004	1004	"Offcore": "1",
1005	1005	"CounterHTOff": "0,1,2,3"
1006	1006	},
1007	1007	{
1008		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1008	+ "PublicDescription": "Counts all demand data writes (RFOs)",
1009	1009	"EventCode": "0xB7, 0xBB",
1010		- "MSRValue": "0x10003c0002 ",
	1010	+ "MSRValue": "0x10003C0002",
1011	1011	"Counter": "0,1,2,3",
1012	1012	"UMask": "0x1",
1013	1013	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
1014		- "MSRIndex": "0x1a6,0x1a7",
	1014	+ "MSRIndex": "0x1a6, 0x1a7",
1015	1015	"SampleAfterValue": "100003",
1016		- "BriefDescription": "DEMAND_RFO & L3_HIT & SNOOP_HITM",
	1016	+ "BriefDescription": "Counts all demand data writes (RFOs)",
1017	1017	"Offcore": "1",
1018	1018	"CounterHTOff": "0,1,2,3"
1019	1019	},
1020	1020	{
1021		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1021	+ "PublicDescription": "Counts all demand data writes (RFOs)",
1022	1022	"EventCode": "0xB7, 0xBB",
1023		- "MSRValue": "0x3f803c0002 ",
	1023	+ "MSRValue": "0x3F803C0002",
1024	1024	"Counter": "0,1,2,3",
1025	1025	"UMask": "0x1",
1026	1026	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
1027		- "MSRIndex": "0x1a6,0x1a7",
	1027	+ "MSRIndex": "0x1a6, 0x1a7",
1028	1028	"SampleAfterValue": "100003",
1029		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3.",
	1029	+ "BriefDescription": "Counts all demand data writes (RFOs)",
1030	1030	"Offcore": "1",
1031	1031	"CounterHTOff": "0,1,2,3"
1032	1032	},
1033	1033	{
1034		- "PublicDescription": "Counts all demand code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1034	+ "PublicDescription": "Counts all demand code reads have any response type.",
1035	1035	"EventCode": "0xB7, 0xBB",
1036		- "MSRValue": "0x0000010004 ",
	1036	+ "MSRValue": "0x0000010004",
1037	1037	"Counter": "0,1,2,3",
1038	1038	"UMask": "0x1",
1039	1039	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
1040		- "MSRIndex": "0x1a6,0x1a7",
	1040	+ "MSRIndex": "0x1a6, 0x1a7",
1041	1041	"SampleAfterValue": "100003",
1042		- "BriefDescription": "Counts all demand code reads that have any response type.",
	1042	+ "BriefDescription": "Counts all demand code reads have any response type.",
1043	1043	"Offcore": "1",
1044	1044	"CounterHTOff": "0,1,2,3"
1045	1045	},
1046	1046	{
1047		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1047	+ "PublicDescription": "Counts all demand code reads",
1048	1048	"EventCode": "0xB7, 0xBB",
1049		- "MSRValue": "0x0080020004 ",
	1049	+ "MSRValue": "0x0080020004",
1050	1050	"Counter": "0,1,2,3",
1051	1051	"UMask": "0x1",
1052	1052	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
1053		- "MSRIndex": "0x1a6,0x1a7",
	1053	+ "MSRIndex": "0x1a6, 0x1a7",
1054	1054	"SampleAfterValue": "100003",
1055		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NONE",
	1055	+ "BriefDescription": "Counts all demand code reads",
1056	1056	"Offcore": "1",
1057	1057	"CounterHTOff": "0,1,2,3"
1058	1058	},
1059	1059	{
1060		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1060	+ "PublicDescription": "Counts all demand code reads",
1061	1061	"EventCode": "0xB7, 0xBB",
1062		- "MSRValue": "0x0100020004 ",
	1062	+ "MSRValue": "0x0100020004",
1063	1063	"Counter": "0,1,2,3",
1064	1064	"UMask": "0x1",
1065	1065	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1066		- "MSRIndex": "0x1a6,0x1a7",
	1066	+ "MSRIndex": "0x1a6, 0x1a7",
1067	1067	"SampleAfterValue": "100003",
1068		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1068	+ "BriefDescription": "Counts all demand code reads",
1069	1069	"Offcore": "1",
1070	1070	"CounterHTOff": "0,1,2,3"
1071	1071	},
1072	1072	{
1073		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1073	+ "PublicDescription": "Counts all demand code reads",
1074	1074	"EventCode": "0xB7, 0xBB",
1075		- "MSRValue": "0x0200020004 ",
	1075	+ "MSRValue": "0x0200020004",
1076	1076	"Counter": "0,1,2,3",
1077	1077	"UMask": "0x1",
1078	1078	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
1079		- "MSRIndex": "0x1a6,0x1a7",
	1079	+ "MSRIndex": "0x1a6, 0x1a7",
1080	1080	"SampleAfterValue": "100003",
1081		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_MISS",
	1081	+ "BriefDescription": "Counts all demand code reads",
1082	1082	"Offcore": "1",
1083	1083	"CounterHTOff": "0,1,2,3"
1084	1084	},
1085	1085	{
1086		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1086	+ "PublicDescription": "Counts all demand code reads",
1087	1087	"EventCode": "0xB7, 0xBB",
1088		- "MSRValue": "0x0400020004 ",
	1088	+ "MSRValue": "0x0400020004",
1089	1089	"Counter": "0,1,2,3",
1090	1090	"UMask": "0x1",
1091	1091	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1092		- "MSRIndex": "0x1a6,0x1a7",
	1092	+ "MSRIndex": "0x1a6, 0x1a7",
1093	1093	"SampleAfterValue": "100003",
1094		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1094	+ "BriefDescription": "Counts all demand code reads",
1095	1095	"Offcore": "1",
1096	1096	"CounterHTOff": "0,1,2,3"
1097	1097	},
1098	1098	{
1099		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1099	+ "PublicDescription": "Counts all demand code reads",
1100	1100	"EventCode": "0xB7, 0xBB",
1101		- "MSRValue": "0x1000020004 ",
	1101	+ "MSRValue": "0x1000020004",
1102	1102	"Counter": "0,1,2,3",
1103	1103	"UMask": "0x1",
1104	1104	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
1105		- "MSRIndex": "0x1a6,0x1a7",
	1105	+ "MSRIndex": "0x1a6, 0x1a7",
1106	1106	"SampleAfterValue": "100003",
1107		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_HITM",
	1107	+ "BriefDescription": "Counts all demand code reads",
1108	1108	"Offcore": "1",
1109	1109	"CounterHTOff": "0,1,2,3"
1110	1110	},
1111	1111	{
1112		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1112	+ "PublicDescription": "Counts all demand code reads",
1113	1113	"EventCode": "0xB7, 0xBB",
1114		- "MSRValue": "0x3f80020004 ",
	1114	+ "MSRValue": "0x3F80020004",
1115	1115	"Counter": "0,1,2,3",
1116	1116	"UMask": "0x1",
1117	1117	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
1118		- "MSRIndex": "0x1a6,0x1a7",
	1118	+ "MSRIndex": "0x1a6, 0x1a7",
1119	1119	"SampleAfterValue": "100003",
1120		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & ANY_SNOOP",
	1120	+ "BriefDescription": "Counts all demand code reads",
1121	1121	"Offcore": "1",
1122	1122	"CounterHTOff": "0,1,2,3"
1123	1123	},
1124	1124	{
1125		- "PublicDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1125	+ "PublicDescription": "Counts all demand code reads",
1126	1126	"EventCode": "0xB7, 0xBB",
1127		- "MSRValue": "0x00803c0004 ",
	1127	+ "MSRValue": "0x00803C0004",
1128	1128	"Counter": "0,1,2,3",
1129	1129	"UMask": "0x1",
1130	1130	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
1131		- "MSRIndex": "0x1a6,0x1a7",
	1131	+ "MSRIndex": "0x1a6, 0x1a7",
1132	1132	"SampleAfterValue": "100003",
1133		- "BriefDescription": "Counts all demand code reads that hit in the L3 with no details on snoop-related information.",
	1133	+ "BriefDescription": "Counts all demand code reads",
1134	1134	"Offcore": "1",
1135	1135	"CounterHTOff": "0,1,2,3"
1136	1136	},
1137	1137	{
1138		- "PublicDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1138	+ "PublicDescription": "Counts all demand code reads",
1139	1139	"EventCode": "0xB7, 0xBB",
1140		- "MSRValue": "0x01003c0004 ",
	1140	+ "MSRValue": "0x01003C0004",
1141	1141	"Counter": "0,1,2,3",
1142	1142	"UMask": "0x1",
1143	1143	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
1144		- "MSRIndex": "0x1a6,0x1a7",
	1144	+ "MSRIndex": "0x1a6, 0x1a7",
1145	1145	"SampleAfterValue": "100003",
1146		- "BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1146	+ "BriefDescription": "Counts all demand code reads",
1147	1147	"Offcore": "1",
1148	1148	"CounterHTOff": "0,1,2,3"
1149	1149	},
1150	1150	{
1151		- "PublicDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1151	+ "PublicDescription": "Counts all demand code reads",
1152	1152	"EventCode": "0xB7, 0xBB",
1153		- "MSRValue": "0x02003c0004 ",
	1153	+ "MSRValue": "0x02003C0004",
1154	1154	"Counter": "0,1,2,3",
1155	1155	"UMask": "0x1",
1156	1156	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
1157		- "MSRIndex": "0x1a6,0x1a7",
	1157	+ "MSRIndex": "0x1a6, 0x1a7",
1158	1158	"SampleAfterValue": "100003",
1159		- "BriefDescription": "Counts all demand code reads that hit in the L3 with a snoop miss response.",
	1159	+ "BriefDescription": "Counts all demand code reads",
1160	1160	"Offcore": "1",
1161	1161	"CounterHTOff": "0,1,2,3"
1162	1162	},
1163	1163	{
1164		- "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1164	+ "PublicDescription": "Counts all demand code reads",
1165	1165	"EventCode": "0xB7, 0xBB",
1166		- "MSRValue": "0x04003c0004 ",
	1166	+ "MSRValue": "0x04003C0004",
1167	1167	"Counter": "0,1,2,3",
1168	1168	"UMask": "0x1",
1169	1169	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
1170		- "MSRIndex": "0x1a6,0x1a7",
	1170	+ "MSRIndex": "0x1a6, 0x1a7",
1171	1171	"SampleAfterValue": "100003",
1172		- "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1172	+ "BriefDescription": "Counts all demand code reads",
1173	1173	"Offcore": "1",
1174	1174	"CounterHTOff": "0,1,2,3"
1175	1175	},
1176	1176	{
1177		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1177	+ "PublicDescription": "Counts all demand code reads",
1178	1178	"EventCode": "0xB7, 0xBB",
1179		- "MSRValue": "0x10003c0004 ",
	1179	+ "MSRValue": "0x10003C0004",
1180	1180	"Counter": "0,1,2,3",
1181	1181	"UMask": "0x1",
1182	1182	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
1183		- "MSRIndex": "0x1a6,0x1a7",
	1183	+ "MSRIndex": "0x1a6, 0x1a7",
1184	1184	"SampleAfterValue": "100003",
1185		- "BriefDescription": "DEMAND_CODE_RD & L3_HIT & SNOOP_HITM",
	1185	+ "BriefDescription": "Counts all demand code reads",
1186	1186	"Offcore": "1",
1187	1187	"CounterHTOff": "0,1,2,3"
1188	1188	},
1189	1189	{
1190		- "PublicDescription": "Counts all demand code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1190	+ "PublicDescription": "Counts all demand code reads",
1191	1191	"EventCode": "0xB7, 0xBB",
1192		- "MSRValue": "0x3f803c0004 ",
	1192	+ "MSRValue": "0x3F803C0004",
1193	1193	"Counter": "0,1,2,3",
1194	1194	"UMask": "0x1",
1195	1195	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
1196		- "MSRIndex": "0x1a6,0x1a7",
	1196	+ "MSRIndex": "0x1a6, 0x1a7",
1197	1197	"SampleAfterValue": "100003",
1198		- "BriefDescription": "Counts all demand code reads that hit in the L3.",
	1198	+ "BriefDescription": "Counts all demand code reads",
1199	1199	"Offcore": "1",
1200	1200	"CounterHTOff": "0,1,2,3"
1201	1201	},
1202	1202	{
1203		- "PublicDescription": "Counts writebacks (modified to exclusive) that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1203	+ "PublicDescription": "Counts writebacks (modified to exclusive) have any response type.",
1204	1204	"EventCode": "0xB7, 0xBB",
1205		- "MSRValue": "0x0000010008 ",
	1205	+ "MSRValue": "0x0000010008",
1206	1206	"Counter": "0,1,2,3",
1207	1207	"UMask": "0x1",
1208	1208	"EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
1209		- "MSRIndex": "0x1a6,0x1a7",
	1209	+ "MSRIndex": "0x1a6, 0x1a7",
1210	1210	"SampleAfterValue": "100003",
1211		- "BriefDescription": "Counts writebacks (modified to exclusive) that have any response type.",
	1211	+ "BriefDescription": "Counts writebacks (modified to exclusive) have any response type.",
1212	1212	"Offcore": "1",
1213	1213	"CounterHTOff": "0,1,2,3"
1214	1214	},
1215	1215	{
1216		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1216	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1217	1217	"EventCode": "0xB7, 0xBB",
1218		- "MSRValue": "0x0080020008 ",
	1218	+ "MSRValue": "0x0080020008",
1219	1219	"Counter": "0,1,2,3",
1220	1220	"UMask": "0x1",
1221	1221	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE",
1222		- "MSRIndex": "0x1a6,0x1a7",
	1222	+ "MSRIndex": "0x1a6, 0x1a7",
1223	1223	"SampleAfterValue": "100003",
1224		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NONE",
	1224	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1225	1225	"Offcore": "1",
1226	1226	"CounterHTOff": "0,1,2,3"
1227	1227	},
1228	1228	{
1229		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1229	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1230	1230	"EventCode": "0xB7, 0xBB",
1231		- "MSRValue": "0x0100020008 ",
	1231	+ "MSRValue": "0x0100020008",
1232	1232	"Counter": "0,1,2,3",
1233	1233	"UMask": "0x1",
1234	1234	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1235		- "MSRIndex": "0x1a6,0x1a7",
	1235	+ "MSRIndex": "0x1a6, 0x1a7",
1236	1236	"SampleAfterValue": "100003",
1237		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1237	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1238	1238	"Offcore": "1",
1239	1239	"CounterHTOff": "0,1,2,3"
1240	1240	},
1241	1241	{
1242		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1242	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1243	1243	"EventCode": "0xB7, 0xBB",
1244		- "MSRValue": "0x0200020008 ",
	1244	+ "MSRValue": "0x0200020008",
1245	1245	"Counter": "0,1,2,3",
1246	1246	"UMask": "0x1",
1247	1247	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS",
1248		- "MSRIndex": "0x1a6,0x1a7",
	1248	+ "MSRIndex": "0x1a6, 0x1a7",
1249	1249	"SampleAfterValue": "100003",
1250		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_MISS",
	1250	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1251	1251	"Offcore": "1",
1252	1252	"CounterHTOff": "0,1,2,3"
1253	1253	},
1254	1254	{
1255		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1255	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1256	1256	"EventCode": "0xB7, 0xBB",
1257		- "MSRValue": "0x0400020008 ",
	1257	+ "MSRValue": "0x0400020008",
1258	1258	"Counter": "0,1,2,3",
1259	1259	"UMask": "0x1",
1260	1260	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1261		- "MSRIndex": "0x1a6,0x1a7",
	1261	+ "MSRIndex": "0x1a6, 0x1a7",
1262	1262	"SampleAfterValue": "100003",
1263		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1263	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1264	1264	"Offcore": "1",
1265	1265	"CounterHTOff": "0,1,2,3"
1266	1266	},
1267	1267	{
1268		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1268	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1269	1269	"EventCode": "0xB7, 0xBB",
1270		- "MSRValue": "0x1000020008 ",
	1270	+ "MSRValue": "0x1000020008",
1271	1271	"Counter": "0,1,2,3",
1272	1272	"UMask": "0x1",
1273	1273	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM",
1274		- "MSRIndex": "0x1a6,0x1a7",
	1274	+ "MSRIndex": "0x1a6, 0x1a7",
1275	1275	"SampleAfterValue": "100003",
1276		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_HITM",
	1276	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1277	1277	"Offcore": "1",
1278	1278	"CounterHTOff": "0,1,2,3"
1279	1279	},
1280	1280	{
1281		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1281	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1282	1282	"EventCode": "0xB7, 0xBB",
1283		- "MSRValue": "0x3f80020008 ",
	1283	+ "MSRValue": "0x3F80020008",
1284	1284	"Counter": "0,1,2,3",
1285	1285	"UMask": "0x1",
1286	1286	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP",
1287		- "MSRIndex": "0x1a6,0x1a7",
	1287	+ "MSRIndex": "0x1a6, 0x1a7",
1288	1288	"SampleAfterValue": "100003",
1289		- "BriefDescription": "COREWB & SUPPLIER_NONE & ANY_SNOOP",
	1289	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1290	1290	"Offcore": "1",
1291	1291	"CounterHTOff": "0,1,2,3"
1292	1292	},
1293	1293	{
1294		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1294	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1295	1295	"EventCode": "0xB7, 0xBB",
1296		- "MSRValue": "0x00803c0008 ",
	1296	+ "MSRValue": "0x00803C0008",
1297	1297	"Counter": "0,1,2,3",
1298	1298	"UMask": "0x1",
1299	1299	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE",
1300		- "MSRIndex": "0x1a6,0x1a7",
	1300	+ "MSRIndex": "0x1a6, 0x1a7",
1301	1301	"SampleAfterValue": "100003",
1302		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with no details on snoop-related information.",
	1302	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1303	1303	"Offcore": "1",
1304	1304	"CounterHTOff": "0,1,2,3"
1305	1305	},
1306	1306	{
1307		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1307	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1308	1308	"EventCode": "0xB7, 0xBB",
1309		- "MSRValue": "0x01003c0008 ",
	1309	+ "MSRValue": "0x01003C0008",
1310	1310	"Counter": "0,1,2,3",
1311	1311	"UMask": "0x1",
1312	1312	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED",
1313		- "MSRIndex": "0x1a6,0x1a7",
	1313	+ "MSRIndex": "0x1a6, 0x1a7",
1314	1314	"SampleAfterValue": "100003",
1315		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1315	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1316	1316	"Offcore": "1",
1317	1317	"CounterHTOff": "0,1,2,3"
1318	1318	},
1319	1319	{
1320		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1320	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1321	1321	"EventCode": "0xB7, 0xBB",
1322		- "MSRValue": "0x02003c0008 ",
	1322	+ "MSRValue": "0x02003C0008",
1323	1323	"Counter": "0,1,2,3",
1324	1324	"UMask": "0x1",
1325	1325	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS",
1326		- "MSRIndex": "0x1a6,0x1a7",
	1326	+ "MSRIndex": "0x1a6, 0x1a7",
1327	1327	"SampleAfterValue": "100003",
1328		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 with a snoop miss response.",
	1328	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1329	1329	"Offcore": "1",
1330	1330	"CounterHTOff": "0,1,2,3"
1331	1331	},
1332	1332	{
1333		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1333	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1334	1334	"EventCode": "0xB7, 0xBB",
1335		- "MSRValue": "0x04003c0008 ",
	1335	+ "MSRValue": "0x04003C0008",
1336	1336	"Counter": "0,1,2,3",
1337	1337	"UMask": "0x1",
1338	1338	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD",
1339		- "MSRIndex": "0x1a6,0x1a7",
	1339	+ "MSRIndex": "0x1a6, 0x1a7",
1340	1340	"SampleAfterValue": "100003",
1341		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1341	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1342	1342	"Offcore": "1",
1343	1343	"CounterHTOff": "0,1,2,3"
1344	1344	},
1345	1345	{
1346		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1346	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1347	1347	"EventCode": "0xB7, 0xBB",
1348		- "MSRValue": "0x10003c0008 ",
	1348	+ "MSRValue": "0x10003C0008",
1349	1349	"Counter": "0,1,2,3",
1350	1350	"UMask": "0x1",
1351	1351	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM",
1352		- "MSRIndex": "0x1a6,0x1a7",
	1352	+ "MSRIndex": "0x1a6, 0x1a7",
1353	1353	"SampleAfterValue": "100003",
1354		- "BriefDescription": "COREWB & L3_HIT & SNOOP_HITM",
	1354	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1355	1355	"Offcore": "1",
1356	1356	"CounterHTOff": "0,1,2,3"
1357	1357	},
1358	1358	{
1359		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1359	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1360	1360	"EventCode": "0xB7, 0xBB",
1361		- "MSRValue": "0x3f803c0008 ",
	1361	+ "MSRValue": "0x3F803C0008",
1362	1362	"Counter": "0,1,2,3",
1363	1363	"UMask": "0x1",
1364	1364	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP",
1365		- "MSRIndex": "0x1a6,0x1a7",
	1365	+ "MSRIndex": "0x1a6, 0x1a7",
1366	1366	"SampleAfterValue": "100003",
1367		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3.",
	1367	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1368	1368	"Offcore": "1",
1369	1369	"CounterHTOff": "0,1,2,3"
1370	1370	},
1371	1371	{
1372		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1372	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
1373	1373	"EventCode": "0xB7, 0xBB",
1374		- "MSRValue": "0x0000010010 ",
	1374	+ "MSRValue": "0x0000010010",
1375	1375	"Counter": "0,1,2,3",
1376	1376	"UMask": "0x1",
1377	1377	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
1378		- "MSRIndex": "0x1a6,0x1a7",
	1378	+ "MSRIndex": "0x1a6, 0x1a7",
1379	1379	"SampleAfterValue": "100003",
1380		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that have any response type.",
	1380	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
1381	1381	"Offcore": "1",
1382	1382	"CounterHTOff": "0,1,2,3"
1383	1383	},
1384	1384	{
1385		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1385	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1386	1386	"EventCode": "0xB7, 0xBB",
1387		- "MSRValue": "0x0080020010 ",
	1387	+ "MSRValue": "0x0080020010",
1388	1388	"Counter": "0,1,2,3",
1389	1389	"UMask": "0x1",
1390	1390	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
1391		- "MSRIndex": "0x1a6,0x1a7",
	1391	+ "MSRIndex": "0x1a6, 0x1a7",
1392	1392	"SampleAfterValue": "100003",
1393		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
	1393	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1394	1394	"Offcore": "1",
1395	1395	"CounterHTOff": "0,1,2,3"
1396	1396	},
1397	1397	{
1398		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1398	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1399	1399	"EventCode": "0xB7, 0xBB",
1400		- "MSRValue": "0x0100020010 ",
	1400	+ "MSRValue": "0x0100020010",
1401	1401	"Counter": "0,1,2,3",
1402	1402	"UMask": "0x1",
1403	1403	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1404		- "MSRIndex": "0x1a6,0x1a7",
	1404	+ "MSRIndex": "0x1a6, 0x1a7",
1405	1405	"SampleAfterValue": "100003",
1406		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1406	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1407	1407	"Offcore": "1",
1408	1408	"CounterHTOff": "0,1,2,3"
1409	1409	},
1410	1410	{
1411		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1411	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1412	1412	"EventCode": "0xB7, 0xBB",
1413		- "MSRValue": "0x0200020010 ",
	1413	+ "MSRValue": "0x0200020010",
1414	1414	"Counter": "0,1,2,3",
1415	1415	"UMask": "0x1",
1416	1416	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
1417		- "MSRIndex": "0x1a6,0x1a7",
	1417	+ "MSRIndex": "0x1a6, 0x1a7",
1418	1418	"SampleAfterValue": "100003",
1419		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
	1419	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1420	1420	"Offcore": "1",
1421	1421	"CounterHTOff": "0,1,2,3"
1422	1422	},
1423	1423	{
1424		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1424	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1425	1425	"EventCode": "0xB7, 0xBB",
1426		- "MSRValue": "0x0400020010 ",
	1426	+ "MSRValue": "0x0400020010",
1427	1427	"Counter": "0,1,2,3",
1428	1428	"UMask": "0x1",
1429	1429	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1430		- "MSRIndex": "0x1a6,0x1a7",
	1430	+ "MSRIndex": "0x1a6, 0x1a7",
1431	1431	"SampleAfterValue": "100003",
1432		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1432	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1433	1433	"Offcore": "1",
1434	1434	"CounterHTOff": "0,1,2,3"
1435	1435	},
1436	1436	{
1437		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1437	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1438	1438	"EventCode": "0xB7, 0xBB",
1439		- "MSRValue": "0x1000020010 ",
	1439	+ "MSRValue": "0x1000020010",
1440	1440	"Counter": "0,1,2,3",
1441	1441	"UMask": "0x1",
1442	1442	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
1443		- "MSRIndex": "0x1a6,0x1a7",
	1443	+ "MSRIndex": "0x1a6, 0x1a7",
1444	1444	"SampleAfterValue": "100003",
1445		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
	1445	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1446	1446	"Offcore": "1",
1447	1447	"CounterHTOff": "0,1,2,3"
1448	1448	},
1449	1449	{
1450		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1450	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1451	1451	"EventCode": "0xB7, 0xBB",
1452		- "MSRValue": "0x3f80020010 ",
	1452	+ "MSRValue": "0x3F80020010",
1453	1453	"Counter": "0,1,2,3",
1454	1454	"UMask": "0x1",
1455	1455	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
1456		- "MSRIndex": "0x1a6,0x1a7",
	1456	+ "MSRIndex": "0x1a6, 0x1a7",
1457	1457	"SampleAfterValue": "100003",
1458		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
	1458	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1459	1459	"Offcore": "1",
1460	1460	"CounterHTOff": "0,1,2,3"
1461	1461	},
1462	1462	{
1463		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1463	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1464	1464	"EventCode": "0xB7, 0xBB",
1465		- "MSRValue": "0x00803c0010 ",
	1465	+ "MSRValue": "0x00803C0010",
1466	1466	"Counter": "0,1,2,3",
1467	1467	"UMask": "0x1",
1468	1468	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
1469		- "MSRIndex": "0x1a6,0x1a7",
	1469	+ "MSRIndex": "0x1a6, 0x1a7",
1470	1470	"SampleAfterValue": "100003",
1471		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with no details on snoop-related information.",
	1471	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1472	1472	"Offcore": "1",
1473	1473	"CounterHTOff": "0,1,2,3"
1474	1474	},
1475	1475	{
1476		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1476	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1477	1477	"EventCode": "0xB7, 0xBB",
1478		- "MSRValue": "0x01003c0010 ",
	1478	+ "MSRValue": "0x01003C0010",
1479	1479	"Counter": "0,1,2,3",
1480	1480	"UMask": "0x1",
1481	1481	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
1482		- "MSRIndex": "0x1a6,0x1a7",
	1482	+ "MSRIndex": "0x1a6, 0x1a7",
1483	1483	"SampleAfterValue": "100003",
1484		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1484	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1485	1485	"Offcore": "1",
1486	1486	"CounterHTOff": "0,1,2,3"
1487	1487	},
1488	1488	{
1489		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1489	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1490	1490	"EventCode": "0xB7, 0xBB",
1491		- "MSRValue": "0x02003c0010 ",
	1491	+ "MSRValue": "0x02003C0010",
1492	1492	"Counter": "0,1,2,3",
1493	1493	"UMask": "0x1",
1494	1494	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
1495		- "MSRIndex": "0x1a6,0x1a7",
	1495	+ "MSRIndex": "0x1a6, 0x1a7",
1496	1496	"SampleAfterValue": "100003",
1497		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 with a snoop miss response.",
	1497	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1498	1498	"Offcore": "1",
1499	1499	"CounterHTOff": "0,1,2,3"
1500	1500	},
1501	1501	{
1502		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1502	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1503	1503	"EventCode": "0xB7, 0xBB",
1504		- "MSRValue": "0x04003c0010 ",
	1504	+ "MSRValue": "0x04003C0010",
1505	1505	"Counter": "0,1,2,3",
1506	1506	"UMask": "0x1",
1507	1507	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
1508		- "MSRIndex": "0x1a6,0x1a7",
	1508	+ "MSRIndex": "0x1a6, 0x1a7",
1509	1509	"SampleAfterValue": "100003",
1510		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1510	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1511	1511	"Offcore": "1",
1512	1512	"CounterHTOff": "0,1,2,3"
1513	1513	},
1514	1514	{
1515		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1515	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1516	1516	"EventCode": "0xB7, 0xBB",
1517		- "MSRValue": "0x10003c0010 ",
	1517	+ "MSRValue": "0x10003C0010",
1518	1518	"Counter": "0,1,2,3",
1519	1519	"UMask": "0x1",
1520	1520	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
1521		- "MSRIndex": "0x1a6,0x1a7",
	1521	+ "MSRIndex": "0x1a6, 0x1a7",
1522	1522	"SampleAfterValue": "100003",
1523		- "BriefDescription": "PF_L2_DATA_RD & L3_HIT & SNOOP_HITM",
	1523	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1524	1524	"Offcore": "1",
1525	1525	"CounterHTOff": "0,1,2,3"
1526	1526	},
1527	1527	{
1528		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1528	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1529	1529	"EventCode": "0xB7, 0xBB",
1530		- "MSRValue": "0x3f803c0010 ",
	1530	+ "MSRValue": "0x3F803C0010",
1531	1531	"Counter": "0,1,2,3",
1532	1532	"UMask": "0x1",
1533	1533	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
1534		- "MSRIndex": "0x1a6,0x1a7",
	1534	+ "MSRIndex": "0x1a6, 0x1a7",
1535	1535	"SampleAfterValue": "100003",
1536		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3.",
	1536	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1537	1537	"Offcore": "1",
1538	1538	"CounterHTOff": "0,1,2,3"
1539	1539	},
1540	1540	{
1541		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1541	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
1542	1542	"EventCode": "0xB7, 0xBB",
1543		- "MSRValue": "0x0000010020 ",
	1543	+ "MSRValue": "0x0000010020",
1544	1544	"Counter": "0,1,2,3",
1545	1545	"UMask": "0x1",
1546	1546	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
1547		- "MSRIndex": "0x1a6,0x1a7",
	1547	+ "MSRIndex": "0x1a6, 0x1a7",
1548	1548	"SampleAfterValue": "100003",
1549		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that have any response type.",
	1549	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
1550	1550	"Offcore": "1",
1551	1551	"CounterHTOff": "0,1,2,3"
1552	1552	},
1553	1553	{
1554		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1554	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1555	1555	"EventCode": "0xB7, 0xBB",
1556		- "MSRValue": "0x0080020020 ",
	1556	+ "MSRValue": "0x0080020020",
1557	1557	"Counter": "0,1,2,3",
1558	1558	"UMask": "0x1",
1559	1559	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
1560		- "MSRIndex": "0x1a6,0x1a7",
	1560	+ "MSRIndex": "0x1a6, 0x1a7",
1561	1561	"SampleAfterValue": "100003",
1562		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NONE",
	1562	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1563	1563	"Offcore": "1",
1564	1564	"CounterHTOff": "0,1,2,3"
1565	1565	},
1566	1566	{
1567		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1567	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1568	1568	"EventCode": "0xB7, 0xBB",
1569		- "MSRValue": "0x0100020020 ",
	1569	+ "MSRValue": "0x0100020020",
1570	1570	"Counter": "0,1,2,3",
1571	1571	"UMask": "0x1",
1572	1572	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1573		- "MSRIndex": "0x1a6,0x1a7",
	1573	+ "MSRIndex": "0x1a6, 0x1a7",
1574	1574	"SampleAfterValue": "100003",
1575		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1575	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1576	1576	"Offcore": "1",
1577	1577	"CounterHTOff": "0,1,2,3"
1578	1578	},
1579	1579	{
1580		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1580	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1581	1581	"EventCode": "0xB7, 0xBB",
1582		- "MSRValue": "0x0200020020 ",
	1582	+ "MSRValue": "0x0200020020",
1583	1583	"Counter": "0,1,2,3",
1584	1584	"UMask": "0x1",
1585	1585	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
1586		- "MSRIndex": "0x1a6,0x1a7",
	1586	+ "MSRIndex": "0x1a6, 0x1a7",
1587	1587	"SampleAfterValue": "100003",
1588		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_MISS",
	1588	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1589	1589	"Offcore": "1",
1590	1590	"CounterHTOff": "0,1,2,3"
1591	1591	},
1592	1592	{
1593		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1593	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1594	1594	"EventCode": "0xB7, 0xBB",
1595		- "MSRValue": "0x0400020020 ",
	1595	+ "MSRValue": "0x0400020020",
1596	1596	"Counter": "0,1,2,3",
1597	1597	"UMask": "0x1",
1598	1598	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1599		- "MSRIndex": "0x1a6,0x1a7",
	1599	+ "MSRIndex": "0x1a6, 0x1a7",
1600	1600	"SampleAfterValue": "100003",
1601		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1601	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1602	1602	"Offcore": "1",
1603	1603	"CounterHTOff": "0,1,2,3"
1604	1604	},
1605	1605	{
1606		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1606	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1607	1607	"EventCode": "0xB7, 0xBB",
1608		- "MSRValue": "0x1000020020 ",
	1608	+ "MSRValue": "0x1000020020",
1609	1609	"Counter": "0,1,2,3",
1610	1610	"UMask": "0x1",
1611	1611	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM",
1612		- "MSRIndex": "0x1a6,0x1a7",
	1612	+ "MSRIndex": "0x1a6, 0x1a7",
1613	1613	"SampleAfterValue": "100003",
1614		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_HITM",
	1614	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1615	1615	"Offcore": "1",
1616	1616	"CounterHTOff": "0,1,2,3"
1617	1617	},
1618	1618	{
1619		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1619	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1620	1620	"EventCode": "0xB7, 0xBB",
1621		- "MSRValue": "0x3f80020020 ",
	1621	+ "MSRValue": "0x3F80020020",
1622	1622	"Counter": "0,1,2,3",
1623	1623	"UMask": "0x1",
1624	1624	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
1625		- "MSRIndex": "0x1a6,0x1a7",
	1625	+ "MSRIndex": "0x1a6, 0x1a7",
1626	1626	"SampleAfterValue": "100003",
1627		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & ANY_SNOOP",
	1627	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1628	1628	"Offcore": "1",
1629	1629	"CounterHTOff": "0,1,2,3"
1630	1630	},
1631	1631	{
1632		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1632	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1633	1633	"EventCode": "0xB7, 0xBB",
1634		- "MSRValue": "0x00803c0020 ",
	1634	+ "MSRValue": "0x00803C0020",
1635	1635	"Counter": "0,1,2,3",
1636	1636	"UMask": "0x1",
1637	1637	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE",
1638		- "MSRIndex": "0x1a6,0x1a7",
	1638	+ "MSRIndex": "0x1a6, 0x1a7",
1639	1639	"SampleAfterValue": "100003",
1640		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with no details on snoop-related information.",
	1640	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1641	1641	"Offcore": "1",
1642	1642	"CounterHTOff": "0,1,2,3"
1643	1643	},
1644	1644	{
1645		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1645	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1646	1646	"EventCode": "0xB7, 0xBB",
1647		- "MSRValue": "0x01003c0020 ",
	1647	+ "MSRValue": "0x01003C0020",
1648	1648	"Counter": "0,1,2,3",
1649	1649	"UMask": "0x1",
1650	1650	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
1651		- "MSRIndex": "0x1a6,0x1a7",
	1651	+ "MSRIndex": "0x1a6, 0x1a7",
1652	1652	"SampleAfterValue": "100003",
1653		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1653	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1654	1654	"Offcore": "1",
1655	1655	"CounterHTOff": "0,1,2,3"
1656	1656	},
1657	1657	{
1658		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1658	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1659	1659	"EventCode": "0xB7, 0xBB",
1660		- "MSRValue": "0x02003c0020 ",
	1660	+ "MSRValue": "0x02003C0020",
1661	1661	"Counter": "0,1,2,3",
1662	1662	"UMask": "0x1",
1663	1663	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS",
1664		- "MSRIndex": "0x1a6,0x1a7",
	1664	+ "MSRIndex": "0x1a6, 0x1a7",
1665	1665	"SampleAfterValue": "100003",
1666		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 with a snoop miss response.",
	1666	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1667	1667	"Offcore": "1",
1668	1668	"CounterHTOff": "0,1,2,3"
1669	1669	},
1670	1670	{
1671		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1671	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1672	1672	"EventCode": "0xB7, 0xBB",
1673		- "MSRValue": "0x04003c0020 ",
	1673	+ "MSRValue": "0x04003C0020",
1674	1674	"Counter": "0,1,2,3",
1675	1675	"UMask": "0x1",
1676	1676	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
1677		- "MSRIndex": "0x1a6,0x1a7",
	1677	+ "MSRIndex": "0x1a6, 0x1a7",
1678	1678	"SampleAfterValue": "100003",
1679		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1679	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1680	1680	"Offcore": "1",
1681	1681	"CounterHTOff": "0,1,2,3"
1682	1682	},
1683	1683	{
1684		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1684	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1685	1685	"EventCode": "0xB7, 0xBB",
1686		- "MSRValue": "0x10003c0020 ",
	1686	+ "MSRValue": "0x10003C0020",
1687	1687	"Counter": "0,1,2,3",
1688	1688	"UMask": "0x1",
1689	1689	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM",
1690		- "MSRIndex": "0x1a6,0x1a7",
	1690	+ "MSRIndex": "0x1a6, 0x1a7",
1691	1691	"SampleAfterValue": "100003",
1692		- "BriefDescription": "PF_L2_RFO & L3_HIT & SNOOP_HITM",
	1692	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1693	1693	"Offcore": "1",
1694	1694	"CounterHTOff": "0,1,2,3"
1695	1695	},
1696	1696	{
1697		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1697	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1698	1698	"EventCode": "0xB7, 0xBB",
1699		- "MSRValue": "0x3f803c0020 ",
	1699	+ "MSRValue": "0x3F803C0020",
1700	1700	"Counter": "0,1,2,3",
1701	1701	"UMask": "0x1",
1702	1702	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
1703		- "MSRIndex": "0x1a6,0x1a7",
	1703	+ "MSRIndex": "0x1a6, 0x1a7",
1704	1704	"SampleAfterValue": "100003",
1705		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3.",
	1705	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1706	1706	"Offcore": "1",
1707	1707	"CounterHTOff": "0,1,2,3"
1708	1708	},
1709	1709	{
1710		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1710	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.",
1711	1711	"EventCode": "0xB7, 0xBB",
1712		- "MSRValue": "0x0000010040 ",
	1712	+ "MSRValue": "0x0000010040",
1713	1713	"Counter": "0,1,2,3",
1714	1714	"UMask": "0x1",
1715	1715	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE",
1716		- "MSRIndex": "0x1a6,0x1a7",
	1716	+ "MSRIndex": "0x1a6, 0x1a7",
1717	1717	"SampleAfterValue": "100003",
1718		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that have any response type.",
	1718	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.",
1719	1719	"Offcore": "1",
1720	1720	"CounterHTOff": "0,1,2,3"
1721	1721	},
1722	1722	{
1723		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1723	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1724	1724	"EventCode": "0xB7, 0xBB",
1725		- "MSRValue": "0x0080020040 ",
	1725	+ "MSRValue": "0x0080020040",
1726	1726	"Counter": "0,1,2,3",
1727	1727	"UMask": "0x1",
1728	1728	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
1729		- "MSRIndex": "0x1a6,0x1a7",
	1729	+ "MSRIndex": "0x1a6, 0x1a7",
1730	1730	"SampleAfterValue": "100003",
1731		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NONE",
	1731	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1732	1732	"Offcore": "1",
1733	1733	"CounterHTOff": "0,1,2,3"
1734	1734	},
1735	1735	{
1736		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1736	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1737	1737	"EventCode": "0xB7, 0xBB",
1738		- "MSRValue": "0x0100020040 ",
	1738	+ "MSRValue": "0x0100020040",
1739	1739	"Counter": "0,1,2,3",
1740	1740	"UMask": "0x1",
1741	1741	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1742		- "MSRIndex": "0x1a6,0x1a7",
	1742	+ "MSRIndex": "0x1a6, 0x1a7",
1743	1743	"SampleAfterValue": "100003",
1744		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1744	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1745	1745	"Offcore": "1",
1746	1746	"CounterHTOff": "0,1,2,3"
1747	1747	},
1748	1748	{
1749		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1749	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1750	1750	"EventCode": "0xB7, 0xBB",
1751		- "MSRValue": "0x0200020040 ",
	1751	+ "MSRValue": "0x0200020040",
1752	1752	"Counter": "0,1,2,3",
1753	1753	"UMask": "0x1",
1754	1754	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
1755		- "MSRIndex": "0x1a6,0x1a7",
	1755	+ "MSRIndex": "0x1a6, 0x1a7",
1756	1756	"SampleAfterValue": "100003",
1757		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_MISS",
	1757	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1758	1758	"Offcore": "1",
1759	1759	"CounterHTOff": "0,1,2,3"
1760	1760	},
1761	1761	{
1762		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1762	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1763	1763	"EventCode": "0xB7, 0xBB",
1764		- "MSRValue": "0x0400020040 ",
	1764	+ "MSRValue": "0x0400020040",
1765	1765	"Counter": "0,1,2,3",
1766	1766	"UMask": "0x1",
1767	1767	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1768		- "MSRIndex": "0x1a6,0x1a7",
	1768	+ "MSRIndex": "0x1a6, 0x1a7",
1769	1769	"SampleAfterValue": "100003",
1770		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1770	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1771	1771	"Offcore": "1",
1772	1772	"CounterHTOff": "0,1,2,3"
1773	1773	},
1774	1774	{
1775		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1775	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1776	1776	"EventCode": "0xB7, 0xBB",
1777		- "MSRValue": "0x1000020040 ",
	1777	+ "MSRValue": "0x1000020040",
1778	1778	"Counter": "0,1,2,3",
1779	1779	"UMask": "0x1",
1780	1780	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
1781		- "MSRIndex": "0x1a6,0x1a7",
	1781	+ "MSRIndex": "0x1a6, 0x1a7",
1782	1782	"SampleAfterValue": "100003",
1783		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_HITM",
	1783	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1784	1784	"Offcore": "1",
1785	1785	"CounterHTOff": "0,1,2,3"
1786	1786	},
1787	1787	{
1788		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1788	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1789	1789	"EventCode": "0xB7, 0xBB",
1790		- "MSRValue": "0x3f80020040 ",
	1790	+ "MSRValue": "0x3F80020040",
1791	1791	"Counter": "0,1,2,3",
1792	1792	"UMask": "0x1",
1793	1793	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
1794		- "MSRIndex": "0x1a6,0x1a7",
	1794	+ "MSRIndex": "0x1a6, 0x1a7",
1795	1795	"SampleAfterValue": "100003",
1796		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & ANY_SNOOP",
	1796	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1797	1797	"Offcore": "1",
1798	1798	"CounterHTOff": "0,1,2,3"
1799	1799	},
1800	1800	{
1801		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1801	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1802	1802	"EventCode": "0xB7, 0xBB",
1803		- "MSRValue": "0x00803c0040 ",
	1803	+ "MSRValue": "0x00803C0040",
1804	1804	"Counter": "0,1,2,3",
1805	1805	"UMask": "0x1",
1806	1806	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE",
1807		- "MSRIndex": "0x1a6,0x1a7",
	1807	+ "MSRIndex": "0x1a6, 0x1a7",
1808	1808	"SampleAfterValue": "100003",
1809		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.",
	1809	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1810	1810	"Offcore": "1",
1811	1811	"CounterHTOff": "0,1,2,3"
1812	1812	},
1813	1813	{
1814		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1814	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1815	1815	"EventCode": "0xB7, 0xBB",
1816		- "MSRValue": "0x01003c0040 ",
	1816	+ "MSRValue": "0x01003C0040",
1817	1817	"Counter": "0,1,2,3",
1818	1818	"UMask": "0x1",
1819	1819	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
1820		- "MSRIndex": "0x1a6,0x1a7",
	1820	+ "MSRIndex": "0x1a6, 0x1a7",
1821	1821	"SampleAfterValue": "100003",
1822		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1822	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1823	1823	"Offcore": "1",
1824	1824	"CounterHTOff": "0,1,2,3"
1825	1825	},
1826	1826	{
1827		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1827	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1828	1828	"EventCode": "0xB7, 0xBB",
1829		- "MSRValue": "0x02003c0040 ",
	1829	+ "MSRValue": "0x02003C0040",
1830	1830	"Counter": "0,1,2,3",
1831	1831	"UMask": "0x1",
1832	1832	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS",
1833		- "MSRIndex": "0x1a6,0x1a7",
	1833	+ "MSRIndex": "0x1a6, 0x1a7",
1834	1834	"SampleAfterValue": "100003",
1835		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.",
	1835	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1836	1836	"Offcore": "1",
1837	1837	"CounterHTOff": "0,1,2,3"
1838	1838	},
1839	1839	{
1840		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1840	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1841	1841	"EventCode": "0xB7, 0xBB",
1842		- "MSRValue": "0x04003c0040 ",
	1842	+ "MSRValue": "0x04003C0040",
1843	1843	"Counter": "0,1,2,3",
1844	1844	"UMask": "0x1",
1845	1845	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
1846		- "MSRIndex": "0x1a6,0x1a7",
	1846	+ "MSRIndex": "0x1a6, 0x1a7",
1847	1847	"SampleAfterValue": "100003",
1848		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	1848	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1849	1849	"Offcore": "1",
1850	1850	"CounterHTOff": "0,1,2,3"
1851	1851	},
1852	1852	{
1853		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1853	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1854	1854	"EventCode": "0xB7, 0xBB",
1855		- "MSRValue": "0x10003c0040 ",
	1855	+ "MSRValue": "0x10003C0040",
1856	1856	"Counter": "0,1,2,3",
1857	1857	"UMask": "0x1",
1858	1858	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM",
1859		- "MSRIndex": "0x1a6,0x1a7",
	1859	+ "MSRIndex": "0x1a6, 0x1a7",
1860	1860	"SampleAfterValue": "100003",
1861		- "BriefDescription": "PF_L2_CODE_RD & L3_HIT & SNOOP_HITM",
	1861	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1862	1862	"Offcore": "1",
1863	1863	"CounterHTOff": "0,1,2,3"
1864	1864	},
1865	1865	{
1866		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1866	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1867	1867	"EventCode": "0xB7, 0xBB",
1868		- "MSRValue": "0x3f803c0040 ",
	1868	+ "MSRValue": "0x3F803C0040",
1869	1869	"Counter": "0,1,2,3",
1870	1870	"UMask": "0x1",
1871	1871	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP",
1872		- "MSRIndex": "0x1a6,0x1a7",
	1872	+ "MSRIndex": "0x1a6, 0x1a7",
1873	1873	"SampleAfterValue": "100003",
1874		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3.",
	1874	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1875	1875	"Offcore": "1",
1876	1876	"CounterHTOff": "0,1,2,3"
1877	1877	},
1878	1878	{
1879		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1879	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
1880	1880	"EventCode": "0xB7, 0xBB",
1881		- "MSRValue": "0x0000010080 ",
	1881	+ "MSRValue": "0x0000010080",
1882	1882	"Counter": "0,1,2,3",
1883	1883	"UMask": "0x1",
1884	1884	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
1885		- "MSRIndex": "0x1a6,0x1a7",
	1885	+ "MSRIndex": "0x1a6, 0x1a7",
1886	1886	"SampleAfterValue": "100003",
1887		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that have any response type.",
	1887	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
1888	1888	"Offcore": "1",
1889	1889	"CounterHTOff": "0,1,2,3"
1890	1890	},
1891	1891	{
1892		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1892	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1893	1893	"EventCode": "0xB7, 0xBB",
1894		- "MSRValue": "0x0080020080 ",
	1894	+ "MSRValue": "0x0080020080",
1895	1895	"Counter": "0,1,2,3",
1896	1896	"UMask": "0x1",
1897	1897	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
1898		- "MSRIndex": "0x1a6,0x1a7",
	1898	+ "MSRIndex": "0x1a6, 0x1a7",
1899	1899	"SampleAfterValue": "100003",
1900		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
	1900	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1901	1901	"Offcore": "1",
1902	1902	"CounterHTOff": "0,1,2,3"
1903	1903	},
1904	1904	{
1905		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1905	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1906	1906	"EventCode": "0xB7, 0xBB",
1907		- "MSRValue": "0x0100020080 ",
	1907	+ "MSRValue": "0x0100020080",
1908	1908	"Counter": "0,1,2,3",
1909	1909	"UMask": "0x1",
1910	1910	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1911		- "MSRIndex": "0x1a6,0x1a7",
	1911	+ "MSRIndex": "0x1a6, 0x1a7",
1912	1912	"SampleAfterValue": "100003",
1913		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	1913	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1914	1914	"Offcore": "1",
1915	1915	"CounterHTOff": "0,1,2,3"
1916	1916	},
1917	1917	{
1918		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1918	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1919	1919	"EventCode": "0xB7, 0xBB",
1920		- "MSRValue": "0x0200020080 ",
	1920	+ "MSRValue": "0x0200020080",
1921	1921	"Counter": "0,1,2,3",
1922	1922	"UMask": "0x1",
1923	1923	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
1924		- "MSRIndex": "0x1a6,0x1a7",
	1924	+ "MSRIndex": "0x1a6, 0x1a7",
1925	1925	"SampleAfterValue": "100003",
1926		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
	1926	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1927	1927	"Offcore": "1",
1928	1928	"CounterHTOff": "0,1,2,3"
1929	1929	},
1930	1930	{
1931		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1931	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1932	1932	"EventCode": "0xB7, 0xBB",
1933		- "MSRValue": "0x0400020080 ",
	1933	+ "MSRValue": "0x0400020080",
1934	1934	"Counter": "0,1,2,3",
1935	1935	"UMask": "0x1",
1936	1936	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1937		- "MSRIndex": "0x1a6,0x1a7",
	1937	+ "MSRIndex": "0x1a6, 0x1a7",
1938	1938	"SampleAfterValue": "100003",
1939		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	1939	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1940	1940	"Offcore": "1",
1941	1941	"CounterHTOff": "0,1,2,3"
1942	1942	},
1943	1943	{
1944		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1944	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1945	1945	"EventCode": "0xB7, 0xBB",
1946		- "MSRValue": "0x1000020080 ",
	1946	+ "MSRValue": "0x1000020080",
1947	1947	"Counter": "0,1,2,3",
1948	1948	"UMask": "0x1",
1949	1949	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
1950		- "MSRIndex": "0x1a6,0x1a7",
	1950	+ "MSRIndex": "0x1a6, 0x1a7",
1951	1951	"SampleAfterValue": "100003",
1952		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
	1952	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1953	1953	"Offcore": "1",
1954	1954	"CounterHTOff": "0,1,2,3"
1955	1955	},
1956	1956	{
1957		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1957	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1958	1958	"EventCode": "0xB7, 0xBB",
1959		- "MSRValue": "0x3f80020080 ",
	1959	+ "MSRValue": "0x3F80020080",
1960	1960	"Counter": "0,1,2,3",
1961	1961	"UMask": "0x1",
1962	1962	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
1963		- "MSRIndex": "0x1a6,0x1a7",
	1963	+ "MSRIndex": "0x1a6, 0x1a7",
1964	1964	"SampleAfterValue": "100003",
1965		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
	1965	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1966	1966	"Offcore": "1",
1967	1967	"CounterHTOff": "0,1,2,3"
1968	1968	},
1969	1969	{
1970		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1970	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1971	1971	"EventCode": "0xB7, 0xBB",
1972		- "MSRValue": "0x00803c0080 ",
	1972	+ "MSRValue": "0x00803C0080",
1973	1973	"Counter": "0,1,2,3",
1974	1974	"UMask": "0x1",
1975	1975	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
1976		- "MSRIndex": "0x1a6,0x1a7",
	1976	+ "MSRIndex": "0x1a6, 0x1a7",
1977	1977	"SampleAfterValue": "100003",
1978		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with no details on snoop-related information.",
	1978	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1979	1979	"Offcore": "1",
1980	1980	"CounterHTOff": "0,1,2,3"
1981	1981	},
1982	1982	{
1983		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1983	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1984	1984	"EventCode": "0xB7, 0xBB",
1985		- "MSRValue": "0x01003c0080 ",
	1985	+ "MSRValue": "0x01003C0080",
1986	1986	"Counter": "0,1,2,3",
1987	1987	"UMask": "0x1",
1988	1988	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
1989		- "MSRIndex": "0x1a6,0x1a7",
	1989	+ "MSRIndex": "0x1a6, 0x1a7",
1990	1990	"SampleAfterValue": "100003",
1991		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	1991	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1992	1992	"Offcore": "1",
1993	1993	"CounterHTOff": "0,1,2,3"
1994	1994	},
1995	1995	{
1996		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1996	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1997	1997	"EventCode": "0xB7, 0xBB",
1998		- "MSRValue": "0x02003c0080 ",
	1998	+ "MSRValue": "0x02003C0080",
1999	1999	"Counter": "0,1,2,3",
2000	2000	"UMask": "0x1",
2001	2001	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
2002		- "MSRIndex": "0x1a6,0x1a7",
	2002	+ "MSRIndex": "0x1a6, 0x1a7",
2003	2003	"SampleAfterValue": "100003",
2004		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 with a snoop miss response.",
	2004	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2005	2005	"Offcore": "1",
2006	2006	"CounterHTOff": "0,1,2,3"
2007	2007	},
2008	2008	{
2009		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2009	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2010	2010	"EventCode": "0xB7, 0xBB",
2011		- "MSRValue": "0x04003c0080 ",
	2011	+ "MSRValue": "0x04003C0080",
2012	2012	"Counter": "0,1,2,3",
2013	2013	"UMask": "0x1",
2014	2014	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
2015		- "MSRIndex": "0x1a6,0x1a7",
	2015	+ "MSRIndex": "0x1a6, 0x1a7",
2016	2016	"SampleAfterValue": "100003",
2017		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2017	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2018	2018	"Offcore": "1",
2019	2019	"CounterHTOff": "0,1,2,3"
2020	2020	},
2021	2021	{
2022		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2022	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2023	2023	"EventCode": "0xB7, 0xBB",
2024		- "MSRValue": "0x10003c0080 ",
	2024	+ "MSRValue": "0x10003C0080",
2025	2025	"Counter": "0,1,2,3",
2026	2026	"UMask": "0x1",
2027	2027	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",
2028		- "MSRIndex": "0x1a6,0x1a7",
	2028	+ "MSRIndex": "0x1a6, 0x1a7",
2029	2029	"SampleAfterValue": "100003",
2030		- "BriefDescription": "PF_L3_DATA_RD & L3_HIT & SNOOP_HITM",
	2030	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2031	2031	"Offcore": "1",
2032	2032	"CounterHTOff": "0,1,2,3"
2033	2033	},
2034	2034	{
2035		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2035	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2036	2036	"EventCode": "0xB7, 0xBB",
2037		- "MSRValue": "0x3f803c0080 ",
	2037	+ "MSRValue": "0x3F803C0080",
2038	2038	"Counter": "0,1,2,3",
2039	2039	"UMask": "0x1",
2040	2040	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
2041		- "MSRIndex": "0x1a6,0x1a7",
	2041	+ "MSRIndex": "0x1a6, 0x1a7",
2042	2042	"SampleAfterValue": "100003",
2043		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3.",
	2043	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
2044	2044	"Offcore": "1",
2045	2045	"CounterHTOff": "0,1,2,3"
2046	2046	},
2047	2047	{
2048		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2048	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
2049	2049	"EventCode": "0xB7, 0xBB",
2050		- "MSRValue": "0x0000010100 ",
	2050	+ "MSRValue": "0x0000010100",
2051	2051	"Counter": "0,1,2,3",
2052	2052	"UMask": "0x1",
2053	2053	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
2054		- "MSRIndex": "0x1a6,0x1a7",
	2054	+ "MSRIndex": "0x1a6, 0x1a7",
2055	2055	"SampleAfterValue": "100003",
2056		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",
	2056	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
2057	2057	"Offcore": "1",
2058	2058	"CounterHTOff": "0,1,2,3"
2059	2059	},
2060	2060	{
2061		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2061	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2062	2062	"EventCode": "0xB7, 0xBB",
2063		- "MSRValue": "0x0080020100 ",
	2063	+ "MSRValue": "0x0080020100",
2064	2064	"Counter": "0,1,2,3",
2065	2065	"UMask": "0x1",
2066	2066	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
2067		- "MSRIndex": "0x1a6,0x1a7",
	2067	+ "MSRIndex": "0x1a6, 0x1a7",
2068	2068	"SampleAfterValue": "100003",
2069		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NONE",
	2069	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2070	2070	"Offcore": "1",
2071	2071	"CounterHTOff": "0,1,2,3"
2072	2072	},
2073	2073	{
2074		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2074	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2075	2075	"EventCode": "0xB7, 0xBB",
2076		- "MSRValue": "0x0100020100 ",
	2076	+ "MSRValue": "0x0100020100",
2077	2077	"Counter": "0,1,2,3",
2078	2078	"UMask": "0x1",
2079	2079	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2080		- "MSRIndex": "0x1a6,0x1a7",
	2080	+ "MSRIndex": "0x1a6, 0x1a7",
2081	2081	"SampleAfterValue": "100003",
2082		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2082	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2083	2083	"Offcore": "1",
2084	2084	"CounterHTOff": "0,1,2,3"
2085	2085	},
2086	2086	{
2087		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2087	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2088	2088	"EventCode": "0xB7, 0xBB",
2089		- "MSRValue": "0x0200020100 ",
	2089	+ "MSRValue": "0x0200020100",
2090	2090	"Counter": "0,1,2,3",
2091	2091	"UMask": "0x1",
2092	2092	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
2093		- "MSRIndex": "0x1a6,0x1a7",
	2093	+ "MSRIndex": "0x1a6, 0x1a7",
2094	2094	"SampleAfterValue": "100003",
2095		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_MISS",
	2095	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2096	2096	"Offcore": "1",
2097	2097	"CounterHTOff": "0,1,2,3"
2098	2098	},
2099	2099	{
2100		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2100	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2101	2101	"EventCode": "0xB7, 0xBB",
2102		- "MSRValue": "0x0400020100 ",
	2102	+ "MSRValue": "0x0400020100",
2103	2103	"Counter": "0,1,2,3",
2104	2104	"UMask": "0x1",
2105	2105	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2106		- "MSRIndex": "0x1a6,0x1a7",
	2106	+ "MSRIndex": "0x1a6, 0x1a7",
2107	2107	"SampleAfterValue": "100003",
2108		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2108	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2109	2109	"Offcore": "1",
2110	2110	"CounterHTOff": "0,1,2,3"
2111	2111	},
2112	2112	{
2113		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2113	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2114	2114	"EventCode": "0xB7, 0xBB",
2115		- "MSRValue": "0x1000020100 ",
	2115	+ "MSRValue": "0x1000020100",
2116	2116	"Counter": "0,1,2,3",
2117	2117	"UMask": "0x1",
2118	2118	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",
2119		- "MSRIndex": "0x1a6,0x1a7",
	2119	+ "MSRIndex": "0x1a6, 0x1a7",
2120	2120	"SampleAfterValue": "100003",
2121		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_HITM",
	2121	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2122	2122	"Offcore": "1",
2123	2123	"CounterHTOff": "0,1,2,3"
2124	2124	},
2125	2125	{
2126		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2126	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2127	2127	"EventCode": "0xB7, 0xBB",
2128		- "MSRValue": "0x3f80020100 ",
	2128	+ "MSRValue": "0x3F80020100",
2129	2129	"Counter": "0,1,2,3",
2130	2130	"UMask": "0x1",
2131	2131	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
2132		- "MSRIndex": "0x1a6,0x1a7",
	2132	+ "MSRIndex": "0x1a6, 0x1a7",
2133	2133	"SampleAfterValue": "100003",
2134		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & ANY_SNOOP",
	2134	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2135	2135	"Offcore": "1",
2136	2136	"CounterHTOff": "0,1,2,3"
2137	2137	},
2138	2138	{
2139		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2139	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2140	2140	"EventCode": "0xB7, 0xBB",
2141		- "MSRValue": "0x00803c0100 ",
	2141	+ "MSRValue": "0x00803C0100",
2142	2142	"Counter": "0,1,2,3",
2143	2143	"UMask": "0x1",
2144	2144	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
2145		- "MSRIndex": "0x1a6,0x1a7",
	2145	+ "MSRIndex": "0x1a6, 0x1a7",
2146	2146	"SampleAfterValue": "100003",
2147		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with no details on snoop-related information.",
	2147	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2148	2148	"Offcore": "1",
2149	2149	"CounterHTOff": "0,1,2,3"
2150	2150	},
2151	2151	{
2152		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2152	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2153	2153	"EventCode": "0xB7, 0xBB",
2154		- "MSRValue": "0x01003c0100 ",
	2154	+ "MSRValue": "0x01003C0100",
2155	2155	"Counter": "0,1,2,3",
2156	2156	"UMask": "0x1",
2157	2157	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",
2158		- "MSRIndex": "0x1a6,0x1a7",
	2158	+ "MSRIndex": "0x1a6, 0x1a7",
2159	2159	"SampleAfterValue": "100003",
2160		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	2160	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2161	2161	"Offcore": "1",
2162	2162	"CounterHTOff": "0,1,2,3"
2163	2163	},
2164	2164	{
2165		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2165	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2166	2166	"EventCode": "0xB7, 0xBB",
2167		- "MSRValue": "0x02003c0100 ",
	2167	+ "MSRValue": "0x02003C0100",
2168	2168	"Counter": "0,1,2,3",
2169	2169	"UMask": "0x1",
2170	2170	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
2171		- "MSRIndex": "0x1a6,0x1a7",
	2171	+ "MSRIndex": "0x1a6, 0x1a7",
2172	2172	"SampleAfterValue": "100003",
2173		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 with a snoop miss response.",
	2173	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2174	2174	"Offcore": "1",
2175	2175	"CounterHTOff": "0,1,2,3"
2176	2176	},
2177	2177	{
2178		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2178	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2179	2179	"EventCode": "0xB7, 0xBB",
2180		- "MSRValue": "0x04003c0100 ",
	2180	+ "MSRValue": "0x04003C0100",
2181	2181	"Counter": "0,1,2,3",
2182	2182	"UMask": "0x1",
2183	2183	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
2184		- "MSRIndex": "0x1a6,0x1a7",
	2184	+ "MSRIndex": "0x1a6, 0x1a7",
2185	2185	"SampleAfterValue": "100003",
2186		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2186	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2187	2187	"Offcore": "1",
2188	2188	"CounterHTOff": "0,1,2,3"
2189	2189	},
2190	2190	{
2191		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2191	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2192	2192	"EventCode": "0xB7, 0xBB",
2193		- "MSRValue": "0x10003c0100 ",
	2193	+ "MSRValue": "0x10003C0100",
2194	2194	"Counter": "0,1,2,3",
2195	2195	"UMask": "0x1",
2196	2196	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",
2197		- "MSRIndex": "0x1a6,0x1a7",
	2197	+ "MSRIndex": "0x1a6, 0x1a7",
2198	2198	"SampleAfterValue": "100003",
2199		- "BriefDescription": "PF_L3_RFO & L3_HIT & SNOOP_HITM",
	2199	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2200	2200	"Offcore": "1",
2201	2201	"CounterHTOff": "0,1,2,3"
2202	2202	},
2203	2203	{
2204		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2204	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2205	2205	"EventCode": "0xB7, 0xBB",
2206		- "MSRValue": "0x3f803c0100 ",
	2206	+ "MSRValue": "0x3F803C0100",
2207	2207	"Counter": "0,1,2,3",
2208	2208	"UMask": "0x1",
2209	2209	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
2210		- "MSRIndex": "0x1a6,0x1a7",
	2210	+ "MSRIndex": "0x1a6, 0x1a7",
2211	2211	"SampleAfterValue": "100003",
2212		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3.",
	2212	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
2213	2213	"Offcore": "1",
2214	2214	"CounterHTOff": "0,1,2,3"
2215	2215	},
2216	2216	{
2217		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2217	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.",
2218	2218	"EventCode": "0xB7, 0xBB",
2219		- "MSRValue": "0x0000010200 ",
	2219	+ "MSRValue": "0x0000010200",
2220	2220	"Counter": "0,1,2,3",
2221	2221	"UMask": "0x1",
2222	2222	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE",
2223		- "MSRIndex": "0x1a6,0x1a7",
	2223	+ "MSRIndex": "0x1a6, 0x1a7",
2224	2224	"SampleAfterValue": "100003",
2225		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that have any response type.",
	2225	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.",
2226	2226	"Offcore": "1",
2227	2227	"CounterHTOff": "0,1,2,3"
2228	2228	},
2229	2229	{
2230		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2230	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2231	2231	"EventCode": "0xB7, 0xBB",
2232		- "MSRValue": "0x0080020200 ",
	2232	+ "MSRValue": "0x0080020200",
2233	2233	"Counter": "0,1,2,3",
2234	2234	"UMask": "0x1",
2235	2235	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
2236		- "MSRIndex": "0x1a6,0x1a7",
	2236	+ "MSRIndex": "0x1a6, 0x1a7",
2237	2237	"SampleAfterValue": "100003",
2238		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NONE",
	2238	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2239	2239	"Offcore": "1",
2240	2240	"CounterHTOff": "0,1,2,3"
2241	2241	},
2242	2242	{
2243		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2243	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2244	2244	"EventCode": "0xB7, 0xBB",
2245		- "MSRValue": "0x0100020200 ",
	2245	+ "MSRValue": "0x0100020200",
2246	2246	"Counter": "0,1,2,3",
2247	2247	"UMask": "0x1",
2248	2248	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2249		- "MSRIndex": "0x1a6,0x1a7",
	2249	+ "MSRIndex": "0x1a6, 0x1a7",
2250	2250	"SampleAfterValue": "100003",
2251		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2251	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2252	2252	"Offcore": "1",
2253	2253	"CounterHTOff": "0,1,2,3"
2254	2254	},
2255	2255	{
2256		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2256	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2257	2257	"EventCode": "0xB7, 0xBB",
2258		- "MSRValue": "0x0200020200 ",
	2258	+ "MSRValue": "0x0200020200",
2259	2259	"Counter": "0,1,2,3",
2260	2260	"UMask": "0x1",
2261	2261	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
2262		- "MSRIndex": "0x1a6,0x1a7",
	2262	+ "MSRIndex": "0x1a6, 0x1a7",
2263	2263	"SampleAfterValue": "100003",
2264		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_MISS",
	2264	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2265	2265	"Offcore": "1",
2266	2266	"CounterHTOff": "0,1,2,3"
2267	2267	},
2268	2268	{
2269		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2269	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2270	2270	"EventCode": "0xB7, 0xBB",
2271		- "MSRValue": "0x0400020200 ",
	2271	+ "MSRValue": "0x0400020200",
2272	2272	"Counter": "0,1,2,3",
2273	2273	"UMask": "0x1",
2274	2274	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2275		- "MSRIndex": "0x1a6,0x1a7",
	2275	+ "MSRIndex": "0x1a6, 0x1a7",
2276	2276	"SampleAfterValue": "100003",
2277		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2277	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2278	2278	"Offcore": "1",
2279	2279	"CounterHTOff": "0,1,2,3"
2280	2280	},
2281	2281	{
2282		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2282	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2283	2283	"EventCode": "0xB7, 0xBB",
2284		- "MSRValue": "0x1000020200 ",
	2284	+ "MSRValue": "0x1000020200",
2285	2285	"Counter": "0,1,2,3",
2286	2286	"UMask": "0x1",
2287	2287	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
2288		- "MSRIndex": "0x1a6,0x1a7",
	2288	+ "MSRIndex": "0x1a6, 0x1a7",
2289	2289	"SampleAfterValue": "100003",
2290		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_HITM",
	2290	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2291	2291	"Offcore": "1",
2292	2292	"CounterHTOff": "0,1,2,3"
2293	2293	},
2294	2294	{
2295		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2295	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2296	2296	"EventCode": "0xB7, 0xBB",
2297		- "MSRValue": "0x3f80020200 ",
	2297	+ "MSRValue": "0x3F80020200",
2298	2298	"Counter": "0,1,2,3",
2299	2299	"UMask": "0x1",
2300	2300	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
2301		- "MSRIndex": "0x1a6,0x1a7",
	2301	+ "MSRIndex": "0x1a6, 0x1a7",
2302	2302	"SampleAfterValue": "100003",
2303		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & ANY_SNOOP",
	2303	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2304	2304	"Offcore": "1",
2305	2305	"CounterHTOff": "0,1,2,3"
2306	2306	},
2307	2307	{
2308		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2308	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2309	2309	"EventCode": "0xB7, 0xBB",
2310		- "MSRValue": "0x00803c0200 ",
	2310	+ "MSRValue": "0x00803C0200",
2311	2311	"Counter": "0,1,2,3",
2312	2312	"UMask": "0x1",
2313	2313	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE",
2314		- "MSRIndex": "0x1a6,0x1a7",
	2314	+ "MSRIndex": "0x1a6, 0x1a7",
2315	2315	"SampleAfterValue": "100003",
2316		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with no details on snoop-related information.",
	2316	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2317	2317	"Offcore": "1",
2318	2318	"CounterHTOff": "0,1,2,3"
2319	2319	},
2320	2320	{
2321		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2321	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2322	2322	"EventCode": "0xB7, 0xBB",
2323		- "MSRValue": "0x01003c0200 ",
	2323	+ "MSRValue": "0x01003C0200",
2324	2324	"Counter": "0,1,2,3",
2325	2325	"UMask": "0x1",
2326	2326	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
2327		- "MSRIndex": "0x1a6,0x1a7",
	2327	+ "MSRIndex": "0x1a6, 0x1a7",
2328	2328	"SampleAfterValue": "100003",
2329		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	2329	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2330	2330	"Offcore": "1",
2331	2331	"CounterHTOff": "0,1,2,3"
2332	2332	},
2333	2333	{
2334		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2334	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2335	2335	"EventCode": "0xB7, 0xBB",
2336		- "MSRValue": "0x02003c0200 ",
	2336	+ "MSRValue": "0x02003C0200",
2337	2337	"Counter": "0,1,2,3",
2338	2338	"UMask": "0x1",
2339	2339	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS",
2340		- "MSRIndex": "0x1a6,0x1a7",
	2340	+ "MSRIndex": "0x1a6, 0x1a7",
2341	2341	"SampleAfterValue": "100003",
2342		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 with a snoop miss response.",
	2342	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2343	2343	"Offcore": "1",
2344	2344	"CounterHTOff": "0,1,2,3"
2345	2345	},
2346	2346	{
2347		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2347	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2348	2348	"EventCode": "0xB7, 0xBB",
2349		- "MSRValue": "0x04003c0200 ",
	2349	+ "MSRValue": "0x04003C0200",
2350	2350	"Counter": "0,1,2,3",
2351	2351	"UMask": "0x1",
2352	2352	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
2353		- "MSRIndex": "0x1a6,0x1a7",
	2353	+ "MSRIndex": "0x1a6, 0x1a7",
2354	2354	"SampleAfterValue": "100003",
2355		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2355	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2356	2356	"Offcore": "1",
2357	2357	"CounterHTOff": "0,1,2,3"
2358	2358	},
2359	2359	{
2360		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2360	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2361	2361	"EventCode": "0xB7, 0xBB",
2362		- "MSRValue": "0x10003c0200 ",
	2362	+ "MSRValue": "0x10003C0200",
2363	2363	"Counter": "0,1,2,3",
2364	2364	"UMask": "0x1",
2365	2365	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM",
2366		- "MSRIndex": "0x1a6,0x1a7",
	2366	+ "MSRIndex": "0x1a6, 0x1a7",
2367	2367	"SampleAfterValue": "100003",
2368		- "BriefDescription": "PF_L3_CODE_RD & L3_HIT & SNOOP_HITM",
	2368	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2369	2369	"Offcore": "1",
2370	2370	"CounterHTOff": "0,1,2,3"
2371	2371	},
2372	2372	{
2373		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2373	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2374	2374	"EventCode": "0xB7, 0xBB",
2375		- "MSRValue": "0x3f803c0200 ",
	2375	+ "MSRValue": "0x3F803C0200",
2376	2376	"Counter": "0,1,2,3",
2377	2377	"UMask": "0x1",
2378	2378	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP",
2379		- "MSRIndex": "0x1a6,0x1a7",
	2379	+ "MSRIndex": "0x1a6, 0x1a7",
2380	2380	"SampleAfterValue": "100003",
2381		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3.",
	2381	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2382	2382	"Offcore": "1",
2383	2383	"CounterHTOff": "0,1,2,3"
2384	2384	},
2385	2385	{
2386		- "PublicDescription": "Counts any other requests that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2386	+ "PublicDescription": "Counts any other requests have any response type.",
2387	2387	"EventCode": "0xB7, 0xBB",
2388		- "MSRValue": "0x0000018000 ",
	2388	+ "MSRValue": "0x0000018000",
2389	2389	"Counter": "0,1,2,3",
2390	2390	"UMask": "0x1",
2391	2391	"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
2392		- "MSRIndex": "0x1a6,0x1a7",
	2392	+ "MSRIndex": "0x1a6, 0x1a7",
2393	2393	"SampleAfterValue": "100003",
2394		- "BriefDescription": "Counts any other requests that have any response type.",
	2394	+ "BriefDescription": "Counts any other requests have any response type.",
2395	2395	"Offcore": "1",
2396	2396	"CounterHTOff": "0,1,2,3"
2397	2397	},
2398	2398	{
2399		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2399	+ "PublicDescription": "Counts any other requests",
2400	2400	"EventCode": "0xB7, 0xBB",
2401		- "MSRValue": "0x0080028000 ",
	2401	+ "MSRValue": "0x0080028000",
2402	2402	"Counter": "0,1,2,3",
2403	2403	"UMask": "0x1",
2404	2404	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
2405		- "MSRIndex": "0x1a6,0x1a7",
	2405	+ "MSRIndex": "0x1a6, 0x1a7",
2406	2406	"SampleAfterValue": "100003",
2407		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NONE",
	2407	+ "BriefDescription": "Counts any other requests",
2408	2408	"Offcore": "1",
2409	2409	"CounterHTOff": "0,1,2,3"
2410	2410	},
2411	2411	{
2412		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2412	+ "PublicDescription": "Counts any other requests",
2413	2413	"EventCode": "0xB7, 0xBB",
2414		- "MSRValue": "0x0100028000 ",
	2414	+ "MSRValue": "0x0100028000",
2415	2415	"Counter": "0,1,2,3",
2416	2416	"UMask": "0x1",
2417	2417	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2418		- "MSRIndex": "0x1a6,0x1a7",
	2418	+ "MSRIndex": "0x1a6, 0x1a7",
2419	2419	"SampleAfterValue": "100003",
2420		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2420	+ "BriefDescription": "Counts any other requests",
2421	2421	"Offcore": "1",
2422	2422	"CounterHTOff": "0,1,2,3"
2423	2423	},
2424	2424	{
2425		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2425	+ "PublicDescription": "Counts any other requests",
2426	2426	"EventCode": "0xB7, 0xBB",
2427		- "MSRValue": "0x0200028000 ",
	2427	+ "MSRValue": "0x0200028000",
2428	2428	"Counter": "0,1,2,3",
2429	2429	"UMask": "0x1",
2430	2430	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
2431		- "MSRIndex": "0x1a6,0x1a7",
	2431	+ "MSRIndex": "0x1a6, 0x1a7",
2432	2432	"SampleAfterValue": "100003",
2433		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_MISS",
	2433	+ "BriefDescription": "Counts any other requests",
2434	2434	"Offcore": "1",
2435	2435	"CounterHTOff": "0,1,2,3"
2436	2436	},
2437	2437	{
2438		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2438	+ "PublicDescription": "Counts any other requests",
2439	2439	"EventCode": "0xB7, 0xBB",
2440		- "MSRValue": "0x0400028000 ",
	2440	+ "MSRValue": "0x0400028000",
2441	2441	"Counter": "0,1,2,3",
2442	2442	"UMask": "0x1",
2443	2443	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2444		- "MSRIndex": "0x1a6,0x1a7",
	2444	+ "MSRIndex": "0x1a6, 0x1a7",
2445	2445	"SampleAfterValue": "100003",
2446		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2446	+ "BriefDescription": "Counts any other requests",
2447	2447	"Offcore": "1",
2448	2448	"CounterHTOff": "0,1,2,3"
2449	2449	},
2450	2450	{
2451		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2451	+ "PublicDescription": "Counts any other requests",
2452	2452	"EventCode": "0xB7, 0xBB",
2453		- "MSRValue": "0x1000028000 ",
	2453	+ "MSRValue": "0x1000028000",
2454	2454	"Counter": "0,1,2,3",
2455	2455	"UMask": "0x1",
2456	2456	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
2457		- "MSRIndex": "0x1a6,0x1a7",
	2457	+ "MSRIndex": "0x1a6, 0x1a7",
2458	2458	"SampleAfterValue": "100003",
2459		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_HITM",
	2459	+ "BriefDescription": "Counts any other requests",
2460	2460	"Offcore": "1",
2461	2461	"CounterHTOff": "0,1,2,3"
2462	2462	},
2463	2463	{
2464		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2464	+ "PublicDescription": "Counts any other requests",
2465	2465	"EventCode": "0xB7, 0xBB",
2466		- "MSRValue": "0x3f80028000 ",
	2466	+ "MSRValue": "0x3F80028000",
2467	2467	"Counter": "0,1,2,3",
2468	2468	"UMask": "0x1",
2469	2469	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
2470		- "MSRIndex": "0x1a6,0x1a7",
	2470	+ "MSRIndex": "0x1a6, 0x1a7",
2471	2471	"SampleAfterValue": "100003",
2472		- "BriefDescription": "OTHER & SUPPLIER_NONE & ANY_SNOOP",
	2472	+ "BriefDescription": "Counts any other requests",
2473	2473	"Offcore": "1",
2474	2474	"CounterHTOff": "0,1,2,3"
2475	2475	},
2476	2476	{
2477		- "PublicDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2477	+ "PublicDescription": "Counts any other requests",
2478	2478	"EventCode": "0xB7, 0xBB",
2479		- "MSRValue": "0x00803c8000 ",
	2479	+ "MSRValue": "0x00803C8000",
2480	2480	"Counter": "0,1,2,3",
2481	2481	"UMask": "0x1",
2482	2482	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
2483		- "MSRIndex": "0x1a6,0x1a7",
	2483	+ "MSRIndex": "0x1a6, 0x1a7",
2484	2484	"SampleAfterValue": "100003",
2485		- "BriefDescription": "Counts any other requests that hit in the L3 with no details on snoop-related information.",
	2485	+ "BriefDescription": "Counts any other requests",
2486	2486	"Offcore": "1",
2487	2487	"CounterHTOff": "0,1,2,3"
2488	2488	},
2489	2489	{
2490		- "PublicDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2490	+ "PublicDescription": "Counts any other requests",
2491	2491	"EventCode": "0xB7, 0xBB",
2492		- "MSRValue": "0x01003c8000 ",
	2492	+ "MSRValue": "0x01003C8000",
2493	2493	"Counter": "0,1,2,3",
2494	2494	"UMask": "0x1",
2495	2495	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
2496		- "MSRIndex": "0x1a6,0x1a7",
	2496	+ "MSRIndex": "0x1a6, 0x1a7",
2497	2497	"SampleAfterValue": "100003",
2498		- "BriefDescription": "Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	2498	+ "BriefDescription": "Counts any other requests",
2499	2499	"Offcore": "1",
2500	2500	"CounterHTOff": "0,1,2,3"
2501	2501	},
2502	2502	{
2503		- "PublicDescription": "Counts any other requests that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2503	+ "PublicDescription": "Counts any other requests",
2504	2504	"EventCode": "0xB7, 0xBB",
2505		- "MSRValue": "0x02003c8000 ",
	2505	+ "MSRValue": "0x02003C8000",
2506	2506	"Counter": "0,1,2,3",
2507	2507	"UMask": "0x1",
2508	2508	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
2509		- "MSRIndex": "0x1a6,0x1a7",
	2509	+ "MSRIndex": "0x1a6, 0x1a7",
2510	2510	"SampleAfterValue": "100003",
2511		- "BriefDescription": "Counts any other requests that hit in the L3 with a snoop miss response.",
	2511	+ "BriefDescription": "Counts any other requests",
2512	2512	"Offcore": "1",
2513	2513	"CounterHTOff": "0,1,2,3"
2514	2514	},
2515	2515	{
2516		- "PublicDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2516	+ "PublicDescription": "Counts any other requests",
2517	2517	"EventCode": "0xB7, 0xBB",
2518		- "MSRValue": "0x04003c8000 ",
	2518	+ "MSRValue": "0x04003C8000",
2519	2519	"Counter": "0,1,2,3",
2520	2520	"UMask": "0x1",
2521	2521	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
2522		- "MSRIndex": "0x1a6,0x1a7",
	2522	+ "MSRIndex": "0x1a6, 0x1a7",
2523	2523	"SampleAfterValue": "100003",
2524		- "BriefDescription": "Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2524	+ "BriefDescription": "Counts any other requests",
2525	2525	"Offcore": "1",
2526	2526	"CounterHTOff": "0,1,2,3"
2527	2527	},
2528	2528	{
2529		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2529	+ "PublicDescription": "Counts any other requests",
2530	2530	"EventCode": "0xB7, 0xBB",
2531		- "MSRValue": "0x10003c8000 ",
	2531	+ "MSRValue": "0x10003C8000",
2532	2532	"Counter": "0,1,2,3",
2533	2533	"UMask": "0x1",
2534	2534	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
2535		- "MSRIndex": "0x1a6,0x1a7",
	2535	+ "MSRIndex": "0x1a6, 0x1a7",
2536	2536	"SampleAfterValue": "100003",
2537		- "BriefDescription": "OTHER & L3_HIT & SNOOP_HITM",
	2537	+ "BriefDescription": "Counts any other requests",
2538	2538	"Offcore": "1",
2539	2539	"CounterHTOff": "0,1,2,3"
2540	2540	},
2541	2541	{
2542		- "PublicDescription": "Counts any other requests that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2542	+ "PublicDescription": "Counts any other requests",
2543	2543	"EventCode": "0xB7, 0xBB",
2544		- "MSRValue": "0x3f803c8000 ",
	2544	+ "MSRValue": "0x3F803C8000",
2545	2545	"Counter": "0,1,2,3",
2546	2546	"UMask": "0x1",
2547	2547	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
2548		- "MSRIndex": "0x1a6,0x1a7",
	2548	+ "MSRIndex": "0x1a6, 0x1a7",
2549	2549	"SampleAfterValue": "100003",
2550		- "BriefDescription": "Counts any other requests that hit in the L3.",
	2550	+ "BriefDescription": "Counts any other requests",
2551	2551	"Offcore": "1",
2552	2552	"CounterHTOff": "0,1,2,3"
2553	2553	},
2554	2554	{
2555		- "PublicDescription": "Counts all prefetch data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2555	+ "PublicDescription": "Counts all prefetch data reads have any response type.",
2556	2556	"EventCode": "0xB7, 0xBB",
2557		- "MSRValue": "0x0000010090 ",
	2557	+ "MSRValue": "0x0000010090",
2558	2558	"Counter": "0,1,2,3",
2559	2559	"UMask": "0x1",
2560	2560	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
2561		- "MSRIndex": "0x1a6,0x1a7",
	2561	+ "MSRIndex": "0x1a6, 0x1a7",
2562	2562	"SampleAfterValue": "100003",
2563		- "BriefDescription": "Counts all prefetch data reads that have any response type.",
	2563	+ "BriefDescription": "Counts all prefetch data reads have any response type.",
2564	2564	"Offcore": "1",
2565	2565	"CounterHTOff": "0,1,2,3"
2566	2566	},
2567	2567	{
2568		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2568	+ "PublicDescription": "Counts all prefetch data reads",
2569	2569	"EventCode": "0xB7, 0xBB",
2570		- "MSRValue": "0x0080020090 ",
	2570	+ "MSRValue": "0x0080020090",
2571	2571	"Counter": "0,1,2,3",
2572	2572	"UMask": "0x1",
2573	2573	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
2574		- "MSRIndex": "0x1a6,0x1a7",
	2574	+ "MSRIndex": "0x1a6, 0x1a7",
2575	2575	"SampleAfterValue": "100003",
2576		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
	2576	+ "BriefDescription": "Counts all prefetch data reads",
2577	2577	"Offcore": "1",
2578	2578	"CounterHTOff": "0,1,2,3"
2579	2579	},
2580	2580	{
2581		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2581	+ "PublicDescription": "Counts all prefetch data reads",
2582	2582	"EventCode": "0xB7, 0xBB",
2583		- "MSRValue": "0x0100020090 ",
	2583	+ "MSRValue": "0x0100020090",
2584	2584	"Counter": "0,1,2,3",
2585	2585	"UMask": "0x1",
2586	2586	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2587		- "MSRIndex": "0x1a6,0x1a7",
	2587	+ "MSRIndex": "0x1a6, 0x1a7",
2588	2588	"SampleAfterValue": "100003",
2589		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2589	+ "BriefDescription": "Counts all prefetch data reads",
2590	2590	"Offcore": "1",
2591	2591	"CounterHTOff": "0,1,2,3"
2592	2592	},
2593	2593	{
2594		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2594	+ "PublicDescription": "Counts all prefetch data reads",
2595	2595	"EventCode": "0xB7, 0xBB",
2596		- "MSRValue": "0x0200020090 ",
	2596	+ "MSRValue": "0x0200020090",
2597	2597	"Counter": "0,1,2,3",
2598	2598	"UMask": "0x1",
2599	2599	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
2600		- "MSRIndex": "0x1a6,0x1a7",
	2600	+ "MSRIndex": "0x1a6, 0x1a7",
2601	2601	"SampleAfterValue": "100003",
2602		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
	2602	+ "BriefDescription": "Counts all prefetch data reads",
2603	2603	"Offcore": "1",
2604	2604	"CounterHTOff": "0,1,2,3"
2605	2605	},
2606	2606	{
2607		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2607	+ "PublicDescription": "Counts all prefetch data reads",
2608	2608	"EventCode": "0xB7, 0xBB",
2609		- "MSRValue": "0x0400020090 ",
	2609	+ "MSRValue": "0x0400020090",
2610	2610	"Counter": "0,1,2,3",
2611	2611	"UMask": "0x1",
2612	2612	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2613		- "MSRIndex": "0x1a6,0x1a7",
	2613	+ "MSRIndex": "0x1a6, 0x1a7",
2614	2614	"SampleAfterValue": "100003",
2615		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2615	+ "BriefDescription": "Counts all prefetch data reads",
2616	2616	"Offcore": "1",
2617	2617	"CounterHTOff": "0,1,2,3"
2618	2618	},
2619	2619	{
2620		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2620	+ "PublicDescription": "Counts all prefetch data reads",
2621	2621	"EventCode": "0xB7, 0xBB",
2622		- "MSRValue": "0x1000020090 ",
	2622	+ "MSRValue": "0x1000020090",
2623	2623	"Counter": "0,1,2,3",
2624	2624	"UMask": "0x1",
2625	2625	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
2626		- "MSRIndex": "0x1a6,0x1a7",
	2626	+ "MSRIndex": "0x1a6, 0x1a7",
2627	2627	"SampleAfterValue": "100003",
2628		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
	2628	+ "BriefDescription": "Counts all prefetch data reads",
2629	2629	"Offcore": "1",
2630	2630	"CounterHTOff": "0,1,2,3"
2631	2631	},
2632	2632	{
2633		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2633	+ "PublicDescription": "Counts all prefetch data reads",
2634	2634	"EventCode": "0xB7, 0xBB",
2635		- "MSRValue": "0x3f80020090 ",
	2635	+ "MSRValue": "0x3F80020090",
2636	2636	"Counter": "0,1,2,3",
2637	2637	"UMask": "0x1",
2638	2638	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
2639		- "MSRIndex": "0x1a6,0x1a7",
	2639	+ "MSRIndex": "0x1a6, 0x1a7",
2640	2640	"SampleAfterValue": "100003",
2641		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
	2641	+ "BriefDescription": "Counts all prefetch data reads",
2642	2642	"Offcore": "1",
2643	2643	"CounterHTOff": "0,1,2,3"
2644	2644	},
2645	2645	{
2646		- "PublicDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2646	+ "PublicDescription": "Counts all prefetch data reads",
2647	2647	"EventCode": "0xB7, 0xBB",
2648		- "MSRValue": "0x00803c0090 ",
	2648	+ "MSRValue": "0x00803C0090",
2649	2649	"Counter": "0,1,2,3",
2650	2650	"UMask": "0x1",
2651	2651	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
2652		- "MSRIndex": "0x1a6,0x1a7",
	2652	+ "MSRIndex": "0x1a6, 0x1a7",
2653	2653	"SampleAfterValue": "100003",
2654		- "BriefDescription": "Counts all prefetch data reads that hit in the L3 with no details on snoop-related information.",
	2654	+ "BriefDescription": "Counts all prefetch data reads",
2655	2655	"Offcore": "1",
2656	2656	"CounterHTOff": "0,1,2,3"
2657	2657	},
2658	2658	{
2659		- "PublicDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2659	+ "PublicDescription": "Counts all prefetch data reads",
2660	2660	"EventCode": "0xB7, 0xBB",
2661		- "MSRValue": "0x01003c0090 ",
	2661	+ "MSRValue": "0x01003C0090",
2662	2662	"Counter": "0,1,2,3",
2663	2663	"UMask": "0x1",
2664	2664	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
2665		- "MSRIndex": "0x1a6,0x1a7",
	2665	+ "MSRIndex": "0x1a6, 0x1a7",
2666	2666	"SampleAfterValue": "100003",
2667		- "BriefDescription": "Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	2667	+ "BriefDescription": "Counts all prefetch data reads",
2668	2668	"Offcore": "1",
2669	2669	"CounterHTOff": "0,1,2,3"
2670	2670	},
2671	2671	{
2672		- "PublicDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2672	+ "PublicDescription": "Counts all prefetch data reads",
2673	2673	"EventCode": "0xB7, 0xBB",
2674		- "MSRValue": "0x02003c0090 ",
	2674	+ "MSRValue": "0x02003C0090",
2675	2675	"Counter": "0,1,2,3",
2676	2676	"UMask": "0x1",
2677	2677	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
2678		- "MSRIndex": "0x1a6,0x1a7",
	2678	+ "MSRIndex": "0x1a6, 0x1a7",
2679	2679	"SampleAfterValue": "100003",
2680		- "BriefDescription": "Counts all prefetch data reads that hit in the L3 with a snoop miss response.",
	2680	+ "BriefDescription": "Counts all prefetch data reads",
2681	2681	"Offcore": "1",
2682	2682	"CounterHTOff": "0,1,2,3"
2683	2683	},
2684	2684	{
2685		- "PublicDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2685	+ "PublicDescription": "Counts all prefetch data reads",
2686	2686	"EventCode": "0xB7, 0xBB",
2687		- "MSRValue": "0x04003c0090 ",
	2687	+ "MSRValue": "0x04003C0090",
2688	2688	"Counter": "0,1,2,3",
2689	2689	"UMask": "0x1",
2690	2690	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
2691		- "MSRIndex": "0x1a6,0x1a7",
	2691	+ "MSRIndex": "0x1a6, 0x1a7",
2692	2692	"SampleAfterValue": "100003",
2693		- "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2693	+ "BriefDescription": "Counts all prefetch data reads",
2694	2694	"Offcore": "1",
2695	2695	"CounterHTOff": "0,1,2,3"
2696	2696	},
2697	2697	{
2698		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2698	+ "PublicDescription": "Counts all prefetch data reads",
2699	2699	"EventCode": "0xB7, 0xBB",
2700		- "MSRValue": "0x10003c0090 ",
	2700	+ "MSRValue": "0x10003C0090",
2701	2701	"Counter": "0,1,2,3",
2702	2702	"UMask": "0x1",
2703	2703	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM",
2704		- "MSRIndex": "0x1a6,0x1a7",
	2704	+ "MSRIndex": "0x1a6, 0x1a7",
2705	2705	"SampleAfterValue": "100003",
2706		- "BriefDescription": "ALL_PF_DATA_RD & L3_HIT & SNOOP_HITM",
	2706	+ "BriefDescription": "Counts all prefetch data reads",
2707	2707	"Offcore": "1",
2708	2708	"CounterHTOff": "0,1,2,3"
2709	2709	},
2710	2710	{
2711		- "PublicDescription": "Counts all prefetch data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2711	+ "PublicDescription": "Counts all prefetch data reads",
2712	2712	"EventCode": "0xB7, 0xBB",
2713		- "MSRValue": "0x3f803c0090 ",
	2713	+ "MSRValue": "0x3F803C0090",
2714	2714	"Counter": "0,1,2,3",
2715	2715	"UMask": "0x1",
2716	2716	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
2717		- "MSRIndex": "0x1a6,0x1a7",
	2717	+ "MSRIndex": "0x1a6, 0x1a7",
2718	2718	"SampleAfterValue": "100003",
2719		- "BriefDescription": "Counts all prefetch data reads that hit in the L3.",
	2719	+ "BriefDescription": "Counts all prefetch data reads",
2720	2720	"Offcore": "1",
2721	2721	"CounterHTOff": "0,1,2,3"
2722	2722	},
2723	2723	{
2724		- "PublicDescription": "Counts prefetch RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2724	+ "PublicDescription": "Counts prefetch RFOs have any response type.",
2725	2725	"EventCode": "0xB7, 0xBB",
2726		- "MSRValue": "0x0000010120 ",
	2726	+ "MSRValue": "0x0000010120",
2727	2727	"Counter": "0,1,2,3",
2728	2728	"UMask": "0x1",
2729	2729	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
2730		- "MSRIndex": "0x1a6,0x1a7",
	2730	+ "MSRIndex": "0x1a6, 0x1a7",
2731	2731	"SampleAfterValue": "100003",
2732		- "BriefDescription": "Counts prefetch RFOs that have any response type.",
	2732	+ "BriefDescription": "Counts prefetch RFOs have any response type.",
2733	2733	"Offcore": "1",
2734	2734	"CounterHTOff": "0,1,2,3"
2735	2735	},
2736	2736	{
2737		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2737	+ "PublicDescription": "Counts prefetch RFOs",
2738	2738	"EventCode": "0xB7, 0xBB",
2739		- "MSRValue": "0x0080020120 ",
	2739	+ "MSRValue": "0x0080020120",
2740	2740	"Counter": "0,1,2,3",
2741	2741	"UMask": "0x1",
2742	2742	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
2743		- "MSRIndex": "0x1a6,0x1a7",
	2743	+ "MSRIndex": "0x1a6, 0x1a7",
2744	2744	"SampleAfterValue": "100003",
2745		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NONE",
	2745	+ "BriefDescription": "Counts prefetch RFOs",
2746	2746	"Offcore": "1",
2747	2747	"CounterHTOff": "0,1,2,3"
2748	2748	},
2749	2749	{
2750		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2750	+ "PublicDescription": "Counts prefetch RFOs",
2751	2751	"EventCode": "0xB7, 0xBB",
2752		- "MSRValue": "0x0100020120 ",
	2752	+ "MSRValue": "0x0100020120",
2753	2753	"Counter": "0,1,2,3",
2754	2754	"UMask": "0x1",
2755	2755	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2756		- "MSRIndex": "0x1a6,0x1a7",
	2756	+ "MSRIndex": "0x1a6, 0x1a7",
2757	2757	"SampleAfterValue": "100003",
2758		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2758	+ "BriefDescription": "Counts prefetch RFOs",
2759	2759	"Offcore": "1",
2760	2760	"CounterHTOff": "0,1,2,3"
2761	2761	},
2762	2762	{
2763		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2763	+ "PublicDescription": "Counts prefetch RFOs",
2764	2764	"EventCode": "0xB7, 0xBB",
2765		- "MSRValue": "0x0200020120 ",
	2765	+ "MSRValue": "0x0200020120",
2766	2766	"Counter": "0,1,2,3",
2767	2767	"UMask": "0x1",
2768	2768	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
2769		- "MSRIndex": "0x1a6,0x1a7",
	2769	+ "MSRIndex": "0x1a6, 0x1a7",
2770	2770	"SampleAfterValue": "100003",
2771		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_MISS",
	2771	+ "BriefDescription": "Counts prefetch RFOs",
2772	2772	"Offcore": "1",
2773	2773	"CounterHTOff": "0,1,2,3"
2774	2774	},
2775	2775	{
2776		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2776	+ "PublicDescription": "Counts prefetch RFOs",
2777	2777	"EventCode": "0xB7, 0xBB",
2778		- "MSRValue": "0x0400020120 ",
	2778	+ "MSRValue": "0x0400020120",
2779	2779	"Counter": "0,1,2,3",
2780	2780	"UMask": "0x1",
2781	2781	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2782		- "MSRIndex": "0x1a6,0x1a7",
	2782	+ "MSRIndex": "0x1a6, 0x1a7",
2783	2783	"SampleAfterValue": "100003",
2784		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2784	+ "BriefDescription": "Counts prefetch RFOs",
2785	2785	"Offcore": "1",
2786	2786	"CounterHTOff": "0,1,2,3"
2787	2787	},
2788	2788	{
2789		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2789	+ "PublicDescription": "Counts prefetch RFOs",
2790	2790	"EventCode": "0xB7, 0xBB",
2791		- "MSRValue": "0x1000020120 ",
	2791	+ "MSRValue": "0x1000020120",
2792	2792	"Counter": "0,1,2,3",
2793	2793	"UMask": "0x1",
2794	2794	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM",
2795		- "MSRIndex": "0x1a6,0x1a7",
	2795	+ "MSRIndex": "0x1a6, 0x1a7",
2796	2796	"SampleAfterValue": "100003",
2797		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_HITM",
	2797	+ "BriefDescription": "Counts prefetch RFOs",
2798	2798	"Offcore": "1",
2799	2799	"CounterHTOff": "0,1,2,3"
2800	2800	},
2801	2801	{
2802		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2802	+ "PublicDescription": "Counts prefetch RFOs",
2803	2803	"EventCode": "0xB7, 0xBB",
2804		- "MSRValue": "0x3f80020120 ",
	2804	+ "MSRValue": "0x3F80020120",
2805	2805	"Counter": "0,1,2,3",
2806	2806	"UMask": "0x1",
2807	2807	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
2808		- "MSRIndex": "0x1a6,0x1a7",
	2808	+ "MSRIndex": "0x1a6, 0x1a7",
2809	2809	"SampleAfterValue": "100003",
2810		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & ANY_SNOOP",
	2810	+ "BriefDescription": "Counts prefetch RFOs",
2811	2811	"Offcore": "1",
2812	2812	"CounterHTOff": "0,1,2,3"
2813	2813	},
2814	2814	{
2815		- "PublicDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2815	+ "PublicDescription": "Counts prefetch RFOs",
2816	2816	"EventCode": "0xB7, 0xBB",
2817		- "MSRValue": "0x00803c0120 ",
	2817	+ "MSRValue": "0x00803C0120",
2818	2818	"Counter": "0,1,2,3",
2819	2819	"UMask": "0x1",
2820	2820	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
2821		- "MSRIndex": "0x1a6,0x1a7",
	2821	+ "MSRIndex": "0x1a6, 0x1a7",
2822	2822	"SampleAfterValue": "100003",
2823		- "BriefDescription": "Counts prefetch RFOs that hit in the L3 with no details on snoop-related information.",
	2823	+ "BriefDescription": "Counts prefetch RFOs",
2824	2824	"Offcore": "1",
2825	2825	"CounterHTOff": "0,1,2,3"
2826	2826	},
2827	2827	{
2828		- "PublicDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2828	+ "PublicDescription": "Counts prefetch RFOs",
2829	2829	"EventCode": "0xB7, 0xBB",
2830		- "MSRValue": "0x01003c0120 ",
	2830	+ "MSRValue": "0x01003C0120",
2831	2831	"Counter": "0,1,2,3",
2832	2832	"UMask": "0x1",
2833	2833	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED",
2834		- "MSRIndex": "0x1a6,0x1a7",
	2834	+ "MSRIndex": "0x1a6, 0x1a7",
2835	2835	"SampleAfterValue": "100003",
2836		- "BriefDescription": "Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	2836	+ "BriefDescription": "Counts prefetch RFOs",
2837	2837	"Offcore": "1",
2838	2838	"CounterHTOff": "0,1,2,3"
2839	2839	},
2840	2840	{
2841		- "PublicDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2841	+ "PublicDescription": "Counts prefetch RFOs",
2842	2842	"EventCode": "0xB7, 0xBB",
2843		- "MSRValue": "0x02003c0120 ",
	2843	+ "MSRValue": "0x02003C0120",
2844	2844	"Counter": "0,1,2,3",
2845	2845	"UMask": "0x1",
2846	2846	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
2847		- "MSRIndex": "0x1a6,0x1a7",
	2847	+ "MSRIndex": "0x1a6, 0x1a7",
2848	2848	"SampleAfterValue": "100003",
2849		- "BriefDescription": "Counts prefetch RFOs that hit in the L3 with a snoop miss response.",
	2849	+ "BriefDescription": "Counts prefetch RFOs",
2850	2850	"Offcore": "1",
2851	2851	"CounterHTOff": "0,1,2,3"
2852	2852	},
2853	2853	{
2854		- "PublicDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2854	+ "PublicDescription": "Counts prefetch RFOs",
2855	2855	"EventCode": "0xB7, 0xBB",
2856		- "MSRValue": "0x04003c0120 ",
	2856	+ "MSRValue": "0x04003C0120",
2857	2857	"Counter": "0,1,2,3",
2858	2858	"UMask": "0x1",
2859	2859	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
2860		- "MSRIndex": "0x1a6,0x1a7",
	2860	+ "MSRIndex": "0x1a6, 0x1a7",
2861	2861	"SampleAfterValue": "100003",
2862		- "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	2862	+ "BriefDescription": "Counts prefetch RFOs",
2863	2863	"Offcore": "1",
2864	2864	"CounterHTOff": "0,1,2,3"
2865	2865	},
2866	2866	{
2867		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2867	+ "PublicDescription": "Counts prefetch RFOs",
2868	2868	"EventCode": "0xB7, 0xBB",
2869		- "MSRValue": "0x10003c0120 ",
	2869	+ "MSRValue": "0x10003C0120",
2870	2870	"Counter": "0,1,2,3",
2871	2871	"UMask": "0x1",
2872	2872	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM",
2873		- "MSRIndex": "0x1a6,0x1a7",
	2873	+ "MSRIndex": "0x1a6, 0x1a7",
2874	2874	"SampleAfterValue": "100003",
2875		- "BriefDescription": "ALL_PF_RFO & L3_HIT & SNOOP_HITM",
	2875	+ "BriefDescription": "Counts prefetch RFOs",
2876	2876	"Offcore": "1",
2877	2877	"CounterHTOff": "0,1,2,3"
2878	2878	},
2879	2879	{
2880		- "PublicDescription": "Counts prefetch RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2880	+ "PublicDescription": "Counts prefetch RFOs",
2881	2881	"EventCode": "0xB7, 0xBB",
2882		- "MSRValue": "0x3f803c0120 ",
	2882	+ "MSRValue": "0x3F803C0120",
2883	2883	"Counter": "0,1,2,3",
2884	2884	"UMask": "0x1",
2885	2885	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
2886		- "MSRIndex": "0x1a6,0x1a7",
	2886	+ "MSRIndex": "0x1a6, 0x1a7",
2887	2887	"SampleAfterValue": "100003",
2888		- "BriefDescription": "Counts prefetch RFOs that hit in the L3.",
	2888	+ "BriefDescription": "Counts prefetch RFOs",
2889	2889	"Offcore": "1",
2890	2890	"CounterHTOff": "0,1,2,3"
2891	2891	},
2892	2892	{
2893		- "PublicDescription": "Counts all prefetch code reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2893	+ "PublicDescription": "Counts all prefetch code reads have any response type.",
2894	2894	"EventCode": "0xB7, 0xBB",
2895		- "MSRValue": "0x0000010240 ",
	2895	+ "MSRValue": "0x0000010240",
2896	2896	"Counter": "0,1,2,3",
2897	2897	"UMask": "0x1",
2898	2898	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE",
2899		- "MSRIndex": "0x1a6,0x1a7",
	2899	+ "MSRIndex": "0x1a6, 0x1a7",
2900	2900	"SampleAfterValue": "100003",
2901		- "BriefDescription": "Counts all prefetch code reads that have any response type.",
	2901	+ "BriefDescription": "Counts all prefetch code reads have any response type.",
2902	2902	"Offcore": "1",
2903	2903	"CounterHTOff": "0,1,2,3"
2904	2904	},
2905	2905	{
2906		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2906	+ "PublicDescription": "Counts all prefetch code reads",
2907	2907	"EventCode": "0xB7, 0xBB",
2908		- "MSRValue": "0x0080020240 ",
	2908	+ "MSRValue": "0x0080020240",
2909	2909	"Counter": "0,1,2,3",
2910	2910	"UMask": "0x1",
2911	2911	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
2912		- "MSRIndex": "0x1a6,0x1a7",
	2912	+ "MSRIndex": "0x1a6, 0x1a7",
2913	2913	"SampleAfterValue": "100003",
2914		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NONE",
	2914	+ "BriefDescription": "Counts all prefetch code reads",
2915	2915	"Offcore": "1",
2916	2916	"CounterHTOff": "0,1,2,3"
2917	2917	},
2918	2918	{
2919		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2919	+ "PublicDescription": "Counts all prefetch code reads",
2920	2920	"EventCode": "0xB7, 0xBB",
2921		- "MSRValue": "0x0100020240 ",
	2921	+ "MSRValue": "0x0100020240",
2922	2922	"Counter": "0,1,2,3",
2923	2923	"UMask": "0x1",
2924	2924	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2925		- "MSRIndex": "0x1a6,0x1a7",
	2925	+ "MSRIndex": "0x1a6, 0x1a7",
2926	2926	"SampleAfterValue": "100003",
2927		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	2927	+ "BriefDescription": "Counts all prefetch code reads",
2928	2928	"Offcore": "1",
2929	2929	"CounterHTOff": "0,1,2,3"
2930	2930	},
2931	2931	{
2932		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2932	+ "PublicDescription": "Counts all prefetch code reads",
2933	2933	"EventCode": "0xB7, 0xBB",
2934		- "MSRValue": "0x0200020240 ",
	2934	+ "MSRValue": "0x0200020240",
2935	2935	"Counter": "0,1,2,3",
2936	2936	"UMask": "0x1",
2937	2937	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
2938		- "MSRIndex": "0x1a6,0x1a7",
	2938	+ "MSRIndex": "0x1a6, 0x1a7",
2939	2939	"SampleAfterValue": "100003",
2940		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_MISS",
	2940	+ "BriefDescription": "Counts all prefetch code reads",
2941	2941	"Offcore": "1",
2942	2942	"CounterHTOff": "0,1,2,3"
2943	2943	},
2944	2944	{
2945		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2945	+ "PublicDescription": "Counts all prefetch code reads",
2946	2946	"EventCode": "0xB7, 0xBB",
2947		- "MSRValue": "0x0400020240 ",
	2947	+ "MSRValue": "0x0400020240",
2948	2948	"Counter": "0,1,2,3",
2949	2949	"UMask": "0x1",
2950	2950	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2951		- "MSRIndex": "0x1a6,0x1a7",
	2951	+ "MSRIndex": "0x1a6, 0x1a7",
2952	2952	"SampleAfterValue": "100003",
2953		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	2953	+ "BriefDescription": "Counts all prefetch code reads",
2954	2954	"Offcore": "1",
2955	2955	"CounterHTOff": "0,1,2,3"
2956	2956	},
2957	2957	{
2958		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2958	+ "PublicDescription": "Counts all prefetch code reads",
2959	2959	"EventCode": "0xB7, 0xBB",
2960		- "MSRValue": "0x1000020240 ",
	2960	+ "MSRValue": "0x1000020240",
2961	2961	"Counter": "0,1,2,3",
2962	2962	"UMask": "0x1",
2963	2963	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
2964		- "MSRIndex": "0x1a6,0x1a7",
	2964	+ "MSRIndex": "0x1a6, 0x1a7",
2965	2965	"SampleAfterValue": "100003",
2966		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_HITM",
	2966	+ "BriefDescription": "Counts all prefetch code reads",
2967	2967	"Offcore": "1",
2968	2968	"CounterHTOff": "0,1,2,3"
2969	2969	},
2970	2970	{
2971		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2971	+ "PublicDescription": "Counts all prefetch code reads",
2972	2972	"EventCode": "0xB7, 0xBB",
2973		- "MSRValue": "0x3f80020240 ",
	2973	+ "MSRValue": "0x3F80020240",
2974	2974	"Counter": "0,1,2,3",
2975	2975	"UMask": "0x1",
2976	2976	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
2977		- "MSRIndex": "0x1a6,0x1a7",
	2977	+ "MSRIndex": "0x1a6, 0x1a7",
2978	2978	"SampleAfterValue": "100003",
2979		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & ANY_SNOOP",
	2979	+ "BriefDescription": "Counts all prefetch code reads",
2980	2980	"Offcore": "1",
2981	2981	"CounterHTOff": "0,1,2,3"
2982	2982	},
2983	2983	{
2984		- "PublicDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2984	+ "PublicDescription": "Counts all prefetch code reads",
2985	2985	"EventCode": "0xB7, 0xBB",
2986		- "MSRValue": "0x00803c0240 ",
	2986	+ "MSRValue": "0x00803C0240",
2987	2987	"Counter": "0,1,2,3",
2988	2988	"UMask": "0x1",
2989	2989	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE",
2990		- "MSRIndex": "0x1a6,0x1a7",
	2990	+ "MSRIndex": "0x1a6, 0x1a7",
2991	2991	"SampleAfterValue": "100003",
2992		- "BriefDescription": "Counts all prefetch code reads that hit in the L3 with no details on snoop-related information.",
	2992	+ "BriefDescription": "Counts all prefetch code reads",
2993	2993	"Offcore": "1",
2994	2994	"CounterHTOff": "0,1,2,3"
2995	2995	},
2996	2996	{
2997		- "PublicDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2997	+ "PublicDescription": "Counts all prefetch code reads",
2998	2998	"EventCode": "0xB7, 0xBB",
2999		- "MSRValue": "0x01003c0240 ",
	2999	+ "MSRValue": "0x01003C0240",
3000	3000	"Counter": "0,1,2,3",
3001	3001	"UMask": "0x1",
3002	3002	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
3003		- "MSRIndex": "0x1a6,0x1a7",
	3003	+ "MSRIndex": "0x1a6, 0x1a7",
3004	3004	"SampleAfterValue": "100003",
3005		- "BriefDescription": "Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	3005	+ "BriefDescription": "Counts all prefetch code reads",
3006	3006	"Offcore": "1",
3007	3007	"CounterHTOff": "0,1,2,3"
3008	3008	},
3009	3009	{
3010		- "PublicDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3010	+ "PublicDescription": "Counts all prefetch code reads",
3011	3011	"EventCode": "0xB7, 0xBB",
3012		- "MSRValue": "0x02003c0240 ",
	3012	+ "MSRValue": "0x02003C0240",
3013	3013	"Counter": "0,1,2,3",
3014	3014	"UMask": "0x1",
3015	3015	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS",
3016		- "MSRIndex": "0x1a6,0x1a7",
	3016	+ "MSRIndex": "0x1a6, 0x1a7",
3017	3017	"SampleAfterValue": "100003",
3018		- "BriefDescription": "Counts all prefetch code reads that hit in the L3 with a snoop miss response.",
	3018	+ "BriefDescription": "Counts all prefetch code reads",
3019	3019	"Offcore": "1",
3020	3020	"CounterHTOff": "0,1,2,3"
3021	3021	},
3022	3022	{
3023		- "PublicDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3023	+ "PublicDescription": "Counts all prefetch code reads",
3024	3024	"EventCode": "0xB7, 0xBB",
3025		- "MSRValue": "0x04003c0240 ",
	3025	+ "MSRValue": "0x04003C0240",
3026	3026	"Counter": "0,1,2,3",
3027	3027	"UMask": "0x1",
3028	3028	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
3029		- "MSRIndex": "0x1a6,0x1a7",
	3029	+ "MSRIndex": "0x1a6, 0x1a7",
3030	3030	"SampleAfterValue": "100003",
3031		- "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	3031	+ "BriefDescription": "Counts all prefetch code reads",
3032	3032	"Offcore": "1",
3033	3033	"CounterHTOff": "0,1,2,3"
3034	3034	},
3035	3035	{
3036		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3036	+ "PublicDescription": "Counts all prefetch code reads",
3037	3037	"EventCode": "0xB7, 0xBB",
3038		- "MSRValue": "0x10003c0240 ",
	3038	+ "MSRValue": "0x10003C0240",
3039	3039	"Counter": "0,1,2,3",
3040	3040	"UMask": "0x1",
3041	3041	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM",
3042		- "MSRIndex": "0x1a6,0x1a7",
	3042	+ "MSRIndex": "0x1a6, 0x1a7",
3043	3043	"SampleAfterValue": "100003",
3044		- "BriefDescription": "ALL_PF_CODE_RD & L3_HIT & SNOOP_HITM",
	3044	+ "BriefDescription": "Counts all prefetch code reads",
3045	3045	"Offcore": "1",
3046	3046	"CounterHTOff": "0,1,2,3"
3047	3047	},
3048	3048	{
3049		- "PublicDescription": "Counts all prefetch code reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3049	+ "PublicDescription": "Counts all prefetch code reads",
3050	3050	"EventCode": "0xB7, 0xBB",
3051		- "MSRValue": "0x3f803c0240 ",
	3051	+ "MSRValue": "0x3F803C0240",
3052	3052	"Counter": "0,1,2,3",
3053	3053	"UMask": "0x1",
3054	3054	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP",
3055		- "MSRIndex": "0x1a6,0x1a7",
	3055	+ "MSRIndex": "0x1a6, 0x1a7",
3056	3056	"SampleAfterValue": "100003",
3057		- "BriefDescription": "Counts all prefetch code reads that hit in the L3.",
	3057	+ "BriefDescription": "Counts all prefetch code reads",
3058	3058	"Offcore": "1",
3059	3059	"CounterHTOff": "0,1,2,3"
3060	3060	},
3061	3061	{
3062		- "PublicDescription": "Counts all demand & prefetch data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3062	+ "PublicDescription": "Counts all demand & prefetch data reads have any response type.",
3063	3063	"EventCode": "0xB7, 0xBB",
3064		- "MSRValue": "0x0000010091 ",
	3064	+ "MSRValue": "0x0000010091",
3065	3065	"Counter": "0,1,2,3",
3066	3066	"UMask": "0x1",
3067	3067	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
3068		- "MSRIndex": "0x1a6,0x1a7",
	3068	+ "MSRIndex": "0x1a6, 0x1a7",
3069	3069	"SampleAfterValue": "100003",
3070		- "BriefDescription": "Counts all demand & prefetch data reads that have any response type.",
	3070	+ "BriefDescription": "Counts all demand & prefetch data reads have any response type.",
3071	3071	"Offcore": "1",
3072	3072	"CounterHTOff": "0,1,2,3"
3073	3073	},
3074	3074	{
3075		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3075	+ "PublicDescription": "Counts all demand & prefetch data reads",
3076	3076	"EventCode": "0xB7, 0xBB",
3077		- "MSRValue": "0x0080020091 ",
	3077	+ "MSRValue": "0x0080020091",
3078	3078	"Counter": "0,1,2,3",
3079	3079	"UMask": "0x1",
3080	3080	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
3081		- "MSRIndex": "0x1a6,0x1a7",
	3081	+ "MSRIndex": "0x1a6, 0x1a7",
3082	3082	"SampleAfterValue": "100003",
3083		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
	3083	+ "BriefDescription": "Counts all demand & prefetch data reads",
3084	3084	"Offcore": "1",
3085	3085	"CounterHTOff": "0,1,2,3"
3086	3086	},
3087	3087	{
3088		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3088	+ "PublicDescription": "Counts all demand & prefetch data reads",
3089	3089	"EventCode": "0xB7, 0xBB",
3090		- "MSRValue": "0x0100020091 ",
	3090	+ "MSRValue": "0x0100020091",
3091	3091	"Counter": "0,1,2,3",
3092	3092	"UMask": "0x1",
3093	3093	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
3094		- "MSRIndex": "0x1a6,0x1a7",
	3094	+ "MSRIndex": "0x1a6, 0x1a7",
3095	3095	"SampleAfterValue": "100003",
3096		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	3096	+ "BriefDescription": "Counts all demand & prefetch data reads",
3097	3097	"Offcore": "1",
3098	3098	"CounterHTOff": "0,1,2,3"
3099	3099	},
3100	3100	{
3101		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3101	+ "PublicDescription": "Counts all demand & prefetch data reads",
3102	3102	"EventCode": "0xB7, 0xBB",
3103		- "MSRValue": "0x0200020091 ",
	3103	+ "MSRValue": "0x0200020091",
3104	3104	"Counter": "0,1,2,3",
3105	3105	"UMask": "0x1",
3106	3106	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
3107		- "MSRIndex": "0x1a6,0x1a7",
	3107	+ "MSRIndex": "0x1a6, 0x1a7",
3108	3108	"SampleAfterValue": "100003",
3109		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
	3109	+ "BriefDescription": "Counts all demand & prefetch data reads",
3110	3110	"Offcore": "1",
3111	3111	"CounterHTOff": "0,1,2,3"
3112	3112	},
3113	3113	{
3114		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3114	+ "PublicDescription": "Counts all demand & prefetch data reads",
3115	3115	"EventCode": "0xB7, 0xBB",
3116		- "MSRValue": "0x0400020091 ",
	3116	+ "MSRValue": "0x0400020091",
3117	3117	"Counter": "0,1,2,3",
3118	3118	"UMask": "0x1",
3119	3119	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
3120		- "MSRIndex": "0x1a6,0x1a7",
	3120	+ "MSRIndex": "0x1a6, 0x1a7",
3121	3121	"SampleAfterValue": "100003",
3122		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	3122	+ "BriefDescription": "Counts all demand & prefetch data reads",
3123	3123	"Offcore": "1",
3124	3124	"CounterHTOff": "0,1,2,3"
3125	3125	},
3126	3126	{
3127		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3127	+ "PublicDescription": "Counts all demand & prefetch data reads",
3128	3128	"EventCode": "0xB7, 0xBB",
3129		- "MSRValue": "0x1000020091 ",
	3129	+ "MSRValue": "0x1000020091",
3130	3130	"Counter": "0,1,2,3",
3131	3131	"UMask": "0x1",
3132	3132	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
3133		- "MSRIndex": "0x1a6,0x1a7",
	3133	+ "MSRIndex": "0x1a6, 0x1a7",
3134	3134	"SampleAfterValue": "100003",
3135		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
	3135	+ "BriefDescription": "Counts all demand & prefetch data reads",
3136	3136	"Offcore": "1",
3137	3137	"CounterHTOff": "0,1,2,3"
3138	3138	},
3139	3139	{
3140		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3140	+ "PublicDescription": "Counts all demand & prefetch data reads",
3141	3141	"EventCode": "0xB7, 0xBB",
3142		- "MSRValue": "0x3f80020091 ",
	3142	+ "MSRValue": "0x3F80020091",
3143	3143	"Counter": "0,1,2,3",
3144	3144	"UMask": "0x1",
3145	3145	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
3146		- "MSRIndex": "0x1a6,0x1a7",
	3146	+ "MSRIndex": "0x1a6, 0x1a7",
3147	3147	"SampleAfterValue": "100003",
3148		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
	3148	+ "BriefDescription": "Counts all demand & prefetch data reads",
3149	3149	"Offcore": "1",
3150	3150	"CounterHTOff": "0,1,2,3"
3151	3151	},
3152	3152	{
3153		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3153	+ "PublicDescription": "Counts all demand & prefetch data reads",
3154	3154	"EventCode": "0xB7, 0xBB",
3155		- "MSRValue": "0x00803c0091 ",
	3155	+ "MSRValue": "0x00803C0091",
3156	3156	"Counter": "0,1,2,3",
3157	3157	"UMask": "0x1",
3158	3158	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
3159		- "MSRIndex": "0x1a6,0x1a7",
	3159	+ "MSRIndex": "0x1a6, 0x1a7",
3160	3160	"SampleAfterValue": "100003",
3161		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with no details on snoop-related information.",
	3161	+ "BriefDescription": "Counts all demand & prefetch data reads",
3162	3162	"Offcore": "1",
3163	3163	"CounterHTOff": "0,1,2,3"
3164	3164	},
3165	3165	{
3166		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3166	+ "PublicDescription": "Counts all demand & prefetch data reads",
3167	3167	"EventCode": "0xB7, 0xBB",
3168		- "MSRValue": "0x01003c0091 ",
	3168	+ "MSRValue": "0x01003C0091",
3169	3169	"Counter": "0,1,2,3",
3170	3170	"UMask": "0x1",
3171	3171	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
3172		- "MSRIndex": "0x1a6,0x1a7",
	3172	+ "MSRIndex": "0x1a6, 0x1a7",
3173	3173	"SampleAfterValue": "100003",
3174		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	3174	+ "BriefDescription": "Counts all demand & prefetch data reads",
3175	3175	"Offcore": "1",
3176	3176	"CounterHTOff": "0,1,2,3"
3177	3177	},
3178	3178	{
3179		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3179	+ "PublicDescription": "Counts all demand & prefetch data reads",
3180	3180	"EventCode": "0xB7, 0xBB",
3181		- "MSRValue": "0x02003c0091 ",
	3181	+ "MSRValue": "0x02003C0091",
3182	3182	"Counter": "0,1,2,3",
3183	3183	"UMask": "0x1",
3184	3184	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
3185		- "MSRIndex": "0x1a6,0x1a7",
	3185	+ "MSRIndex": "0x1a6, 0x1a7",
3186	3186	"SampleAfterValue": "100003",
3187		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 with a snoop miss response.",
	3187	+ "BriefDescription": "Counts all demand & prefetch data reads",
3188	3188	"Offcore": "1",
3189	3189	"CounterHTOff": "0,1,2,3"
3190	3190	},
3191	3191	{
3192		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3192	+ "PublicDescription": "Counts all demand & prefetch data reads",
3193	3193	"EventCode": "0xB7, 0xBB",
3194		- "MSRValue": "0x04003c0091 ",
	3194	+ "MSRValue": "0x04003C0091",
3195	3195	"Counter": "0,1,2,3",
3196	3196	"UMask": "0x1",
3197	3197	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
3198		- "MSRIndex": "0x1a6,0x1a7",
	3198	+ "MSRIndex": "0x1a6, 0x1a7",
3199	3199	"SampleAfterValue": "100003",
3200		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	3200	+ "BriefDescription": "Counts all demand & prefetch data reads",
3201	3201	"Offcore": "1",
3202	3202	"CounterHTOff": "0,1,2,3"
3203	3203	},
3204	3204	{
3205		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3205	+ "PublicDescription": "Counts all demand & prefetch data reads",
3206	3206	"EventCode": "0xB7, 0xBB",
3207		- "MSRValue": "0x10003c0091 ",
	3207	+ "MSRValue": "0x10003C0091",
3208	3208	"Counter": "0,1,2,3",
3209	3209	"UMask": "0x1",
3210	3210	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM",
3211		- "MSRIndex": "0x1a6,0x1a7",
	3211	+ "MSRIndex": "0x1a6, 0x1a7",
3212	3212	"SampleAfterValue": "100003",
3213		- "BriefDescription": "ALL_DATA_RD & L3_HIT & SNOOP_HITM",
	3213	+ "BriefDescription": "Counts all demand & prefetch data reads",
3214	3214	"Offcore": "1",
3215	3215	"CounterHTOff": "0,1,2,3"
3216	3216	},
3217	3217	{
3218		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3218	+ "PublicDescription": "Counts all demand & prefetch data reads",
3219	3219	"EventCode": "0xB7, 0xBB",
3220		- "MSRValue": "0x3f803c0091 ",
	3220	+ "MSRValue": "0x3F803C0091",
3221	3221	"Counter": "0,1,2,3",
3222	3222	"UMask": "0x1",
3223	3223	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
3224		- "MSRIndex": "0x1a6,0x1a7",
	3224	+ "MSRIndex": "0x1a6, 0x1a7",
3225	3225	"SampleAfterValue": "100003",
3226		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3.",
	3226	+ "BriefDescription": "Counts all demand & prefetch data reads",
3227	3227	"Offcore": "1",
3228	3228	"CounterHTOff": "0,1,2,3"
3229	3229	},
3230	3230	{
3231		- "PublicDescription": "Counts all demand & prefetch RFOs that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3231	+ "PublicDescription": "Counts all demand & prefetch RFOs have any response type.",
3232	3232	"EventCode": "0xB7, 0xBB",
3233		- "MSRValue": "0x0000010122 ",
	3233	+ "MSRValue": "0x0000010122",
3234	3234	"Counter": "0,1,2,3",
3235	3235	"UMask": "0x1",
3236	3236	"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
3237		- "MSRIndex": "0x1a6,0x1a7",
	3237	+ "MSRIndex": "0x1a6, 0x1a7",
3238	3238	"SampleAfterValue": "100003",
3239		- "BriefDescription": "Counts all demand & prefetch RFOs that have any response type.",
	3239	+ "BriefDescription": "Counts all demand & prefetch RFOs have any response type.",
3240	3240	"Offcore": "1",
3241	3241	"CounterHTOff": "0,1,2,3"
3242	3242	},
3243	3243	{
3244		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3244	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3245	3245	"EventCode": "0xB7, 0xBB",
3246		- "MSRValue": "0x0080020122 ",
	3246	+ "MSRValue": "0x0080020122",
3247	3247	"Counter": "0,1,2,3",
3248	3248	"UMask": "0x1",
3249	3249	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
3250		- "MSRIndex": "0x1a6,0x1a7",
	3250	+ "MSRIndex": "0x1a6, 0x1a7",
3251	3251	"SampleAfterValue": "100003",
3252		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NONE",
	3252	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3253	3253	"Offcore": "1",
3254	3254	"CounterHTOff": "0,1,2,3"
3255	3255	},
3256	3256	{
3257		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3257	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3258	3258	"EventCode": "0xB7, 0xBB",
3259		- "MSRValue": "0x0100020122 ",
	3259	+ "MSRValue": "0x0100020122",
3260	3260	"Counter": "0,1,2,3",
3261	3261	"UMask": "0x1",
3262	3262	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
3263		- "MSRIndex": "0x1a6,0x1a7",
	3263	+ "MSRIndex": "0x1a6, 0x1a7",
3264	3264	"SampleAfterValue": "100003",
3265		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
	3265	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3266	3266	"Offcore": "1",
3267	3267	"CounterHTOff": "0,1,2,3"
3268	3268	},
3269	3269	{
3270		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3270	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3271	3271	"EventCode": "0xB7, 0xBB",
3272		- "MSRValue": "0x0200020122 ",
	3272	+ "MSRValue": "0x0200020122",
3273	3273	"Counter": "0,1,2,3",
3274	3274	"UMask": "0x1",
3275	3275	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
3276		- "MSRIndex": "0x1a6,0x1a7",
	3276	+ "MSRIndex": "0x1a6, 0x1a7",
3277	3277	"SampleAfterValue": "100003",
3278		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_MISS",
	3278	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3279	3279	"Offcore": "1",
3280	3280	"CounterHTOff": "0,1,2,3"
3281	3281	},
3282	3282	{
3283		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3283	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3284	3284	"EventCode": "0xB7, 0xBB",
3285		- "MSRValue": "0x0400020122 ",
	3285	+ "MSRValue": "0x0400020122",
3286	3286	"Counter": "0,1,2,3",
3287	3287	"UMask": "0x1",
3288	3288	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
3289		- "MSRIndex": "0x1a6,0x1a7",
	3289	+ "MSRIndex": "0x1a6, 0x1a7",
3290	3290	"SampleAfterValue": "100003",
3291		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
	3291	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3292	3292	"Offcore": "1",
3293	3293	"CounterHTOff": "0,1,2,3"
3294	3294	},
3295	3295	{
3296		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3296	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3297	3297	"EventCode": "0xB7, 0xBB",
3298		- "MSRValue": "0x1000020122 ",
	3298	+ "MSRValue": "0x1000020122",
3299	3299	"Counter": "0,1,2,3",
3300	3300	"UMask": "0x1",
3301	3301	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM",
3302		- "MSRIndex": "0x1a6,0x1a7",
	3302	+ "MSRIndex": "0x1a6, 0x1a7",
3303	3303	"SampleAfterValue": "100003",
3304		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_HITM",
	3304	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3305	3305	"Offcore": "1",
3306	3306	"CounterHTOff": "0,1,2,3"
3307	3307	},
3308	3308	{
3309		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3309	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3310	3310	"EventCode": "0xB7, 0xBB",
3311		- "MSRValue": "0x3f80020122 ",
	3311	+ "MSRValue": "0x3F80020122",
3312	3312	"Counter": "0,1,2,3",
3313	3313	"UMask": "0x1",
3314	3314	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
3315		- "MSRIndex": "0x1a6,0x1a7",
	3315	+ "MSRIndex": "0x1a6, 0x1a7",
3316	3316	"SampleAfterValue": "100003",
3317		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & ANY_SNOOP",
	3317	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3318	3318	"Offcore": "1",
3319	3319	"CounterHTOff": "0,1,2,3"
3320	3320	},
3321	3321	{
3322		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3322	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3323	3323	"EventCode": "0xB7, 0xBB",
3324		- "MSRValue": "0x00803c0122 ",
	3324	+ "MSRValue": "0x00803C0122",
3325	3325	"Counter": "0,1,2,3",
3326	3326	"UMask": "0x1",
3327	3327	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",
3328		- "MSRIndex": "0x1a6,0x1a7",
	3328	+ "MSRIndex": "0x1a6, 0x1a7",
3329	3329	"SampleAfterValue": "100003",
3330		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with no details on snoop-related information.",
	3330	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3331	3331	"Offcore": "1",
3332	3332	"CounterHTOff": "0,1,2,3"
3333	3333	},
3334	3334	{
3335		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3335	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3336	3336	"EventCode": "0xB7, 0xBB",
3337		- "MSRValue": "0x01003c0122 ",
	3337	+ "MSRValue": "0x01003C0122",
3338	3338	"Counter": "0,1,2,3",
3339	3339	"UMask": "0x1",
3340	3340	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED",
3341		- "MSRIndex": "0x1a6,0x1a7",
	3341	+ "MSRIndex": "0x1a6, 0x1a7",
3342	3342	"SampleAfterValue": "100003",
3343		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
	3343	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3344	3344	"Offcore": "1",
3345	3345	"CounterHTOff": "0,1,2,3"
3346	3346	},
3347	3347	{
3348		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3348	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3349	3349	"EventCode": "0xB7, 0xBB",
3350		- "MSRValue": "0x02003c0122 ",
	3350	+ "MSRValue": "0x02003C0122",
3351	3351	"Counter": "0,1,2,3",
3352	3352	"UMask": "0x1",
3353	3353	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
3354		- "MSRIndex": "0x1a6,0x1a7",
	3354	+ "MSRIndex": "0x1a6, 0x1a7",
3355	3355	"SampleAfterValue": "100003",
3356		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 with a snoop miss response.",
	3356	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3357	3357	"Offcore": "1",
3358	3358	"CounterHTOff": "0,1,2,3"
3359	3359	},
3360	3360	{
3361		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3361	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3362	3362	"EventCode": "0xB7, 0xBB",
3363		- "MSRValue": "0x04003c0122 ",
	3363	+ "MSRValue": "0x04003C0122",
3364	3364	"Counter": "0,1,2,3",
3365	3365	"UMask": "0x1",
3366	3366	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
3367		- "MSRIndex": "0x1a6,0x1a7",
	3367	+ "MSRIndex": "0x1a6, 0x1a7",
3368	3368	"SampleAfterValue": "100003",
3369		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
	3369	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3370	3370	"Offcore": "1",
3371	3371	"CounterHTOff": "0,1,2,3"
3372	3372	},
3373	3373	{
3374		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3374	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3375	3375	"EventCode": "0xB7, 0xBB",
3376		- "MSRValue": "0x10003c0122 ",
	3376	+ "MSRValue": "0x10003C0122",
3377	3377	"Counter": "0,1,2,3",
3378	3378	"UMask": "0x1",
3379	3379	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM",
3380		- "MSRIndex": "0x1a6,0x1a7",
	3380	+ "MSRIndex": "0x1a6, 0x1a7",
3381	3381	"SampleAfterValue": "100003",
3382		- "BriefDescription": "ALL_RFO & L3_HIT & SNOOP_HITM",
	3382	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3383	3383	"Offcore": "1",
3384	3384	"CounterHTOff": "0,1,2,3"
3385	3385	},
3386	3386	{
3387		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3387	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3388	3388	"EventCode": "0xB7, 0xBB",
3389		- "MSRValue": "0x3f803c0122 ",
	3389	+ "MSRValue": "0x3F803C0122",
3390	3390	"Counter": "0,1,2,3",
3391	3391	"UMask": "0x1",
3392	3392	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
3393		- "MSRIndex": "0x1a6,0x1a7",
	3393	+ "MSRIndex": "0x1a6, 0x1a7",
3394	3394	"SampleAfterValue": "100003",
3395		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3.",
	3395	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3396	3396	"Offcore": "1",
3397	3397	"CounterHTOff": "0,1,2,3"
3398	3398	}