add audio

hc

2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/sound/soc/rockchip/rockchip_spdif.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* sound/soc/rockchip/rk_spdif.c
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  *
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  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
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@@ -6,10 +7,6 @@
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  * Author: Jianqun <jay.xu@rock-chips.com>
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  * Copyright (c) 2015 Collabora Ltd.
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  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/module.h>
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@@ -63,7 +60,7 @@
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 	struct regmap *regmap;
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 };
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-static const struct of_device_id rk_spdif_match[] = {
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+static const struct of_device_id rk_spdif_match[] __maybe_unused = {
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 	{ .compatible = "rockchip,rk3066-spdif",
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 	  .data = (void *)RK_SPDIF_RK3066 },
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 	{ .compatible = "rockchip,rk3188-spdif",
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@@ -81,6 +78,8 @@
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 	{ .compatible = "rockchip,rk3399-spdif",
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 	  .data = (void *)RK_SPDIF_RK3366 },
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 	{ .compatible = "rockchip,rk3568-spdif",
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+	  .data = (void *)RK_SPDIF_RK3366 },
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+	{ .compatible = "rockchip,rk3588-spdif",
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 	  .data = (void *)RK_SPDIF_RK3366 },
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 	{},
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 };
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@@ -132,8 +131,8 @@
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 {
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 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
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 	unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
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-	int srate, mclk;
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-	int ret, i;
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+	unsigned int mclk_rate = clk_get_rate(spdif->mclk);
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+	int bmc, div, ret, i;
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 	u8 cs[CS_BYTE];
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 	u16 *fc = (u16 *)cs;
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@@ -147,8 +146,10 @@
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 	regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CSE_MASK,
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 			   SPDIF_CFGR_CSE_EN);
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-	srate = params_rate(params);
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-	mclk = srate * 128;
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+	/* bmc = 128fs */
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+	bmc = 128 * params_rate(params);
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+	div = DIV_ROUND_CLOSEST(mclk_rate, bmc);
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+	val |= SPDIF_CFGR_CLK_DIV(div);
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 	switch (params_format(params)) {
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 	case SNDRV_PCM_FORMAT_S16_LE:
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@@ -169,16 +170,9 @@
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 		return -EINVAL;
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 	}
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-	/* Set clock and calculate divider */
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-	ret = clk_set_rate(spdif->mclk, mclk);
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-	if (ret != 0) {
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-		dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
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-			ret);
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-		return ret;
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-	}
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-
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 	regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK,
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 			   SPDIF_CFGR_CLR_EN);
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+
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 	udelay(1);
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 	ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
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 				 SPDIF_CFGR_CLK_DIV_MASK |
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@@ -243,7 +237,24 @@
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 	return 0;
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 }
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+static int rk_spdif_set_sysclk(struct snd_soc_dai *dai,
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+			       int clk_id, unsigned int freq, int dir)
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+{
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+	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
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+	int ret = 0;
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+
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+	if (!freq)
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+		return 0;
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+
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+	ret = clk_set_rate(spdif->mclk, freq);
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+	if (ret)
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+		dev_err(spdif->dev, "Failed to set mclk: %d\n", ret);
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+
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+	return ret;
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+}
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+
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 static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
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+	.set_sysclk = rk_spdif_set_sysclk,
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 	.hw_params = rk_spdif_hw_params,
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 	.trigger = rk_spdif_trigger,
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 };
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@@ -363,8 +374,7 @@
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 	if (IS_ERR(spdif->mclk))
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 		return PTR_ERR(spdif->mclk);
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	regs = devm_ioremap_resource(&pdev->dev, res);
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+	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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 	if (IS_ERR(regs))
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 		return PTR_ERR(regs);
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