~hc/RK356X_SDK_RELEASE.git

..	..	@@ -24,6 +24,12 @@
24	24
25	25	#define FW_RATIO_MAX 8
26	26	#define FW_RATIO_MIN 1
	27	+#define MAXBURST_PER_FIFO 8
	28	+
	29	+#define DEFAULT_FS 48000
	30	+#define TIMEOUT_US 1000
	31	+#define WAIT_TIME_MS_MAX 10000
	32	+#define QUIRK_ALWAYS_ON BIT(0)
27	33
28	34	enum fpw_mode {
29	35	FPW_ONE_BCLK_WIDTH,
..	..	@@ -41,14 +47,30 @@
41	47	struct snd_dmaengine_dai_dma_data capture_dma_data;
42	48	struct snd_dmaengine_dai_dma_data playback_dma_data;
43	49	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
	50	+ unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
	51	+ unsigned int tx_lanes;
	52	+ unsigned int rx_lanes;
	53	+ unsigned int quirks;
44	54	enum fpw_mode fpw;
45		- int fw_ratio;
	55	+ int fw_ratio;
46	56	bool has_capture;
47	57	bool has_playback;
48	58	bool is_master_mode;
	59	+ bool is_tdm;
	60	+ bool is_clk_auto;
49	61	};
50	62
51		-static int sai_runtime_suspend(struct device *dev)
	63	+static const struct sai_of_quirks {
	64	+ char *quirk;
	65	+ int id;
	66	+} of_quirks[] = {
	67	+ {
	68	+ .quirk = "rockchip,always-on",
	69	+ .id = QUIRK_ALWAYS_ON,
	70	+ },
	71	+};
	72	+
	73	+static int rockchip_sai_runtime_suspend(struct device *dev)
52	74	{
53	75	struct rk_sai_dev *sai = dev_get_drvdata(dev);
54	76	unsigned int val;
..	..	@@ -62,20 +84,40 @@
62	84	SAI_XFER_FSS_DIS);
63	85
64	86	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
65		- (val & SAI_XFER_FS_IDLE), 10, 100);
	87	+ (val & SAI_XFER_FS_IDLE), 10, TIMEOUT_US);
66	88	if (ret < 0)
67	89	dev_warn(sai->dev, "Failed to idle FS\n");
68	90
69	91	regcache_cache_only(sai->regmap, true);
	92	+ /*
	93	+ * After FS idle, should wait at least 2 BCLK cycle to make sure
	94	+ * the CLK gate operation done, and then disable mclk.
	95	+ *
	96	+ * Otherwise, the BCLK is still ungated. once the mclk is enabled,
	97	+ * there maybe a risk that a few BCLK cycle leak. especially for
	98	+ * low speed situation, such as 8k samplerate.
	99	+ *
	100	+ * The best way is to use delay per samplerate, but, the max time
	101	+ * is quite a tiny value, so, let's make it simple to use the max
	102	+ * time.
	103	+ *
	104	+ * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
	105	+ */
	106	+ udelay(40);
70	107	clk_disable_unprepare(sai->mclk);
	108	+ clk_disable_unprepare(sai->hclk);
71	109
72	110	return 0;
73	111	}
74	112
75		-static int sai_runtime_resume(struct device *dev)
	113	+static int rockchip_sai_runtime_resume(struct device *dev)
76	114	{
77	115	struct rk_sai_dev *sai = dev_get_drvdata(dev);
78	116	int ret;
	117	+
	118	+ ret = clk_prepare_enable(sai->hclk);
	119	+ if (ret)
	120	+ goto err_hclk;
79	121
80	122	ret = clk_prepare_enable(sai->mclk);
81	123	if (ret)
..	..	@@ -87,7 +129,7 @@
87	129	if (ret)
88	130	goto err_regmap;
89	131
90		- if (sai->is_master_mode)
	132	+ if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode)
91	133	regmap_update_bits(sai->regmap, SAI_XFER,
92	134	SAI_XFER_CLK_MASK \|
93	135	SAI_XFER_FSS_MASK,
..	..	@@ -99,6 +141,8 @@
99	141	err_regmap:
100	142	clk_disable_unprepare(sai->mclk);
101	143	err_mclk:
	144	+ clk_disable_unprepare(sai->hclk);
	145	+err_hclk:
102	146	return ret;
103	147	}
104	148
..	..	@@ -178,7 +222,7 @@
178	222
179	223	regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
180	224	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
181		- !(val & clr), 10, 100);
	225	+ !(val & clr), 10, TIMEOUT_US);
182	226	if (ret < 0) {
183	227	dev_warn(sai->dev, "Failed to clear %u\n", clr);
184	228	goto reset;
..	..	@@ -224,7 +268,7 @@
224	268
225	269	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
226	270	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
227		- (val & idle), 10, 100);
	271	+ (val & idle), 10, TIMEOUT_US);
228	272	if (ret < 0)
229	273	dev_warn(sai->dev, "Failed to idle stream %d\n", stream);
230	274
..	..	@@ -359,19 +403,42 @@
359	403	return ret;
360	404	}
361	405
	406	+static unsigned int rockchip_sai_lanes_auto(struct snd_pcm_hw_params *params,
	407	+ struct snd_soc_dai *dai)
	408	+{
	409	+ struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	410	+ unsigned int lanes = 1;
	411	+
	412	+ if (!sai->is_tdm)
	413	+ lanes = DIV_ROUND_UP(params_channels(params), 2);
	414	+
	415	+ return lanes;
	416	+}
	417	+
362	418	static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
363	419	struct snd_pcm_hw_params *params,
364	420	struct snd_soc_dai *dai)
365	421	{
366	422	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	423	+ struct snd_dmaengine_dai_dma_data *dma_data;
367	424	unsigned int mclk_rate, bclk_rate, div_bclk;
368	425	unsigned int ch_per_lane, lanes, slot_width;
369	426	unsigned int val, fscr, reg;
370	427
371		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	428	+ dma_data = snd_soc_dai_get_dma_data(dai, substream);
	429	+ dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
	430	+
	431	+ lanes = rockchip_sai_lanes_auto(params, dai);
	432	+
	433	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
372	434	reg = SAI_TXCR;
373		- else
	435	+ if (sai->tx_lanes)
	436	+ lanes = sai->tx_lanes;
	437	+ } else {
374	438	reg = SAI_RXCR;
	439	+ if (sai->rx_lanes)
	440	+ lanes = sai->rx_lanes;
	441	+ }
375	442
376	443	switch (params_format(params)) {
377	444	case SNDRV_PCM_FORMAT_S8:
..	..	@@ -385,18 +452,20 @@
385	452	val = SAI_XCR_VDW(24);
386	453	break;
387	454	case SNDRV_PCM_FORMAT_S32_LE:
	455	+ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
388	456	val = SAI_XCR_VDW(32);
389	457	break;
390	458	default:
391	459	return -EINVAL;
392	460	}
393	461
394		- regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK, val);
	462	+ val \|= SAI_XCR_CSR(lanes);
	463	+
	464	+ regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK \| SAI_XCR_CSR_MASK, val);
395	465
396	466	regmap_read(sai->regmap, reg, &val);
397	467
398	468	slot_width = SAI_XCR_SBW_V(val);
399		- lanes = SAI_XCR_CSR_V(val);
400	469	ch_per_lane = params_channels(params) / lanes;
401	470
402	471	regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK,
..	..	@@ -424,6 +493,8 @@
424	493
425	494	if (sai->is_master_mode) {
426	495	bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
	496	+ if (sai->is_clk_auto)
	497	+ clk_set_rate(sai->mclk, bclk_rate);
427	498	mclk_rate = clk_get_rate(sai->mclk);
428	499	if (mclk_rate < bclk_rate) {
429	500	dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
..	..	@@ -435,6 +506,22 @@
435	506
436	507	regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
437	508	SAI_CKR_MDIV(div_bclk));
	509	+ /*
	510	+ * Should wait for one BCLK ready after DIV and then ungate
	511	+ * output clk to achieve the clean clk.
	512	+ *
	513	+ * The best way is to use delay per samplerate, but, the max time
	514	+ * is quite a tiny value, so, let's make it simple to use the max
	515	+ * time.
	516	+ *
	517	+ * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK)
	518	+ */
	519	+ udelay(20);
	520	+ regmap_update_bits(sai->regmap, SAI_XFER,
	521	+ SAI_XFER_CLK_MASK \|
	522	+ SAI_XFER_FSS_MASK,
	523	+ SAI_XFER_CLK_EN \|
	524	+ SAI_XFER_FSS_EN);
438	525	}
439	526
440	527	return 0;
..	..	@@ -471,7 +558,7 @@
471	558	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
472	559	int ret;
473	560
474		- if (!freq)
	561	+ if (!freq \|\| sai->is_clk_auto)
475	562	return 0;
476	563
477	564	ret = clk_set_rate(sai->mclk, freq);
..	..	@@ -496,11 +583,15 @@
496	583	struct snd_soc_dai *dai)
497	584	{
498	585	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
	586	+ int stream = substream->stream;
499	587
500		- if (sai->substreams[substream->stream])
	588	+ if (sai->substreams[stream])
501	589	return -EBUSY;
502	590
503		- sai->substreams[substream->stream] = substream;
	591	+ if (sai->wait_time[stream])
	592	+ substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]);
	593	+
	594	+ sai->substreams[stream] = substream;
504	595
505	596	return 0;
506	597	}
..	..	@@ -525,6 +616,8 @@
525	616	regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK,
526	617	SAI_XCR_SBW(slot_width));
527	618	pm_runtime_put(dai->dev);
	619	+
	620	+ sai->is_tdm = true;
528	621
529	622	return 0;
530	623	}
..	..	@@ -695,11 +788,12 @@
695	788	dai->playback.formats = SNDRV_PCM_FMTBIT_S8 \|
696	789	SNDRV_PCM_FMTBIT_S16_LE \|
697	790	SNDRV_PCM_FMTBIT_S24_LE \|
698		- SNDRV_PCM_FMTBIT_S32_LE;
	791	+ SNDRV_PCM_FMTBIT_S32_LE \|
	792	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
699	793
700	794	sai->playback_dma_data.addr = res->start + SAI_TXDR;
701	795	sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
702		- sai->playback_dma_data.maxburst = 8;
	796	+ sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
703	797	}
704	798
705	799	if (sai->has_capture) {
..	..	@@ -710,11 +804,12 @@
710	804	dai->capture.formats = SNDRV_PCM_FMTBIT_S8 \|
711	805	SNDRV_PCM_FMTBIT_S16_LE \|
712	806	SNDRV_PCM_FMTBIT_S24_LE \|
713		- SNDRV_PCM_FMTBIT_S32_LE;
	807	+ SNDRV_PCM_FMTBIT_S32_LE \|
	808	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
714	809
715	810	sai->capture_dma_data.addr = res->start + SAI_RXDR;
716	811	sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
717		- sai->capture_dma_data.maxburst = 8;
	812	+ sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
718	813	}
719	814
720	815	regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK,
..	..	@@ -728,8 +823,8 @@
728	823	return 0;
729	824	}
730	825
731		-static const char * const tcsr_text[] = { "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
732		-static const char * const rcsr_text[] = { "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
	826	+static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
	827	+static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
733	828	static const char * const edge_text[] = { "Rising Edge", "Dual Edge" };
734	829	static const char * const edge_shift_text[] = { "Normal", "Shift 1 Edge" };
735	830
..	..	@@ -743,8 +838,8 @@
743	838	static const char * const vdj_text[] = { "Right J", "Left J" };
744	839
745	840	static const char * const sbw_text[] = {
746		- " 0", " 0", " 0", " 0", " 0", " 0", " 0", " 8",
747		- " 9", "10", "11", "12", "13", "14", "15", "16",
	841	+ "0", "0", "0", "0", "0", "0", "0", "8",
	842	+ "9", "10", "11", "12", "13", "14", "15", "16",
748	843	"17", "18", "19", "20", "21", "22", "23", "24",
749	844	"25", "26", "27", "28", "29", "30", "31", "32", };
750	845
..	..	@@ -752,7 +847,7 @@
752	847
753	848	static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
754	849
755		-static const char * const mss_text[] = { "Master", "Slave" };
	850	+static const char * const mss_text[] = { "Slave", "Master" };
756	851
757	852	static const char * const ckp_text[] = { "Normal", "Inverted" };
758	853
..	..	@@ -771,7 +866,8 @@
771	866
772	867	/* TXCR */
773	868	static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
774		-static SOC_ENUM_SINGLE_DECL(tcsr_enum, SAI_TXCR, 20, tcsr_text);
	869	+static const struct soc_enum tx_lanes_enum =
	870	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
775	871	static SOC_ENUM_SINGLE_DECL(tsjm_enum, SAI_TXCR, 19, sjm_text);
776	872	static SOC_ENUM_SINGLE_DECL(tfbm_enum, SAI_TXCR, 18, fbm_text);
777	873	static SOC_ENUM_SINGLE_DECL(tvdj_enum, SAI_TXCR, 10, vdj_text);
..	..	@@ -786,7 +882,8 @@
786	882
787	883	/* RXCR */
788	884	static SOC_ENUM_SINGLE_DECL(rsft_enum, SAI_RXCR, 22, edge_shift_text);
789		-static SOC_ENUM_SINGLE_DECL(rcsr_enum, SAI_RXCR, 20, rcsr_text);
	885	+static const struct soc_enum rx_lanes_enum =
	886	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
790	887	static SOC_ENUM_SINGLE_DECL(rsjm_enum, SAI_RXCR, 19, sjm_text);
791	888	static SOC_ENUM_SINGLE_DECL(rfbm_enum, SAI_RXCR, 18, fbm_text);
792	889	static SOC_ENUM_SINGLE_DECL(rvdj_enum, SAI_RXCR, 10, vdj_text);
..	..	@@ -797,7 +894,8 @@
797	894	static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
798	895
799	896	/* CKR */
800		-static SOC_ENUM_SINGLE_DECL(mss_switch, SAI_CKR, 2, mss_text);
	897	+static const struct soc_enum mss_switch =
	898	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
801	899	static SOC_ENUM_SINGLE_DECL(sp_switch, SAI_CKR, 1, ckp_text);
802	900	static SOC_ENUM_SINGLE_DECL(fp_switch, SAI_CKR, 0, ckp_text);
803	901
..	..	@@ -874,19 +972,223 @@
874	972	return 1;
875	973	}
876	974
	975	+static int rockchip_sai_tx_lanes_get(struct snd_kcontrol *kcontrol,
	976	+ struct snd_ctl_elem_value *ucontrol)
	977	+{
	978	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	979	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	980	+
	981	+ ucontrol->value.enumerated.item[0] = sai->tx_lanes;
	982	+
	983	+ return 0;
	984	+}
	985	+
	986	+static int rockchip_sai_tx_lanes_put(struct snd_kcontrol *kcontrol,
	987	+ struct snd_ctl_elem_value *ucontrol)
	988	+{
	989	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	990	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	991	+ int num;
	992	+
	993	+ num = ucontrol->value.enumerated.item[0];
	994	+ if (num >= ARRAY_SIZE(tx_lanes_text))
	995	+ return -EINVAL;
	996	+
	997	+ sai->tx_lanes = num;
	998	+
	999	+ return 1;
	1000	+}
	1001	+
	1002	+static int rockchip_sai_rx_lanes_get(struct snd_kcontrol *kcontrol,
	1003	+ struct snd_ctl_elem_value *ucontrol)
	1004	+{
	1005	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1006	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1007	+
	1008	+ ucontrol->value.enumerated.item[0] = sai->rx_lanes;
	1009	+
	1010	+ return 0;
	1011	+}
	1012	+
	1013	+static int rockchip_sai_rx_lanes_put(struct snd_kcontrol *kcontrol,
	1014	+ struct snd_ctl_elem_value *ucontrol)
	1015	+{
	1016	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1017	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1018	+ int num;
	1019	+
	1020	+ num = ucontrol->value.enumerated.item[0];
	1021	+ if (num >= ARRAY_SIZE(rx_lanes_text))
	1022	+ return -EINVAL;
	1023	+
	1024	+ sai->rx_lanes = num;
	1025	+
	1026	+ return 1;
	1027	+}
	1028	+
	1029	+static int rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
	1030	+ struct snd_ctl_elem_value *ucontrol)
	1031	+{
	1032	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1033	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1034	+
	1035	+ ucontrol->value.enumerated.item[0] = sai->is_master_mode;
	1036	+
	1037	+ return 0;
	1038	+}
	1039	+
	1040	+static int rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
	1041	+ struct snd_ctl_elem_value *ucontrol)
	1042	+{
	1043	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1044	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1045	+ bool mss;
	1046	+
	1047	+ /* MUST: do not update mode while stream is running */
	1048	+ if (snd_soc_component_active(component))
	1049	+ return -EPERM;
	1050	+
	1051	+ mss = !!ucontrol->value.enumerated.item[0];
	1052	+ if (mss == sai->is_master_mode)
	1053	+ return 0;
	1054	+
	1055	+ sai->is_master_mode = mss;
	1056	+
	1057	+ pm_runtime_get_sync(sai->dev);
	1058	+ if (sai->is_master_mode) {
	1059	+ /* Switch from Slave to Master */
	1060	+ regmap_update_bits(sai->regmap, SAI_CKR,
	1061	+ SAI_CKR_MSS_MASK,
	1062	+ SAI_CKR_MSS_MASTER);
	1063	+ regmap_update_bits(sai->regmap, SAI_XFER,
	1064	+ SAI_XFER_CLK_MASK \|
	1065	+ SAI_XFER_FSS_MASK,
	1066	+ SAI_XFER_CLK_EN \|
	1067	+ SAI_XFER_FSS_EN);
	1068	+ } else {
	1069	+ /* Switch from Master to Slave */
	1070	+ regmap_update_bits(sai->regmap, SAI_CKR,
	1071	+ SAI_CKR_MSS_MASK,
	1072	+ SAI_CKR_MSS_SLAVE);
	1073	+ regmap_update_bits(sai->regmap, SAI_XFER,
	1074	+ SAI_XFER_CLK_MASK \|
	1075	+ SAI_XFER_FSS_MASK,
	1076	+ SAI_XFER_CLK_DIS \|
	1077	+ SAI_XFER_FSS_DIS);
	1078	+ }
	1079	+ pm_runtime_put(sai->dev);
	1080	+
	1081	+ return 1;
	1082	+}
	1083	+
	1084	+static int rockchip_sai_clk_auto_get(struct snd_kcontrol *kcontrol,
	1085	+ struct snd_ctl_elem_value *ucontrol)
	1086	+{
	1087	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1088	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1089	+
	1090	+ ucontrol->value.integer.value[0] = sai->is_clk_auto;
	1091	+
	1092	+ return 0;
	1093	+}
	1094	+
	1095	+static int rockchip_sai_clk_auto_put(struct snd_kcontrol *kcontrol,
	1096	+ struct snd_ctl_elem_value *ucontrol)
	1097	+{
	1098	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1099	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1100	+ bool clk_auto = ucontrol->value.integer.value[0];
	1101	+
	1102	+ if (clk_auto == sai->is_clk_auto)
	1103	+ return 0;
	1104	+
	1105	+ sai->is_clk_auto = clk_auto;
	1106	+
	1107	+ return 1;
	1108	+}
	1109	+
	1110	+static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
	1111	+ struct snd_ctl_elem_info *uinfo)
	1112	+{
	1113	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	1114	+ uinfo->count = 1;
	1115	+ uinfo->value.integer.min = 0;
	1116	+ uinfo->value.integer.max = WAIT_TIME_MS_MAX;
	1117	+ uinfo->value.integer.step = 1;
	1118	+
	1119	+ return 0;
	1120	+}
	1121	+
	1122	+static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
	1123	+ struct snd_ctl_elem_value *ucontrol)
	1124	+{
	1125	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1126	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1127	+
	1128	+ ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
	1129	+
	1130	+ return 0;
	1131	+}
	1132	+
	1133	+static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
	1134	+ struct snd_ctl_elem_value *ucontrol)
	1135	+{
	1136	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1137	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1138	+
	1139	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	1140	+ return -EINVAL;
	1141	+
	1142	+ sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
	1143	+
	1144	+ return 1;
	1145	+}
	1146	+
	1147	+static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
	1148	+ struct snd_ctl_elem_value *ucontrol)
	1149	+{
	1150	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1151	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1152	+
	1153	+ ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
	1154	+
	1155	+ return 0;
	1156	+}
	1157	+
	1158	+static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
	1159	+ struct snd_ctl_elem_value *ucontrol)
	1160	+{
	1161	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1162	+ struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
	1163	+
	1164	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	1165	+ return -EINVAL;
	1166	+
	1167	+ sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
	1168	+
	1169	+ return 1;
	1170	+}
	1171	+
	1172	+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
	1173	+{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
	1174	+ .info = rockchip_sai_wait_time_info, \
	1175	+ .get = xhandler_get, .put = xhandler_put }
	1176	+
877	1177	static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
878	1178
879	1179	static const struct snd_kcontrol_new rockchip_sai_controls[] = {
880	1180
881	1181	SOC_ENUM("Transmit Edge Shift", tsft_enum),
882		- SOC_ENUM("Transmit SDOx Select", tcsr_enum),
	1182	+ SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
	1183	+ rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
883	1184	SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
884	1185	SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
885	1186	SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
886	1187	SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
887	1188
888	1189	SOC_ENUM("Receive Edge Shift", rsft_enum),
889		- SOC_ENUM("Receive SDIx Select", rcsr_enum),
	1190	+ SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
	1191	+ rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
890	1192	SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
891	1193	SOC_ENUM("Receive First Bit Mode", rfbm_enum),
892	1194	SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
..	..	@@ -903,7 +1205,8 @@
903	1205	SOC_ENUM("Receive Mono Switch", rmono_switch),
904	1206	SOC_ENUM("Transmit Mono Switch", tmono_switch),
905	1207
906		- SOC_ENUM("Master / Slave Mode Select", mss_switch),
	1208	+ SOC_ENUM_EXT("Master / Slave Mode Select", mss_switch,
	1209	+ rockchip_sai_mss_get, rockchip_sai_mss_put),
907	1210	SOC_ENUM("Sclk Polarity", sp_switch),
908	1211	SOC_ENUM("Frame Sync Polarity", fp_switch),
909	1212
..	..	@@ -930,6 +1233,17 @@
930	1233	0, 8192, 0, fs_shift_tlv),
931	1234	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
932	1235	0, 8192, 0, fs_shift_tlv),
	1236	+
	1237	+ SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
	1238	+ rockchip_sai_clk_auto_get,
	1239	+ rockchip_sai_clk_auto_put),
	1240	+
	1241	+ SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
	1242	+ rockchip_sai_rd_wait_time_get,
	1243	+ rockchip_sai_rd_wait_time_put),
	1244	+ SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
	1245	+ rockchip_sai_wr_wait_time_get,
	1246	+ rockchip_sai_wr_wait_time_put),
933	1247	};
934	1248
935	1249	static const struct snd_soc_component_driver rockchip_sai_component = {
..	..	@@ -966,6 +1280,50 @@
966	1280	return IRQ_HANDLED;
967	1281	}
968	1282
	1283	+static int rockchip_sai_keep_clk_always_on(struct rk_sai_dev *sai)
	1284	+{
	1285	+ unsigned int mclk_rate, bclk_rate, div_bclk;
	1286	+
	1287	+ sai->is_master_mode = true;
	1288	+
	1289	+ /* init I2S fmt default */
	1290	+ rockchip_sai_fmt_create(sai, SND_SOC_DAIFMT_I2S);
	1291	+
	1292	+ regmap_update_bits(sai->regmap, SAI_FSCR,
	1293	+ SAI_FSCR_FW_MASK \|
	1294	+ SAI_FSCR_FPW_MASK,
	1295	+ SAI_FSCR_FW(64) \|
	1296	+ SAI_FSCR_FPW(32));
	1297	+
	1298	+ mclk_rate = clk_get_rate(sai->mclk);
	1299	+ bclk_rate = DEFAULT_FS * 64;
	1300	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	1301	+
	1302	+ regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
	1303	+ SAI_CKR_MDIV(div_bclk));
	1304	+
	1305	+ pm_runtime_forbid(sai->dev);
	1306	+
	1307	+ dev_info(sai->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
	1308	+ mclk_rate, bclk_rate, DEFAULT_FS);
	1309	+
	1310	+ return 0;
	1311	+}
	1312	+
	1313	+static int rockchip_sai_parse_quirks(struct rk_sai_dev *sai)
	1314	+{
	1315	+ int ret = 0, i = 0;
	1316	+
	1317	+ for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
	1318	+ if (device_property_read_bool(sai->dev, of_quirks[i].quirk))
	1319	+ sai->quirks \|= of_quirks[i].id;
	1320	+
	1321	+ if (sai->quirks & QUIRK_ALWAYS_ON)
	1322	+ ret = rockchip_sai_keep_clk_always_on(sai);
	1323	+
	1324	+ return ret;
	1325	+}
	1326	+
969	1327	static int rockchip_sai_probe(struct platform_device *pdev)
970	1328	{
971	1329	struct device_node *node = pdev->dev.of_node;
..	..	@@ -981,6 +1339,8 @@
981	1339
982	1340	sai->dev = &pdev->dev;
983	1341	sai->fw_ratio = 1;
	1342	+ /* match to register default */
	1343	+ sai->is_master_mode = true;
984	1344	dev_set_drvdata(&pdev->dev, sai);
985	1345
986	1346	sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
..	..	@@ -1000,7 +1360,7 @@
1000	1360	if (IS_ERR(sai->regmap))
1001	1361	return PTR_ERR(sai->regmap);
1002	1362
1003		- irq = platform_get_irq(pdev, 0);
	1363	+ irq = platform_get_irq_optional(pdev, 0);
1004	1364	if (irq > 0) {
1005	1365	ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
1006	1366	IRQF_SHARED, node->name, sai);
..	..	@@ -1022,13 +1382,13 @@
1022	1382	return PTR_ERR(sai->hclk);
1023	1383	}
1024	1384
1025		- ret = clk_prepare_enable(sai->hclk);
	1385	+ ret = rockchip_sai_parse_quirks(sai);
1026	1386	if (ret)
1027	1387	return ret;
1028	1388
1029	1389	pm_runtime_enable(&pdev->dev);
1030	1390	if (!pm_runtime_enabled(&pdev->dev)) {
1031		- ret = sai_runtime_resume(&pdev->dev);
	1391	+ ret = rockchip_sai_runtime_resume(&pdev->dev);
1032	1392	if (ret)
1033	1393	goto err_runtime_disable;
1034	1394	}
..	..	@@ -1043,6 +1403,11 @@
1043	1403	if (ret)
1044	1404	goto err_runtime_suspend;
1045	1405
	1406	+ if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) {
	1407	+ dev_info(&pdev->dev, "Used for Multi-DAI\n");
	1408	+ return 0;
	1409	+ }
	1410	+
1046	1411	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1047	1412	if (ret)
1048	1413	goto err_runtime_suspend;
..	..	@@ -1051,29 +1416,49 @@
1051	1416
1052	1417	err_runtime_suspend:
1053	1418	if (!pm_runtime_status_suspended(&pdev->dev))
1054		- sai_runtime_suspend(&pdev->dev);
	1419	+ rockchip_sai_runtime_suspend(&pdev->dev);
1055	1420	err_runtime_disable:
1056	1421	pm_runtime_disable(&pdev->dev);
1057		- clk_disable_unprepare(sai->hclk);
1058	1422
1059	1423	return ret;
1060	1424	}
1061	1425
1062	1426	static int rockchip_sai_remove(struct platform_device *pdev)
1063	1427	{
1064		- struct rk_sai_dev *sai = dev_get_drvdata(&pdev->dev);
1065		-
1066	1428	pm_runtime_disable(&pdev->dev);
1067	1429	if (!pm_runtime_status_suspended(&pdev->dev))
1068		- sai_runtime_suspend(&pdev->dev);
1069		-
1070		- clk_disable_unprepare(sai->hclk);
	1430	+ rockchip_sai_runtime_suspend(&pdev->dev);
1071	1431
1072	1432	return 0;
1073	1433	}
1074	1434
	1435	+#ifdef CONFIG_PM_SLEEP
	1436	+static int rockchip_sai_suspend(struct device *dev)
	1437	+{
	1438	+ struct rk_sai_dev *sai = dev_get_drvdata(dev);
	1439	+
	1440	+ regcache_mark_dirty(sai->regmap);
	1441	+
	1442	+ return 0;
	1443	+}
	1444	+
	1445	+static int rockchip_sai_resume(struct device *dev)
	1446	+{
	1447	+ struct rk_sai_dev *sai = dev_get_drvdata(dev);
	1448	+ int ret = pm_runtime_resume_and_get(dev);
	1449	+
	1450	+ if (ret < 0)
	1451	+ return ret;
	1452	+ ret = regcache_sync(sai->regmap);
	1453	+ pm_runtime_put(dev);
	1454	+
	1455	+ return ret;
	1456	+}
	1457	+#endif /* CONFIG_PM_SLEEP */
	1458	+
1075	1459	static const struct dev_pm_ops rockchip_sai_pm_ops = {
1076		- SET_RUNTIME_PM_OPS(sai_runtime_suspend, sai_runtime_resume, NULL)
	1460	+ SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
	1461	+ SET_SYSTEM_SLEEP_PM_OPS(rockchip_sai_suspend, rockchip_sai_resume)
1077	1462	};
1078	1463
1079	1464	static struct platform_driver rockchip_sai_driver = {