~hc/RK356X_SDK_RELEASE.git

..	..	@@ -27,6 +27,7 @@
27	27	#include <sound/dmaengine_pcm.h>
28	28
29	29	#include "rockchip_i2s_tdm.h"
	30	+#include "rockchip_dlp.h"
30	31
31	32	#define DRV_NAME "rockchip-i2s-tdm"
32	33
..	..	@@ -35,10 +36,15 @@
35	36	#endif
36	37
37	38	#define DEFAULT_MCLK_FS 256
	39	+#define DEFAULT_FS 48000
38	40	#define CH_GRP_MAX 4 /* The max channel 8 / 2 */
39	41	#define MULTIPLEX_CH_MAX 10
40	42	#define CLK_PPM_MIN (-1000)
41	43	#define CLK_PPM_MAX (1000)
	44	+#define MAXBURST_PER_FIFO 8
	45	+
	46	+#define QUIRK_ALWAYS_ON BIT(0)
	47	+#define QUIRK_HDMI_PATH BIT(1)
42	48
43	49	struct txrx_config {
44	50	u32 addr;
..	..	@@ -79,6 +85,7 @@
79	85	struct regmap *grf;
80	86	struct snd_dmaengine_dai_dma_data capture_dma_data;
81	87	struct snd_dmaengine_dai_dma_data playback_dma_data;
	88	+ struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
82	89	struct reset_control *tx_reset;
83	90	struct reset_control *rx_reset;
84	91	const struct rk_i2s_soc_data *soc_data;
..	..	@@ -102,9 +109,24 @@
102	109	unsigned int clk_trcm;
103	110	unsigned int i2s_sdis[CH_GRP_MAX];
104	111	unsigned int i2s_sdos[CH_GRP_MAX];
	112	+ unsigned int quirks;
105	113	int clk_ppm;
106	114	atomic_t refcount;
107	115	spinlock_t lock; /* xfer lock */
	116	+};
	117	+
	118	+static struct i2s_of_quirks {
	119	+ char *quirk;
	120	+ int id;
	121	+} of_quirks[] = {
	122	+ {
	123	+ .quirk = "rockchip,always-on",
	124	+ .id = QUIRK_ALWAYS_ON,
	125	+ },
	126	+ {
	127	+ .quirk = "rockchip,hdmi-path",
	128	+ .id = QUIRK_HDMI_PATH,
	129	+ },
108	130	};
109	131
110	132	static int to_ch_num(unsigned int val)
..	..	@@ -134,10 +156,9 @@
134	156	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
135	157
136	158	regcache_cache_only(i2s_tdm->regmap, true);
137		- if (!IS_ERR(i2s_tdm->mclk_tx))
138		- clk_disable_unprepare(i2s_tdm->mclk_tx);
139		- if (!IS_ERR(i2s_tdm->mclk_rx))
140		- clk_disable_unprepare(i2s_tdm->mclk_rx);
	159	+
	160	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	161	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
141	162
142	163	return 0;
143	164	}
..	..	@@ -147,28 +168,45 @@
147	168	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
148	169	int ret;
149	170
150		- if (!IS_ERR(i2s_tdm->mclk_tx))
151		- clk_prepare_enable(i2s_tdm->mclk_tx);
152		- if (!IS_ERR(i2s_tdm->mclk_rx))
153		- clk_prepare_enable(i2s_tdm->mclk_rx);
	171	+ ret = clk_prepare_enable(i2s_tdm->mclk_tx);
	172	+ if (ret)
	173	+ goto err_mclk_tx;
	174	+
	175	+ ret = clk_prepare_enable(i2s_tdm->mclk_rx);
	176	+ if (ret)
	177	+ goto err_mclk_rx;
154	178
155	179	regcache_cache_only(i2s_tdm->regmap, false);
156	180	regcache_mark_dirty(i2s_tdm->regmap);
157		-
158	181	ret = regcache_sync(i2s_tdm->regmap);
159		- if (ret) {
160		- if (!IS_ERR(i2s_tdm->mclk_tx))
161		- clk_disable_unprepare(i2s_tdm->mclk_tx);
162		- if (!IS_ERR(i2s_tdm->mclk_rx))
163		- clk_disable_unprepare(i2s_tdm->mclk_rx);
164		- }
	182	+ if (ret)
	183	+ goto err_regmap;
165	184
	185	+ return 0;
	186	+
	187	+err_regmap:
	188	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
	189	+err_mclk_rx:
	190	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	191	+err_mclk_tx:
166	192	return ret;
167	193	}
168	194
169	195	static inline struct rk_i2s_tdm_dev to_info(struct snd_soc_dai dai)
170	196	{
171	197	return snd_soc_dai_get_drvdata(dai);
	198	+}
	199	+
	200	+static inline bool is_stream_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	201	+{
	202	+ unsigned int val;
	203	+
	204	+ regmap_read(i2s_tdm->regmap, I2S_XFER, &val);
	205	+
	206	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	207	+ return (val & I2S_XFER_TXS_START);
	208	+ else
	209	+ return (val & I2S_XFER_RXS_START);
172	210	}
173	211
174	212	#ifdef HAVE_SYNC_RESET
..	..	@@ -180,7 +218,7 @@
180	218	#define writeq(v,c) ({ __iowmb(); __raw_writeq((__force u64) cpu_to_le64(v), c); })
181	219	#endif
182	220
183		-static void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
	221	+static void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
184	222	{
185	223	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
186	224	void __iomem cru_reset, addr;
..	..	@@ -229,7 +267,7 @@
229	267	writeq(val, addr);
230	268	break;
231	269	}
232		- /* fall through */
	270	+ fallthrough;
233	271	default:
234	272	local_irq_save(flags);
235	273	writel(BIT(tx_offset) \| (BIT(tx_offset) << 16),
..	..	@@ -243,7 +281,7 @@
243	281	udelay(10);
244	282	}
245	283
246		-static void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
	284	+static void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
247	285	{
248	286	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
249	287	void __iomem cru_reset, addr;
..	..	@@ -291,7 +329,7 @@
291	329	writeq(val, addr);
292	330	break;
293	331	}
294		- /* fall through */
	332	+ fallthrough;
295	333	default:
296	334	local_irq_save(flags);
297	335	writel((BIT(tx_offset) << 16),
..	..	@@ -309,94 +347,26 @@
309	347	* make sure both tx and rx are reset at the same time for sync lrck
310	348	* when clk_trcm > 0
311	349	*/
312		-static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
	350	+static void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
313	351	{
314		- rockchip_snd_xfer_reset_assert(i2s_tdm);
315		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
	352	+ rockchip_i2s_tdm_reset_assert(i2s_tdm);
	353	+ rockchip_i2s_tdm_reset_deassert(i2s_tdm);
316	354	}
317	355	#else
318		-static inline void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
	356	+static inline void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
319	357	{
320	358	}
321		-static inline void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
	359	+static inline void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
322	360	{
323	361	}
324		-static inline void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
	362	+static inline void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
325	363	{
326	364	}
327	365	#endif
328	366
329		-/* only used when clk_trcm > 0 */
330		-static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
331		- struct snd_soc_dai *dai, int on)
	367	+static void rockchip_i2s_tdm_reset(struct reset_control *rc)
332	368	{
333		- struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
334		- unsigned int val = 0;
335		- unsigned long flags;
336		- int retry = 10;
337		-
338		- spin_lock_irqsave(&i2s_tdm->lock, flags);
339		- if (on) {
340		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
342		- I2S_DMACR_TDE_ENABLE,
343		- I2S_DMACR_TDE_ENABLE);
344		- else
345		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
346		- I2S_DMACR_RDE_ENABLE,
347		- I2S_DMACR_RDE_ENABLE);
348		-
349		- if (atomic_inc_return(&i2s_tdm->refcount) == 1) {
350		- rockchip_snd_xfer_reset_assert(i2s_tdm);
351		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
352		- I2S_XFER_TXS_START \|
353		- I2S_XFER_RXS_START,
354		- I2S_XFER_TXS_START \|
355		- I2S_XFER_RXS_START);
356		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
357		- }
358		- } else {
359		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
360		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
361		- I2S_DMACR_TDE_ENABLE,
362		- I2S_DMACR_TDE_DISABLE);
363		- else
364		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
365		- I2S_DMACR_RDE_ENABLE,
366		- I2S_DMACR_RDE_DISABLE);
367		-
368		- if (atomic_dec_and_test(&i2s_tdm->refcount)) {
369		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
370		- I2S_XFER_TXS_START \|
371		- I2S_XFER_RXS_START,
372		- I2S_XFER_TXS_STOP \|
373		- I2S_XFER_RXS_STOP);
374		-
375		- udelay(150);
376		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
377		- I2S_CLR_TXC \| I2S_CLR_RXC,
378		- I2S_CLR_TXC \| I2S_CLR_RXC);
379		-
380		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
381		-
382		- /* Should wait for clear operation to finish */
383		- while (val) {
384		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
385		- retry--;
386		- if (!retry) {
387		- dev_info(i2s_tdm->dev, "reset txrx\n");
388		- rockchip_snd_xfer_sync_reset(i2s_tdm);
389		- break;
390		- }
391		- }
392		- }
393		- }
394		- spin_unlock_irqrestore(&i2s_tdm->lock, flags);
395		-}
396		-
397		-static void rockchip_snd_reset(struct reset_control *rc)
398		-{
399		- if (IS_ERR(rc))
	369	+ if (IS_ERR_OR_NULL(rc))
400	370	return;
401	371
402	372	reset_control_assert(rc);
..	..	@@ -407,92 +377,270 @@
407	377	udelay(10);
408	378	}
409	379
410		-static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
	380	+static int rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev *i2s_tdm,
	381	+ unsigned int clr)
411	382	{
	383	+ struct reset_control *rst = NULL;
412	384	unsigned int val = 0;
413		- int retry = 10;
	385	+ int ret = 0;
414	386
415		- if (on) {
416		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
417		- I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	387	+ switch (clr) {
	388	+ case I2S_CLR_TXC:
	389	+ rst = i2s_tdm->tx_reset;
	390	+ break;
	391	+ case I2S_CLR_RXC:
	392	+ rst = i2s_tdm->rx_reset;
	393	+ break;
	394	+ case I2S_CLR_TXC \| I2S_CLR_RXC:
	395	+ break;
	396	+ default:
	397	+ return -EINVAL;
	398	+ }
418	399
419		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
420		- I2S_XFER_TXS_START,
421		- I2S_XFER_TXS_START);
	400	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
	401	+ ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
	402	+ !(val & clr), 10, 100);
	403	+ if (ret == 0)
	404	+ return 0;
	405	+
	406	+ /*
	407	+ * Workaround for FIFO clear on SLAVE mode:
	408	+ *
	409	+ * A Suggest to do reset hclk domain and then do mclk
	410	+ * domain, especially for SLAVE mode without CLK in.
	411	+ * at last, recovery regmap config.
	412	+ *
	413	+ * B Suggest to switch to MASTER, and then do FIFO clr,
	414	+ * at last, bring back to SLAVE.
	415	+ *
	416	+ * Now we choose plan B here.
	417	+ */
	418	+ if (!i2s_tdm->is_master_mode)
	419	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	420	+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
	421	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
	422	+ ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
	423	+ !(val & clr), 10, 100);
	424	+ if (!i2s_tdm->is_master_mode)
	425	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	426	+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
	427	+
	428	+ if (ret < 0) {
	429	+ dev_warn(i2s_tdm->dev, "failed to clear %u on %s mode\n",
	430	+ clr, i2s_tdm->is_master_mode ? "master" : "slave");
	431	+ goto reset;
	432	+ }
	433	+
	434	+ return 0;
	435	+
	436	+reset:
	437	+ if (i2s_tdm->clk_trcm)
	438	+ rockchip_i2s_tdm_sync_reset(i2s_tdm);
	439	+ else
	440	+ rockchip_i2s_tdm_reset(rst);
	441	+
	442	+ return 0;
	443	+}
	444	+
	445	+/*
	446	+ * HDMI controller ignores the first FRAME_SYNC cycle, Lost one frame is no big deal
	447	+ * for LPCM, but it does matter for Bitstream (NLPCM/HBR), So, padding one frame
	448	+ * before xfer the real data to fix it.
	449	+ */
	450	+static void rockchip_i2s_tdm_tx_fifo_padding(struct rk_i2s_tdm_dev *i2s_tdm, bool en)
	451	+{
	452	+ unsigned int val, w, c, i;
	453	+
	454	+ if (!en)
	455	+ return;
	456	+
	457	+ regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
	458	+ w = ((val & I2S_TXCR_VDW_MASK) >> I2S_TXCR_VDW_SHIFT) + 1;
	459	+ c = to_ch_num(val & I2S_TXCR_CSR_MASK) * w / 32;
	460	+
	461	+ for (i = 0; i < c; i++)
	462	+ regmap_write(i2s_tdm->regmap, I2S_TXDR, 0x0);
	463	+}
	464	+
	465	+static void rockchip_i2s_tdm_fifo_xrun_detect(struct rk_i2s_tdm_dev *i2s_tdm,
	466	+ int stream, bool en)
	467	+{
	468	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	469	+ /* clear irq status which was asserted before TXUIE enabled */
	470	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	471	+ I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
	472	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	473	+ I2S_INTCR_TXUIE_MASK,
	474	+ I2S_INTCR_TXUIE(en));
422	475	} else {
423		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
424		- I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
425		-
426		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
427		- I2S_XFER_TXS_START,
428		- I2S_XFER_TXS_STOP);
429		-
430		- udelay(150);
431		- if (i2s_tdm->is_master_mode) {
432		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
433		- I2S_CLR_TXC,
434		- I2S_CLR_TXC);
435		-
436		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
437		-
438		- /* Should wait for clear operation to finish */
439		- while (val) {
440		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
441		- retry--;
442		- if (!retry) {
443		- dev_warn(i2s_tdm->dev, "reset tx\n");
444		- rockchip_snd_reset(i2s_tdm->tx_reset);
445		- break;
446		- }
447		- }
448		- } else {
449		- rockchip_snd_reset(i2s_tdm->tx_reset);
450		- }
	476	+ /* clear irq status which was asserted before RXOIE enabled */
	477	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	478	+ I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
	479	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	480	+ I2S_INTCR_RXOIE_MASK,
	481	+ I2S_INTCR_RXOIE(en));
451	482	}
452	483	}
453	484
454		-static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
	485	+static void rockchip_i2s_tdm_dma_ctrl(struct rk_i2s_tdm_dev *i2s_tdm,
	486	+ int stream, bool en)
455	487	{
456		- unsigned int val = 0;
457		- int retry = 10;
	488	+ if (!en)
	489	+ rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 0);
458	490
459		- if (on) {
	491	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	492	+ if (i2s_tdm->quirks & QUIRK_HDMI_PATH)
	493	+ rockchip_i2s_tdm_tx_fifo_padding(i2s_tdm, en);
	494	+
460	495	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
461		- I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
462		-
463		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
464		- I2S_XFER_RXS_START,
465		- I2S_XFER_RXS_START);
	496	+ I2S_DMACR_TDE_MASK,
	497	+ I2S_DMACR_TDE(en));
	498	+ /*
	499	+ * Explicitly delay 1 usec for dma to fill FIFO,
	500	+ * though there was a implied HW delay that around
	501	+ * half LRCK cycle (e.g. 2.6us@192k) from XFER-start
	502	+ * to FIFO-pop.
	503	+ *
	504	+ * 1 usec is enough to fill at lease 4 entry each FIFO
	505	+ * @192k 8ch 32bit situation.
	506	+ */
	507	+ udelay(1);
466	508	} else {
467	509	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
468		- I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
469		-
470		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
471		- I2S_XFER_RXS_START,
472		- I2S_XFER_RXS_STOP);
473		-
474		- udelay(150);
475		- if (i2s_tdm->is_master_mode) {
476		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
477		- I2S_CLR_RXC,
478		- I2S_CLR_RXC);
479		-
480		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
481		-
482		- /* Should wait for clear operation to finish */
483		- while (val) {
484		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
485		- retry--;
486		- if (!retry) {
487		- dev_warn(i2s_tdm->dev, "reset rx\n");
488		- rockchip_snd_reset(i2s_tdm->rx_reset);
489		- break;
490		- }
491		- }
492		- } else {
493		- rockchip_snd_reset(i2s_tdm->rx_reset);
494		- }
	510	+ I2S_DMACR_RDE_MASK,
	511	+ I2S_DMACR_RDE(en));
495	512	}
	513	+
	514	+ if (en)
	515	+ rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 1);
	516	+}
	517	+
	518	+static void rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev *i2s_tdm,
	519	+ int stream)
	520	+{
	521	+ if (i2s_tdm->clk_trcm) {
	522	+ rockchip_i2s_tdm_reset_assert(i2s_tdm);
	523	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	524	+ I2S_XFER_TXS_MASK \|
	525	+ I2S_XFER_RXS_MASK,
	526	+ I2S_XFER_TXS_START \|
	527	+ I2S_XFER_RXS_START);
	528	+ rockchip_i2s_tdm_reset_deassert(i2s_tdm);
	529	+ } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	530	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	531	+ I2S_XFER_TXS_MASK,
	532	+ I2S_XFER_TXS_START);
	533	+ } else {
	534	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	535	+ I2S_XFER_RXS_MASK,
	536	+ I2S_XFER_RXS_START);
	537	+ }
	538	+}
	539	+
	540	+static void rockchip_i2s_tdm_xfer_stop(struct rk_i2s_tdm_dev *i2s_tdm,
	541	+ int stream, bool force)
	542	+{
	543	+ unsigned int msk, val, clr;
	544	+
	545	+ if (i2s_tdm->quirks & QUIRK_ALWAYS_ON && !force)
	546	+ return;
	547	+
	548	+ if (i2s_tdm->clk_trcm) {
	549	+ msk = I2S_XFER_TXS_MASK \| I2S_XFER_RXS_MASK;
	550	+ val = I2S_XFER_TXS_STOP \| I2S_XFER_RXS_STOP;
	551	+ clr = I2S_CLR_TXC \| I2S_CLR_RXC;
	552	+ } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	553	+ msk = I2S_XFER_TXS_MASK;
	554	+ val = I2S_XFER_TXS_STOP;
	555	+ clr = I2S_CLR_TXC;
	556	+ } else {
	557	+ msk = I2S_XFER_RXS_MASK;
	558	+ val = I2S_XFER_RXS_STOP;
	559	+ clr = I2S_CLR_RXC;
	560	+ }
	561	+
	562	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
	563	+
	564	+ /* delay for LRCK signal integrity */
	565	+ udelay(150);
	566	+
	567	+ rockchip_i2s_tdm_clear(i2s_tdm, clr);
	568	+}
	569	+
	570	+static void rockchip_i2s_tdm_xfer_trcm_start(struct rk_i2s_tdm_dev *i2s_tdm)
	571	+{
	572	+ unsigned long flags;
	573	+
	574	+ spin_lock_irqsave(&i2s_tdm->lock, flags);
	575	+ if (atomic_inc_return(&i2s_tdm->refcount) == 1)
	576	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, 0);
	577	+ spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	578	+}
	579	+
	580	+static void rockchip_i2s_tdm_xfer_trcm_stop(struct rk_i2s_tdm_dev *i2s_tdm)
	581	+{
	582	+ unsigned long flags;
	583	+
	584	+ spin_lock_irqsave(&i2s_tdm->lock, flags);
	585	+ if (atomic_dec_and_test(&i2s_tdm->refcount))
	586	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, 0, false);
	587	+ spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	588	+}
	589	+
	590	+static void rockchip_i2s_tdm_trcm_pause(struct snd_pcm_substream *substream,
	591	+ struct rk_i2s_tdm_dev *i2s_tdm)
	592	+{
	593	+ int stream = substream->stream;
	594	+ int bstream = SNDRV_PCM_STREAM_LAST - stream;
	595	+
	596	+ /* disable dma for both tx and rx */
	597	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
	598	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 0);
	599	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, bstream, true);
	600	+}
	601	+
	602	+static void rockchip_i2s_tdm_trcm_resume(struct snd_pcm_substream *substream,
	603	+ struct rk_i2s_tdm_dev *i2s_tdm)
	604	+{
	605	+ int bstream = SNDRV_PCM_STREAM_LAST - substream->stream;
	606	+
	607	+ /*
	608	+ * just resume bstream, because current stream will be
	609	+ * startup in the trigger-cmd-START
	610	+ */
	611	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
	612	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, bstream);
	613	+}
	614	+
	615	+static void rockchip_i2s_tdm_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	616	+{
	617	+ /*
	618	+ * On HDMI-PATH-ALWAYS-ON situation, we almost keep XFER always on,
	619	+ * so, for new data start, suggested to STOP-CLEAR-START to make sure
	620	+ * data aligned.
	621	+ */
	622	+ if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
	623	+ (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
	624	+ (stream == SNDRV_PCM_STREAM_PLAYBACK)) {
	625	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
	626	+ }
	627	+
	628	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 1);
	629	+
	630	+ if (i2s_tdm->clk_trcm)
	631	+ rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
	632	+ else
	633	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, stream);
	634	+}
	635	+
	636	+static void rockchip_i2s_tdm_stop(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	637	+{
	638	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
	639	+
	640	+ if (i2s_tdm->clk_trcm)
	641	+ rockchip_i2s_tdm_xfer_trcm_stop(i2s_tdm);
	642	+ else
	643	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, false);
496	644	}
497	645
498	646	static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
..	..	@@ -513,6 +661,19 @@
513	661	case SND_SOC_DAIFMT_CBM_CFM:
514	662	val = I2S_CKR_MSS_SLAVE;
515	663	i2s_tdm->is_master_mode = false;
	664	+ /*
	665	+ * TRCM require TX/RX enabled at the same time, or need the one
	666	+ * which provide clk enabled at first for master mode.
	667	+ *
	668	+ * It is quite a different for slave mode which does not have
	669	+ * these restrictions, because the BCLK / LRCK are provided by
	670	+ * external master devices.
	671	+ *
	672	+ * So, we just set the right clk path value on TRCM register on
	673	+ * stage probe and then drop the trcm value to make TX / RX work
	674	+ * independently.
	675	+ */
	676	+ i2s_tdm->clk_trcm = 0;
516	677	break;
517	678	default:
518	679	ret = -EINVAL;
..	..	@@ -659,72 +820,6 @@
659	820	return ret;
660	821	}
661	822
662		-static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
663		- struct rk_i2s_tdm_dev *i2s_tdm)
664		-{
665		- int stream;
666		- unsigned int val = 0;
667		- int retry = 10;
668		-
669		- stream = SNDRV_PCM_STREAM_LAST - substream->stream;
670		- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
671		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
672		- I2S_DMACR_TDE_ENABLE,
673		- I2S_DMACR_TDE_DISABLE);
674		- else
675		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
676		- I2S_DMACR_RDE_ENABLE,
677		- I2S_DMACR_RDE_DISABLE);
678		-
679		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
680		- I2S_XFER_TXS_START \|
681		- I2S_XFER_RXS_START,
682		- I2S_XFER_TXS_STOP \|
683		- I2S_XFER_RXS_STOP);
684		-
685		- udelay(150);
686		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
687		- I2S_CLR_TXC \| I2S_CLR_RXC,
688		- I2S_CLR_TXC \| I2S_CLR_RXC);
689		-
690		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
691		-
692		- /* Should wait for clear operation to finish */
693		- while (val) {
694		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
695		- retry--;
696		- if (!retry) {
697		- dev_info(i2s_tdm->dev, "reset txrx\n");
698		- rockchip_snd_xfer_sync_reset(i2s_tdm);
699		- break;
700		- }
701		- }
702		-}
703		-
704		-static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
705		- struct rk_i2s_tdm_dev *i2s_tdm)
706		-{
707		- int stream;
708		-
709		- stream = SNDRV_PCM_STREAM_LAST - substream->stream;
710		- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
711		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
712		- I2S_DMACR_TDE_ENABLE,
713		- I2S_DMACR_TDE_ENABLE);
714		- else
715		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
716		- I2S_DMACR_RDE_ENABLE,
717		- I2S_DMACR_RDE_ENABLE);
718		-
719		- rockchip_snd_xfer_reset_assert(i2s_tdm);
720		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
721		- I2S_XFER_TXS_START \|
722		- I2S_XFER_RXS_START,
723		- I2S_XFER_TXS_START \|
724		- I2S_XFER_RXS_START);
725		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
726		-}
727		-
728	823	static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
729	824	struct clk *clk, unsigned long rate,
730	825	int ppm)
..	..	@@ -840,6 +935,41 @@
840	935	return ret;
841	936	}
842	937
	938	+static int rockchip_i2s_tdm_mclk_reparent(struct rk_i2s_tdm_dev *i2s_tdm)
	939	+{
	940	+ struct clk *parent;
	941	+ int ret = 0;
	942	+
	943	+ /* reparent to the same clk on TRCM mode */
	944	+ switch (i2s_tdm->clk_trcm) {
	945	+ case I2S_CKR_TRCM_TXONLY:
	946	+ parent = clk_get_parent(i2s_tdm->mclk_tx);
	947	+ /*
	948	+ * API clk_has_parent is not available yet on GKI, so we
	949	+ * use clk_set_parent directly and ignore the ret value.
	950	+ * if the API has addressed on GKI, should remove it.
	951	+ */
	952	+#ifdef CONFIG_NO_GKI
	953	+ if (clk_has_parent(i2s_tdm->mclk_rx, parent))
	954	+ ret = clk_set_parent(i2s_tdm->mclk_rx, parent);
	955	+#else
	956	+ clk_set_parent(i2s_tdm->mclk_rx, parent);
	957	+#endif
	958	+ break;
	959	+ case I2S_CKR_TRCM_RXONLY:
	960	+ parent = clk_get_parent(i2s_tdm->mclk_rx);
	961	+#ifdef CONFIG_NO_GKI
	962	+ if (clk_has_parent(i2s_tdm->mclk_tx, parent))
	963	+ ret = clk_set_parent(i2s_tdm->mclk_tx, parent);
	964	+#else
	965	+ clk_set_parent(i2s_tdm->mclk_tx, parent);
	966	+#endif
	967	+ break;
	968	+ }
	969	+
	970	+ return ret;
	971	+}
	972	+
843	973	static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
844	974	struct snd_pcm_substream *substream,
845	975	struct clk **mclk)
..	..	@@ -862,6 +992,10 @@
862	992	goto err;
863	993
864	994	ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
	995	+ if (ret)
	996	+ goto err;
	997	+
	998	+ ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
865	999	if (ret)
866	1000	goto err;
867	1001
..	..	@@ -895,6 +1029,9 @@
895	1029	unsigned int val = 0;
896	1030
897	1031	if (!i2s_tdm->io_multiplex)
	1032	+ return 0;
	1033	+
	1034	+ if (IS_ERR(i2s_tdm->grf))
898	1035	return 0;
899	1036
900	1037	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
..	..	@@ -1006,24 +1143,18 @@
1006	1143	return false;
1007	1144	}
1008	1145
1009		-static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
1010		- struct snd_soc_dai *dai,
1011		- unsigned int div_bclk,
1012		- unsigned int div_lrck,
1013		- unsigned int fmt)
	1146	+static int rockchip_i2s_tdm_params_trcm(struct snd_pcm_substream *substream,
	1147	+ struct snd_soc_dai *dai,
	1148	+ unsigned int div_bclk,
	1149	+ unsigned int div_lrck,
	1150	+ unsigned int fmt)
1014	1151	{
1015	1152	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1016	1153	unsigned long flags;
1017	1154
1018		- if (!i2s_tdm->clk_trcm)
1019		- return 0;
1020		-
1021		- if (!is_params_dirty(substream, dai, div_bclk, div_lrck, fmt))
1022		- return 0;
1023		-
1024	1155	spin_lock_irqsave(&i2s_tdm->lock, flags);
1025	1156	if (atomic_read(&i2s_tdm->refcount))
1026		- rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
	1157	+ rockchip_i2s_tdm_trcm_pause(substream, i2s_tdm);
1027	1158
1028	1159	regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1029	1160	I2S_CLKDIV_TXM_MASK \| I2S_CLKDIV_RXM_MASK,
..	..	@@ -1042,8 +1173,56 @@
1042	1173	fmt);
1043	1174
1044	1175	if (atomic_read(&i2s_tdm->refcount))
1045		- rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
	1176	+ rockchip_i2s_tdm_trcm_resume(substream, i2s_tdm);
1046	1177	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	1178	+
	1179	+ return 0;
	1180	+}
	1181	+
	1182	+static int rockchip_i2s_tdm_params(struct snd_pcm_substream *substream,
	1183	+ struct snd_soc_dai *dai,
	1184	+ unsigned int div_bclk,
	1185	+ unsigned int div_lrck,
	1186	+ unsigned int fmt)
	1187	+{
	1188	+ struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
	1189	+ int stream = substream->stream;
	1190	+
	1191	+ if (is_stream_active(i2s_tdm, stream))
	1192	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
	1193	+
	1194	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	1195	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	1196	+ I2S_CLKDIV_TXM_MASK,
	1197	+ I2S_CLKDIV_TXM(div_bclk));
	1198	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	1199	+ I2S_CKR_TSD_MASK,
	1200	+ I2S_CKR_TSD(div_lrck));
	1201	+ regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
	1202	+ I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	1203	+ fmt);
	1204	+ } else {
	1205	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	1206	+ I2S_CLKDIV_RXM_MASK,
	1207	+ I2S_CLKDIV_RXM(div_bclk));
	1208	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	1209	+ I2S_CKR_RSD_MASK,
	1210	+ I2S_CKR_RSD(div_lrck));
	1211	+ regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
	1212	+ I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	1213	+ fmt);
	1214	+ }
	1215	+
	1216	+ /*
	1217	+ * Bring back CLK ASAP after cfg changed to make SINK devices active
	1218	+ * on HDMI-PATH-ALWAYS-ON situation, this workaround for some TVs no
	1219	+ * sound issue. at the moment, it's 8K@60Hz display situation.
	1220	+ */
	1221	+ if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
	1222	+ (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
	1223	+ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) {
	1224	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	1225	+ }
1047	1226
1048	1227	return 0;
1049	1228	}
..	..	@@ -1110,29 +1289,31 @@
1110	1289	struct snd_soc_dai *dai)
1111	1290	{
1112	1291	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
	1292	+ struct snd_dmaengine_dai_dma_data *dma_data;
1113	1293	struct clk *mclk;
1114	1294	int ret = 0;
1115	1295	unsigned int val = 0;
1116	1296	unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
1117	1297
1118		- if (i2s_tdm->is_master_mode) {
1119		- if (i2s_tdm->mclk_calibrate)
1120		- rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
1121		- params_rate(params));
	1298	+ dma_data = snd_soc_dai_get_dma_data(dai, substream);
	1299	+ dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
1122	1300
1123		- ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
1124		- if (ret)
1125		- goto err;
	1301	+ if (i2s_tdm->mclk_calibrate)
	1302	+ rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
	1303	+ params_rate(params));
1126	1304
1127		- mclk_rate = clk_get_rate(mclk);
1128		- bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
1129		- if (!bclk_rate) {
1130		- ret = -EINVAL;
1131		- goto err;
1132		- }
1133		- div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1134		- div_lrck = bclk_rate / params_rate(params);
	1305	+ ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
	1306	+ if (ret)
	1307	+ goto err;
	1308	+
	1309	+ mclk_rate = clk_get_rate(mclk);
	1310	+ bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
	1311	+ if (!bclk_rate) {
	1312	+ ret = -EINVAL;
	1313	+ goto err;
1135	1314	}
	1315	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	1316	+ div_lrck = bclk_rate / params_rate(params);
1136	1317
1137	1318	switch (params_format(params)) {
1138	1319	case SNDRV_PCM_FORMAT_S8:
..	..	@@ -1148,6 +1329,7 @@
1148	1329	val \|= I2S_TXCR_VDW(24);
1149	1330	break;
1150	1331	case SNDRV_PCM_FORMAT_S32_LE:
	1332	+ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1151	1333	val \|= I2S_TXCR_VDW(32);
1152	1334	break;
1153	1335	default:
..	..	@@ -1160,29 +1342,13 @@
1160	1342	goto err;
1161	1343
1162	1344	val \|= ret;
1163		- if (i2s_tdm->clk_trcm) {
1164		- rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
1165		- } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1166		- regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1167		- I2S_CLKDIV_TXM_MASK,
1168		- I2S_CLKDIV_TXM(div_bclk));
1169		- regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1170		- I2S_CKR_TSD_MASK,
1171		- I2S_CKR_TSD(div_lrck));
1172		- regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1173		- I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
1174		- val);
1175		- } else {
1176		- regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1177		- I2S_CLKDIV_RXM_MASK,
1178		- I2S_CLKDIV_RXM(div_bclk));
1179		- regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1180		- I2S_CKR_RSD_MASK,
1181		- I2S_CKR_RSD(div_lrck));
1182		- regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1183		- I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
1184		- val);
1185		- }
	1345	+ if (!is_params_dirty(substream, dai, div_bclk, div_lrck, val))
	1346	+ return 0;
	1347	+
	1348	+ if (i2s_tdm->clk_trcm)
	1349	+ rockchip_i2s_tdm_params_trcm(substream, dai, div_bclk, div_lrck, val);
	1350	+ else
	1351	+ rockchip_i2s_tdm_params(substream, dai, div_bclk, div_lrck, val);
1186	1352
1187	1353	ret = rockchip_i2s_io_multiplex(substream, dai);
1188	1354
..	..	@@ -1200,22 +1366,12 @@
1200	1366	case SNDRV_PCM_TRIGGER_START:
1201	1367	case SNDRV_PCM_TRIGGER_RESUME:
1202	1368	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1203		- if (i2s_tdm->clk_trcm)
1204		- rockchip_snd_txrxctrl(substream, dai, 1);
1205		- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1206		- rockchip_snd_rxctrl(i2s_tdm, 1);
1207		- else
1208		- rockchip_snd_txctrl(i2s_tdm, 1);
	1369	+ rockchip_i2s_tdm_start(i2s_tdm, substream->stream);
1209	1370	break;
1210	1371	case SNDRV_PCM_TRIGGER_SUSPEND:
1211	1372	case SNDRV_PCM_TRIGGER_STOP:
1212	1373	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1213		- if (i2s_tdm->clk_trcm)
1214		- rockchip_snd_txrxctrl(substream, dai, 0);
1215		- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1216		- rockchip_snd_rxctrl(i2s_tdm, 0);
1217		- else
1218		- rockchip_snd_txctrl(i2s_tdm, 0);
	1374	+ rockchip_i2s_tdm_stop(i2s_tdm, substream->stream);
1219	1375	break;
1220	1376	default:
1221	1377	ret = -EINVAL;
..	..	@@ -1305,6 +1461,93 @@
1305	1461	.put = rockchip_i2s_tdm_clk_compensation_put,
1306	1462	};
1307	1463
	1464	+/* loopback mode select */
	1465	+enum {
	1466	+ LOOPBACK_MODE_DIS = 0,
	1467	+ LOOPBACK_MODE_1,
	1468	+ LOOPBACK_MODE_2,
	1469	+ LOOPBACK_MODE_2_SWAP,
	1470	+};
	1471	+
	1472	+static const char *const loopback_text[] = {
	1473	+ "Disabled",
	1474	+ "Mode1",
	1475	+ "Mode2",
	1476	+ "Mode2 Swap",
	1477	+};
	1478	+
	1479	+static SOC_ENUM_SINGLE_EXT_DECL(loopback_mode, loopback_text);
	1480	+
	1481	+static int rockchip_i2s_tdm_loopback_get(struct snd_kcontrol *kcontrol,
	1482	+ struct snd_ctl_elem_value *ucontrol)
	1483	+{
	1484	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1485	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1486	+ unsigned int reg = 0, mode = 0;
	1487	+
	1488	+ pm_runtime_get_sync(component->dev);
	1489	+ regmap_read(i2s_tdm->regmap, I2S_XFER, &reg);
	1490	+ pm_runtime_put(component->dev);
	1491	+
	1492	+ switch (reg & I2S_XFER_LP_MODE_MASK) {
	1493	+ case I2S_XFER_LP_MODE_2_SWAP:
	1494	+ mode = LOOPBACK_MODE_2_SWAP;
	1495	+ break;
	1496	+ case I2S_XFER_LP_MODE_2:
	1497	+ mode = LOOPBACK_MODE_2;
	1498	+ break;
	1499	+ case I2S_XFER_LP_MODE_1:
	1500	+ mode = LOOPBACK_MODE_1;
	1501	+ break;
	1502	+ default:
	1503	+ mode = LOOPBACK_MODE_DIS;
	1504	+ break;
	1505	+ }
	1506	+
	1507	+ ucontrol->value.enumerated.item[0] = mode;
	1508	+
	1509	+ return 0;
	1510	+}
	1511	+
	1512	+static int rockchip_i2s_tdm_loopback_put(struct snd_kcontrol *kcontrol,
	1513	+ struct snd_ctl_elem_value *ucontrol)
	1514	+{
	1515	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1516	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1517	+ unsigned int val = 0, mode = ucontrol->value.enumerated.item[0];
	1518	+
	1519	+ if (mode < LOOPBACK_MODE_DIS \|\|
	1520	+ mode > LOOPBACK_MODE_2_SWAP)
	1521	+ return -EINVAL;
	1522	+
	1523	+ switch (mode) {
	1524	+ case LOOPBACK_MODE_2_SWAP:
	1525	+ val = I2S_XFER_LP_MODE_2_SWAP;
	1526	+ break;
	1527	+ case LOOPBACK_MODE_2:
	1528	+ val = I2S_XFER_LP_MODE_2;
	1529	+ break;
	1530	+ case LOOPBACK_MODE_1:
	1531	+ val = I2S_XFER_LP_MODE_1;
	1532	+ break;
	1533	+ default:
	1534	+ val = I2S_XFER_LP_MODE_DIS;
	1535	+ break;
	1536	+ }
	1537	+
	1538	+ pm_runtime_get_sync(component->dev);
	1539	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, I2S_XFER_LP_MODE_MASK, val);
	1540	+ pm_runtime_put(component->dev);
	1541	+
	1542	+ return 0;
	1543	+}
	1544	+
	1545	+static const struct snd_kcontrol_new rockchip_i2s_tdm_snd_controls[] = {
	1546	+ SOC_ENUM_EXT("I2STDM Digital Loopback Mode", loopback_mode,
	1547	+ rockchip_i2s_tdm_loopback_get,
	1548	+ rockchip_i2s_tdm_loopback_put),
	1549	+};
	1550	+
1308	1551	static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1309	1552	{
1310	1553	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
..	..	@@ -1340,7 +1583,30 @@
1340	1583	return 0;
1341	1584	}
1342	1585
	1586	+static int rockchip_i2s_tdm_startup(struct snd_pcm_substream *substream,
	1587	+ struct snd_soc_dai *dai)
	1588	+{
	1589	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	1590	+
	1591	+ if (i2s_tdm->substreams[substream->stream])
	1592	+ return -EBUSY;
	1593	+
	1594	+ i2s_tdm->substreams[substream->stream] = substream;
	1595	+
	1596	+ return 0;
	1597	+}
	1598	+
	1599	+static void rockchip_i2s_tdm_shutdown(struct snd_pcm_substream *substream,
	1600	+ struct snd_soc_dai *dai)
	1601	+{
	1602	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	1603	+
	1604	+ i2s_tdm->substreams[substream->stream] = NULL;
	1605	+}
	1606	+
1343	1607	static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
	1608	+ .startup = rockchip_i2s_tdm_startup,
	1609	+ .shutdown = rockchip_i2s_tdm_shutdown,
1344	1610	.hw_params = rockchip_i2s_tdm_hw_params,
1345	1611	.set_sysclk = rockchip_i2s_tdm_set_sysclk,
1346	1612	.set_fmt = rockchip_i2s_tdm_set_fmt,
..	..	@@ -1350,6 +1616,8 @@
1350	1616
1351	1617	static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1352	1618	.name = DRV_NAME,
	1619	+ .controls = rockchip_i2s_tdm_snd_controls,
	1620	+ .num_controls = ARRAY_SIZE(rockchip_i2s_tdm_snd_controls),
1353	1621	};
1354	1622
1355	1623	static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
..	..	@@ -1400,6 +1668,7 @@
1400	1668	{
1401	1669	switch (reg) {
1402	1670	case I2S_TXFIFOLR:
	1671	+ case I2S_INTCR:
1403	1672	case I2S_INTSR:
1404	1673	case I2S_CLR:
1405	1674	case I2S_TXDR:
..	..	@@ -1453,9 +1722,11 @@
1453	1722	u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1454	1723	int i;
1455	1724
	1725	+ if (IS_ERR(i2s_tdm->grf))
	1726	+ return 0;
	1727	+
1456	1728	switch (trcm) {
1457	1729	case I2S_CKR_TRCM_TXONLY:
1458		- /* fall through */
1459	1730	case I2S_CKR_TRCM_RXONLY:
1460	1731	break;
1461	1732	default:
..	..	@@ -1551,6 +1822,12 @@
1551	1822	#ifdef CONFIG_CPU_RK3568
1552	1823	{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1553	1824	#endif
	1825	+#ifdef CONFIG_CPU_RK3588
	1826	+ { .compatible = "rockchip,rk3588-i2s-tdm", },
	1827	+#endif
	1828	+#ifdef CONFIG_CPU_RV1106
	1829	+ { .compatible = "rockchip,rv1106-i2s-tdm", },
	1830	+#endif
1554	1831	#ifdef CONFIG_CPU_RV1126
1555	1832	{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1556	1833	#endif
..	..	@@ -1591,7 +1868,8 @@
1591	1868	SNDRV_PCM_FMTBIT_S16_LE \|
1592	1869	SNDRV_PCM_FMTBIT_S20_3LE \|
1593	1870	SNDRV_PCM_FMTBIT_S24_LE \|
1594		- SNDRV_PCM_FMTBIT_S32_LE),
	1871	+ SNDRV_PCM_FMTBIT_S32_LE \|
	1872	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1595	1873	},
1596	1874	.capture = {
1597	1875	.stream_name = "Capture",
..	..	@@ -1602,7 +1880,8 @@
1602	1880	SNDRV_PCM_FMTBIT_S16_LE \|
1603	1881	SNDRV_PCM_FMTBIT_S20_3LE \|
1604	1882	SNDRV_PCM_FMTBIT_S24_LE \|
1605		- SNDRV_PCM_FMTBIT_S32_LE),
	1883	+ SNDRV_PCM_FMTBIT_S32_LE \|
	1884	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1606	1885	},
1607	1886	.ops = &rockchip_i2s_tdm_dai_ops,
1608	1887	};
..	..	@@ -1758,6 +2037,56 @@
1758	2037	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1759	2038	}
1760	2039
	2040	+static int rockchip_i2s_tdm_get_fifo_count(struct device *dev, int stream)
	2041	+{
	2042	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
	2043	+ int val = 0;
	2044	+
	2045	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	2046	+ regmap_read(i2s_tdm->regmap, I2S_TXFIFOLR, &val);
	2047	+ else
	2048	+ regmap_read(i2s_tdm->regmap, I2S_RXFIFOLR, &val);
	2049	+
	2050	+ val = ((val & I2S_FIFOLR_TFL3_MASK) >> I2S_FIFOLR_TFL3_SHIFT) +
	2051	+ ((val & I2S_FIFOLR_TFL2_MASK) >> I2S_FIFOLR_TFL2_SHIFT) +
	2052	+ ((val & I2S_FIFOLR_TFL1_MASK) >> I2S_FIFOLR_TFL1_SHIFT) +
	2053	+ ((val & I2S_FIFOLR_TFL0_MASK) >> I2S_FIFOLR_TFL0_SHIFT);
	2054	+
	2055	+ return val;
	2056	+}
	2057	+
	2058	+static const struct snd_dlp_config dconfig = {
	2059	+ .get_fifo_count = rockchip_i2s_tdm_get_fifo_count,
	2060	+};
	2061	+
	2062	+static irqreturn_t rockchip_i2s_tdm_isr(int irq, void *devid)
	2063	+{
	2064	+ struct rk_i2s_tdm_dev i2s_tdm = (struct rk_i2s_tdm_dev )devid;
	2065	+ struct snd_pcm_substream *substream;
	2066	+ u32 val;
	2067	+
	2068	+ regmap_read(i2s_tdm->regmap, I2S_INTSR, &val);
	2069	+ if (val & I2S_INTSR_TXUI_ACT) {
	2070	+ dev_warn_ratelimited(i2s_tdm->dev, "TX FIFO Underrun\n");
	2071	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2072	+ I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
	2073	+ substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_PLAYBACK];
	2074	+ if (substream)
	2075	+ snd_pcm_stop_xrun(substream);
	2076	+ }
	2077	+
	2078	+ if (val & I2S_INTSR_RXOI_ACT) {
	2079	+ dev_warn_ratelimited(i2s_tdm->dev, "RX FIFO Overrun\n");
	2080	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2081	+ I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
	2082	+ substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_CAPTURE];
	2083	+ if (substream)
	2084	+ snd_pcm_stop_xrun(substream);
	2085	+ }
	2086	+
	2087	+ return IRQ_HANDLED;
	2088	+}
	2089	+
1761	2090	static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1762	2091	{
1763	2092	struct device_node *node = pdev->dev.of_node;
..	..	@@ -1769,8 +2098,7 @@
1769	2098	#ifdef HAVE_SYNC_RESET
1770	2099	bool sync;
1771	2100	#endif
1772		- int ret;
1773		- int val;
	2101	+ int ret, val, i, irq;
1774	2102
1775	2103	ret = rockchip_i2s_tdm_dai_prepare(pdev, &soc_dai);
1776	2104	if (ret)
..	..	@@ -1783,11 +2111,15 @@
1783	2111	i2s_tdm->dev = &pdev->dev;
1784	2112
1785	2113	of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1786		- if (!of_id \|\| !of_id->data)
	2114	+ if (!of_id)
1787	2115	return -EINVAL;
1788	2116
1789	2117	spin_lock_init(&i2s_tdm->lock);
1790	2118	i2s_tdm->soc_data = (const struct rk_i2s_soc_data *)of_id->data;
	2119	+
	2120	+ for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
	2121	+ if (of_property_read_bool(node, of_quirks[i].quirk))
	2122	+ i2s_tdm->quirks \|= of_quirks[i].id;
1791	2123
1792	2124	i2s_tdm->bclk_fs = 64;
1793	2125	if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
..	..	@@ -1813,8 +2145,6 @@
1813	2145	soc_dai->playback.channels_min = 0;
1814	2146
1815	2147	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1816		- if (IS_ERR(i2s_tdm->grf))
1817		- return PTR_ERR(i2s_tdm->grf);
1818	2148
1819	2149	#ifdef HAVE_SYNC_RESET
1820	2150	sync = of_device_is_compatible(node, "rockchip,px30-i2s-tdm") \|\|
..	..	@@ -1892,23 +2222,32 @@
1892	2222	i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1893	2223	}
1894	2224
1895		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1896		- regs = devm_ioremap_resource(&pdev->dev, res);
	2225	+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1897	2226	if (IS_ERR(regs))
1898	2227	return PTR_ERR(regs);
1899	2228
1900	2229	i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1901		- &rockchip_i2s_tdm_regmap_config);
	2230	+ &rockchip_i2s_tdm_regmap_config);
1902	2231	if (IS_ERR(i2s_tdm->regmap))
1903	2232	return PTR_ERR(i2s_tdm->regmap);
1904	2233
	2234	+ irq = platform_get_irq_optional(pdev, 0);
	2235	+ if (irq > 0) {
	2236	+ ret = devm_request_irq(&pdev->dev, irq, rockchip_i2s_tdm_isr,
	2237	+ IRQF_SHARED, node->name, i2s_tdm);
	2238	+ if (ret) {
	2239	+ dev_err(&pdev->dev, "failed to request irq %u\n", irq);
	2240	+ return ret;
	2241	+ }
	2242	+ }
	2243	+
1905	2244	i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1906	2245	i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1907		- i2s_tdm->playback_dma_data.maxburst = 8;
	2246	+ i2s_tdm->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
1908	2247
1909	2248	i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1910	2249	i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1911		- i2s_tdm->capture_dma_data.maxburst = 8;
	2250	+ i2s_tdm->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
1912	2251
1913	2252	ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1914	2253	if (ret < 0) {
..	..	@@ -1932,6 +2271,36 @@
1932	2271	goto err_pm_disable;
1933	2272	}
1934	2273
	2274	+ if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
	2275	+ unsigned int rate = DEFAULT_FS * DEFAULT_MCLK_FS;
	2276	+ unsigned int div_bclk = DEFAULT_FS * DEFAULT_MCLK_FS;
	2277	+ unsigned int div_lrck = i2s_tdm->bclk_fs;
	2278	+
	2279	+ div_bclk = DIV_ROUND_CLOSEST(rate, div_lrck * DEFAULT_FS);
	2280	+
	2281	+ /* assign generic freq */
	2282	+ clk_set_rate(i2s_tdm->mclk_rx, rate);
	2283	+ clk_set_rate(i2s_tdm->mclk_tx, rate);
	2284	+
	2285	+ ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
	2286	+ if (ret)
	2287	+ goto err_pm_disable;
	2288	+
	2289	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	2290	+ I2S_CLKDIV_RXM_MASK \| I2S_CLKDIV_TXM_MASK,
	2291	+ I2S_CLKDIV_RXM(div_bclk) \| I2S_CLKDIV_TXM(div_bclk));
	2292	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	2293	+ I2S_CKR_RSD_MASK \| I2S_CKR_TSD_MASK,
	2294	+ I2S_CKR_RSD(div_lrck) \| I2S_CKR_TSD(div_lrck));
	2295	+
	2296	+ if (i2s_tdm->clk_trcm)
	2297	+ rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
	2298	+ else
	2299	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	2300	+
	2301	+ pm_runtime_forbid(&pdev->dev);
	2302	+ }
	2303	+
1935	2304	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1936	2305	I2S_DMACR_TDL(16));
1937	2306	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
..	..	@@ -1951,9 +2320,16 @@
1951	2320	goto err_suspend;
1952	2321	}
1953	2322
1954		- if (of_property_read_bool(node, "rockchip,no-dmaengine"))
1955		- return ret;
1956		- ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	2323	+ if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
	2324	+ dev_info(&pdev->dev, "Used for Multi-DAI\n");
	2325	+ return 0;
	2326	+ }
	2327	+
	2328	+ if (of_property_read_bool(node, "rockchip,digital-loopback"))
	2329	+ ret = devm_snd_dmaengine_dlp_register(&pdev->dev, &dconfig);
	2330	+ else
	2331	+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	2332	+
1957	2333	if (ret) {
1958	2334	dev_err(&pdev->dev, "Could not register PCM\n");
1959	2335	return ret;
..	..	@@ -1978,14 +2354,21 @@
1978	2354	if (!pm_runtime_status_suspended(&pdev->dev))
1979	2355	i2s_tdm_runtime_suspend(&pdev->dev);
1980	2356
1981		- if (!IS_ERR(i2s_tdm->mclk_tx))
1982		- clk_prepare_enable(i2s_tdm->mclk_tx);
1983		- if (!IS_ERR(i2s_tdm->mclk_rx))
1984		- clk_prepare_enable(i2s_tdm->mclk_rx);
1985		- if (!IS_ERR(i2s_tdm->hclk))
1986		- clk_disable_unprepare(i2s_tdm->hclk);
	2357	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	2358	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
	2359	+ clk_disable_unprepare(i2s_tdm->hclk);
1987	2360
1988	2361	return 0;
	2362	+}
	2363	+
	2364	+static void rockchip_i2s_tdm_platform_shutdown(struct platform_device *pdev)
	2365	+{
	2366	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(&pdev->dev);
	2367	+
	2368	+ pm_runtime_get_sync(i2s_tdm->dev);
	2369	+ rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	2370	+ rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_CAPTURE);
	2371	+ pm_runtime_put(i2s_tdm->dev);
1989	2372	}
1990	2373
1991	2374	#ifdef CONFIG_PM_SLEEP
..	..	@@ -2023,6 +2406,7 @@
2023	2406	static struct platform_driver rockchip_i2s_tdm_driver = {
2024	2407	.probe = rockchip_i2s_tdm_probe,
2025	2408	.remove = rockchip_i2s_tdm_remove,
	2409	+ .shutdown = rockchip_i2s_tdm_platform_shutdown,
2026	2410	.driver = {
2027	2411	.name = DRV_NAME,
2028	2412	.of_match_table = of_match_ptr(rockchip_i2s_tdm_match),