forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/sound/soc/rockchip/rockchip_i2s.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* sound/soc/rockchip/rockchip_i2s.c
23  *
34  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
45  *
56  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
67  * Author: Jianqun <jay.xu@rock-chips.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  */
129 
1310 #include <linux/module.h>
....@@ -19,7 +16,6 @@
1916 #include <linux/clk/rockchip.h>
2017 #include <linux/pm_runtime.h>
2118 #include <linux/regmap.h>
22
-#include <linux/reset.h>
2319 #include <linux/spinlock.h>
2420 #include <sound/pcm_params.h>
2521 #include <sound/dmaengine_pcm.h>
....@@ -48,8 +44,9 @@
4844 
4945 	struct regmap *regmap;
5046 	struct regmap *grf;
51
-	struct reset_control *reset_m;
52
-	struct reset_control *reset_h;
47
+
48
+	bool has_capture;
49
+	bool has_playback;
5350 
5451 /*
5552  * Used to indicate the tx/rx status.
....@@ -60,7 +57,7 @@
6057 	bool rx_start;
6158 	bool is_master_mode;
6259 	const struct rk_i2s_pins *pins;
63
-	unsigned int bclk_fs;
60
+	unsigned int bclk_ratio;
6461 	spinlock_t lock; /* tx/rx lock */
6562 	unsigned int clk_trcm;
6663 
....@@ -107,21 +104,6 @@
107104 	return snd_soc_dai_get_drvdata(dai);
108105 }
109106 
110
-static void rockchip_i2s_reset(struct rk_i2s_dev *i2s)
111
-{
112
-	if (!IS_ERR(i2s->reset_m))
113
-		reset_control_assert(i2s->reset_m);
114
-	if (!IS_ERR(i2s->reset_h))
115
-		reset_control_assert(i2s->reset_h);
116
-	udelay(1);
117
-	if (!IS_ERR(i2s->reset_m))
118
-		reset_control_deassert(i2s->reset_m);
119
-	if (!IS_ERR(i2s->reset_h))
120
-		reset_control_deassert(i2s->reset_h);
121
-	regcache_mark_dirty(i2s->regmap);
122
-	regcache_sync(i2s->regmap);
123
-}
124
-
125107 static int rockchip_i2s_clear(struct rk_i2s_dev *i2s)
126108 {
127109 	unsigned int clr = I2S_CLR_TXC | I2S_CLR_RXC;
....@@ -150,16 +132,9 @@
150132 	if (!i2s->is_master_mode)
151133 		regmap_update_bits(i2s->regmap, I2S_CKR,
152134 				   I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
153
-	if (ret < 0) {
135
+	if (ret < 0)
154136 		dev_warn(i2s->dev, "failed to clear fifo on %s mode\n",
155137 			 i2s->is_master_mode ? "master" : "slave");
156
-		goto reset;
157
-	}
158
-
159
-	return 0;
160
-
161
-reset:
162
-	rockchip_i2s_reset(i2s);
163138 
164139 	return ret;
165140 }
....@@ -347,7 +322,7 @@
347322 
348323 	if (i2s->is_master_mode) {
349324 		mclk_rate = clk_get_rate(i2s->mclk);
350
-		bclk_rate = i2s->bclk_fs * params_rate(params);
325
+		bclk_rate = i2s->bclk_ratio * params_rate(params);
351326 		if (!bclk_rate)
352327 			return -EINVAL;
353328 
....@@ -475,6 +450,16 @@
475450 	return ret;
476451 }
477452 
453
+static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
454
+				       unsigned int ratio)
455
+{
456
+	struct rk_i2s_dev *i2s = to_info(dai);
457
+
458
+	i2s->bclk_ratio = ratio;
459
+
460
+	return 0;
461
+}
462
+
478463 static int rockchip_i2s_clk_set_rate(struct rk_i2s_dev *i2s,
479464 				     struct clk *clk, unsigned long rate,
480465 				     int ppm)
....@@ -514,6 +499,9 @@
514499 	unsigned int root_rate, div, delta;
515500 	uint64_t ppm;
516501 	int ret;
502
+
503
+	if (rate == 0)
504
+		return 0;
517505 
518506 	if (i2s->mclk_calibrate) {
519507 		ret = rockchip_i2s_clk_set_rate(i2s, i2s->mclk_root,
....@@ -595,8 +583,9 @@
595583 {
596584 	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
597585 
598
-	dai->capture_dma_data = &i2s->capture_dma_data;
599
-	dai->playback_dma_data = &i2s->playback_dma_data;
586
+	snd_soc_dai_init_dma_data(dai,
587
+		i2s->has_playback ? &i2s->playback_dma_data : NULL,
588
+		i2s->has_capture  ? &i2s->capture_dma_data  : NULL);
600589 
601590 	if (i2s->mclk_calibrate)
602591 		snd_soc_add_dai_controls(dai, &rockchip_i2s_compensation_control, 1);
....@@ -606,6 +595,7 @@
606595 
607596 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
608597 	.hw_params = rockchip_i2s_hw_params,
598
+	.set_bclk_ratio	= rockchip_i2s_set_bclk_ratio,
609599 	.set_sysclk = rockchip_i2s_set_sysclk,
610600 	.set_fmt = rockchip_i2s_set_fmt,
611601 	.trigger = rockchip_i2s_trigger,
....@@ -613,28 +603,6 @@
613603 
614604 static struct snd_soc_dai_driver rockchip_i2s_dai = {
615605 	.probe = rockchip_i2s_dai_probe,
616
-	.playback = {
617
-		.stream_name = "Playback",
618
-		.channels_min = 2,
619
-		.channels_max = 8,
620
-		.rates = SNDRV_PCM_RATE_8000_192000,
621
-		.formats = (SNDRV_PCM_FMTBIT_S8 |
622
-			    SNDRV_PCM_FMTBIT_S16_LE |
623
-			    SNDRV_PCM_FMTBIT_S20_3LE |
624
-			    SNDRV_PCM_FMTBIT_S24_LE |
625
-			    SNDRV_PCM_FMTBIT_S32_LE),
626
-	},
627
-	.capture = {
628
-		.stream_name = "Capture",
629
-		.channels_min = 2,
630
-		.channels_max = 2,
631
-		.rates = SNDRV_PCM_RATE_8000_192000,
632
-		.formats = (SNDRV_PCM_FMTBIT_S8 |
633
-			    SNDRV_PCM_FMTBIT_S16_LE |
634
-			    SNDRV_PCM_FMTBIT_S20_3LE |
635
-			    SNDRV_PCM_FMTBIT_S24_LE |
636
-			    SNDRV_PCM_FMTBIT_S32_LE),
637
-	},
638606 	.ops = &rockchip_i2s_dai_ops,
639607 };
640608 
....@@ -730,7 +698,7 @@
730698 	.shift = 11,
731699 };
732700 
733
-static const struct of_device_id rockchip_i2s_match[] = {
701
+static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
734702 #ifdef CONFIG_CPU_PX30
735703 	{ .compatible = "rockchip,px30-i2s", },
736704 #endif
....@@ -747,6 +715,9 @@
747715 #ifdef CONFIG_CPU_RK3188
748716 	{ .compatible = "rockchip,rk3188-i2s", },
749717 #endif
718
+#ifdef CONFIG_CPU_RK322X
719
+	{ .compatible = "rockchip,rk3228-i2s", },
720
+#endif
750721 #ifdef CONFIG_CPU_RK3288
751722 	{ .compatible = "rockchip,rk3288-i2s", },
752723 #endif
....@@ -755,6 +726,9 @@
755726 #endif
756727 #ifdef CONFIG_CPU_RK3328
757728 	{ .compatible = "rockchip,rk3328-i2s", },
729
+#endif
730
+#ifdef CONFIG_CPU_RK3366
731
+	{ .compatible = "rockchip,rk3366-i2s", },
758732 #endif
759733 #ifdef CONFIG_CPU_RK3368
760734 	{ .compatible = "rockchip,rk3368-i2s", },
....@@ -768,16 +742,96 @@
768742 	{},
769743 };
770744 
745
+static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
746
+				 struct snd_soc_dai_driver **dp)
747
+{
748
+	struct device_node *node = i2s->dev->of_node;
749
+	struct snd_soc_dai_driver *dai;
750
+	struct property *dma_names;
751
+	const char *dma_name;
752
+	unsigned int val;
753
+
754
+	of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
755
+		if (!strcmp(dma_name, "tx"))
756
+			i2s->has_playback = true;
757
+		if (!strcmp(dma_name, "rx"))
758
+			i2s->has_capture = true;
759
+	}
760
+
761
+	dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
762
+			   sizeof(*dai), GFP_KERNEL);
763
+	if (!dai)
764
+		return -ENOMEM;
765
+
766
+	if (i2s->has_playback) {
767
+		dai->playback.stream_name = "Playback";
768
+		dai->playback.channels_min = 2;
769
+		dai->playback.channels_max = 8;
770
+		dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
771
+		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
772
+					SNDRV_PCM_FMTBIT_S16_LE |
773
+					SNDRV_PCM_FMTBIT_S20_3LE |
774
+					SNDRV_PCM_FMTBIT_S24_LE |
775
+					SNDRV_PCM_FMTBIT_S32_LE;
776
+
777
+		i2s->playback_dma_data.addr = res->start + I2S_TXDR;
778
+		i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
779
+		i2s->playback_dma_data.maxburst = 8;
780
+
781
+		if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
782
+			if (val >= 2 && val <= 8)
783
+				dai->playback.channels_max = val;
784
+		}
785
+	}
786
+
787
+	if (i2s->has_capture) {
788
+		dai->capture.stream_name = "Capture";
789
+		dai->capture.channels_min = 2;
790
+		dai->capture.channels_max = 8;
791
+		dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
792
+		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
793
+				       SNDRV_PCM_FMTBIT_S16_LE |
794
+				       SNDRV_PCM_FMTBIT_S20_3LE |
795
+				       SNDRV_PCM_FMTBIT_S24_LE |
796
+				       SNDRV_PCM_FMTBIT_S32_LE;
797
+
798
+		i2s->capture_dma_data.addr = res->start + I2S_RXDR;
799
+		i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
800
+		i2s->capture_dma_data.maxburst = 8;
801
+
802
+		if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
803
+			if (val >= 2 && val <= 8)
804
+				dai->capture.channels_max = val;
805
+		}
806
+	}
807
+
808
+	i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
809
+	if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
810
+		if (val >= 0 && val <= 2) {
811
+			i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
812
+			if (i2s->clk_trcm)
813
+				dai->symmetric_rates = 1;
814
+		}
815
+	}
816
+
817
+	regmap_update_bits(i2s->regmap, I2S_CKR,
818
+			   I2S_CKR_TRCM_MASK, i2s->clk_trcm);
819
+
820
+	if (dp)
821
+		*dp = dai;
822
+
823
+	return 0;
824
+}
825
+
771826 static int rockchip_i2s_probe(struct platform_device *pdev)
772827 {
773828 	struct device_node *node = pdev->dev.of_node;
774829 	const struct of_device_id *of_id;
775830 	struct rk_i2s_dev *i2s;
776
-	struct snd_soc_dai_driver *soc_dai;
831
+	struct snd_soc_dai_driver *dai;
777832 	struct resource *res;
778833 	void __iomem *regs;
779834 	int ret;
780
-	int val;
781835 
782836 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
783837 	if (!i2s)
....@@ -795,8 +849,21 @@
795849 		i2s->pins = of_id->data;
796850 	}
797851 
798
-	i2s->reset_m = devm_reset_control_get(&pdev->dev, "reset-m");
799
-	i2s->reset_h = devm_reset_control_get(&pdev->dev, "reset-h");
852
+	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
853
+	if (IS_ERR(regs))
854
+		return PTR_ERR(regs);
855
+
856
+	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
857
+					    &rockchip_i2s_regmap_config);
858
+	if (IS_ERR(i2s->regmap)) {
859
+		dev_err(&pdev->dev,
860
+			"Failed to initialise managed register map\n");
861
+		return PTR_ERR(i2s->regmap);
862
+	}
863
+
864
+	i2s->bclk_ratio = 64;
865
+
866
+	dev_set_drvdata(&pdev->dev, i2s);
800867 
801868 	i2s->mclk_calibrate =
802869 		of_property_read_bool(node, "rockchip,mclk-calibrate");
....@@ -807,6 +874,12 @@
807874 
808875 		i2s->mclk_root_initial_rate = clk_get_rate(i2s->mclk_root);
809876 		i2s->mclk_root_rate = i2s->mclk_root_initial_rate;
877
+	}
878
+
879
+	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
880
+	if (IS_ERR(i2s->mclk)) {
881
+		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
882
+		return PTR_ERR(i2s->mclk);
810883 	}
811884 
812885 	/* try to prepare related clocks */
....@@ -821,38 +894,6 @@
821894 		return ret;
822895 	}
823896 
824
-	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
825
-	if (IS_ERR(i2s->mclk)) {
826
-		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
827
-		ret = PTR_ERR(i2s->mclk);
828
-		goto err_clk;
829
-	}
830
-
831
-	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
832
-	if (IS_ERR(regs)) {
833
-		ret = PTR_ERR(regs);
834
-		goto err_clk;
835
-	}
836
-
837
-	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
838
-					    &rockchip_i2s_regmap_config);
839
-	if (IS_ERR(i2s->regmap)) {
840
-		dev_err(&pdev->dev,
841
-			"Failed to initialise managed register map\n");
842
-		ret = PTR_ERR(i2s->regmap);
843
-		goto err_clk;
844
-	}
845
-
846
-	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
847
-	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
848
-	i2s->playback_dma_data.maxburst = 8;
849
-
850
-	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
851
-	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
852
-	i2s->capture_dma_data.maxburst = 8;
853
-
854
-	dev_set_drvdata(&pdev->dev, i2s);
855
-
856897 	pm_runtime_enable(&pdev->dev);
857898 	if (!pm_runtime_enabled(&pdev->dev)) {
858899 		ret = i2s_runtime_resume(&pdev->dev);
....@@ -860,49 +901,13 @@
860901 			goto err_pm_disable;
861902 	}
862903 
863
-	soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
864
-			       sizeof(*soc_dai), GFP_KERNEL);
865
-	if (!soc_dai) {
866
-		ret = -ENOMEM;
904
+	ret = rockchip_i2s_init_dai(i2s, res, &dai);
905
+	if (ret)
867906 		goto err_pm_disable;
868
-	}
869
-
870
-	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
871
-		if (val >= 2 && val <= 8)
872
-			soc_dai->playback.channels_max = val;
873
-	}
874
-
875
-	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
876
-		if (val >= 2 && val <= 8)
877
-			soc_dai->capture.channels_max = val;
878
-	}
879
-
880
-	if (of_property_read_bool(node, "rockchip,playback-only"))
881
-		soc_dai->capture.channels_min = 0;
882
-	else if (of_property_read_bool(node, "rockchip,capture-only"))
883
-		soc_dai->playback.channels_min = 0;
884
-
885
-	i2s->bclk_fs = 64;
886
-	if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
887
-		if ((val >= 32) && (val % 2 == 0))
888
-			i2s->bclk_fs = val;
889
-	}
890
-
891
-	i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
892
-	if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
893
-		if (val >= 0 && val <= 2) {
894
-			i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
895
-			if (i2s->clk_trcm)
896
-				soc_dai->symmetric_rates = 1;
897
-		}
898
-	}
899
-
900
-	regmap_update_bits(i2s->regmap, I2S_CKR,
901
-			   I2S_CKR_TRCM_MASK, i2s->clk_trcm);
902907 
903908 	ret = devm_snd_soc_register_component(&pdev->dev,
904909 					      &rockchip_i2s_component,
905
-					      soc_dai, 1);
910
+					      dai, 1);
906911 
907912 	if (ret) {
908913 		dev_err(&pdev->dev, "Could not register DAI\n");
....@@ -927,8 +932,9 @@
927932 		i2s_runtime_suspend(&pdev->dev);
928933 err_pm_disable:
929934 	pm_runtime_disable(&pdev->dev);
930
-err_clk:
935
+
931936 	clk_disable_unprepare(i2s->hclk);
937
+
932938 	return ret;
933939 }
934940