forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/sound/soc/qcom/qdsp6/q6afe.c
....@@ -42,6 +42,10 @@
4242 #define AFE_PARAM_ID_I2S_CONFIG	0x0001020D
4343 #define AFE_PARAM_ID_TDM_CONFIG	0x0001029D
4444 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG	0x00010297
45
+#define AFE_PARAM_ID_CODEC_DMA_CONFIG	0x000102B8
46
+#define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST	0x000100f4
47
+#define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST   0x000100f5
48
+#define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST	0x000100f6
4549 
4650 /* I2S config specific */
4751 #define AFE_API_VERSION_I2S_CONFIG	0x1
....@@ -71,6 +75,7 @@
7175 /* Port IDs */
7276 #define AFE_API_VERSION_HDMI_CONFIG	0x1
7377 #define AFE_PORT_ID_MULTICHAN_HDMI_RX	0x100E
78
+#define AFE_PORT_ID_HDMI_OVER_DP_RX	0x6020
7479 
7580 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1
7681 /* Clock set API version */
....@@ -298,22 +303,71 @@
298303 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \
299304 	(AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
300305 
306
+/* AFE WSA Codec DMA Rx port 0 */
307
+#define AFE_PORT_ID_WSA_CODEC_DMA_RX_0	0xB000
308
+/* AFE WSA Codec DMA Tx port 0 */
309
+#define AFE_PORT_ID_WSA_CODEC_DMA_TX_0	0xB001
310
+/* AFE WSA Codec DMA Rx port 1 */
311
+#define AFE_PORT_ID_WSA_CODEC_DMA_RX_1	0xB002
312
+/* AFE WSA Codec DMA Tx port 1 */
313
+#define AFE_PORT_ID_WSA_CODEC_DMA_TX_1	0xB003
314
+/* AFE WSA Codec DMA Tx port 2 */
315
+#define AFE_PORT_ID_WSA_CODEC_DMA_TX_2	0xB005
316
+/* AFE VA Codec DMA Tx port 0 */
317
+#define AFE_PORT_ID_VA_CODEC_DMA_TX_0	0xB021
318
+/* AFE VA Codec DMA Tx port 1 */
319
+#define AFE_PORT_ID_VA_CODEC_DMA_TX_1	0xB023
320
+/* AFE VA Codec DMA Tx port 2 */
321
+#define AFE_PORT_ID_VA_CODEC_DMA_TX_2	0xB025
322
+/* AFE Rx Codec DMA Rx port 0 */
323
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_0	0xB030
324
+/* AFE Tx Codec DMA Tx port 0 */
325
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_0	0xB031
326
+/* AFE Rx Codec DMA Rx port 1 */
327
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_1	0xB032
328
+/* AFE Tx Codec DMA Tx port 1 */
329
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_1	0xB033
330
+/* AFE Rx Codec DMA Rx port 2 */
331
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_2	0xB034
332
+/* AFE Tx Codec DMA Tx port 2 */
333
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_2	0xB035
334
+/* AFE Rx Codec DMA Rx port 3 */
335
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_3	0xB036
336
+/* AFE Tx Codec DMA Tx port 3 */
337
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_3	0xB037
338
+/* AFE Rx Codec DMA Rx port 4 */
339
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_4	0xB038
340
+/* AFE Tx Codec DMA Tx port 4 */
341
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_4	0xB039
342
+/* AFE Rx Codec DMA Rx port 5 */
343
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_5	0xB03A
344
+/* AFE Tx Codec DMA Tx port 5 */
345
+#define AFE_PORT_ID_TX_CODEC_DMA_TX_5	0xB03B
346
+/* AFE Rx Codec DMA Rx port 6 */
347
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_6	0xB03C
348
+/* AFE Rx Codec DMA Rx port 7 */
349
+#define AFE_PORT_ID_RX_CODEC_DMA_RX_7	0xB03E
350
+
301351 #define Q6AFE_LPASS_MODE_CLK1_VALID 1
302352 #define Q6AFE_LPASS_MODE_CLK2_VALID 2
303353 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
304354 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
305355 #define AFE_API_VERSION_TDM_CONFIG              1
306356 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG	1
357
+#define AFE_API_VERSION_CODEC_DMA_CONFIG	1
307358 
308359 #define TIMEOUT_MS 1000
309360 #define AFE_CMD_RESP_AVAIL	0
310361 #define AFE_CMD_RESP_NONE	1
362
+#define AFE_CLK_TOKEN		1024
311363 
312364 struct q6afe {
313365 	struct apr_device *apr;
314366 	struct device *dev;
315367 	struct q6core_svc_api_info ainfo;
316368 	struct mutex lock;
369
+	struct aprv2_ibasic_rsp_result_t result;
370
+	wait_queue_head_t wait;
317371 	struct list_head port_list;
318372 	spinlock_t port_list_lock;
319373 };
....@@ -447,11 +501,21 @@
447501 	u32	slot_mask;
448502 } __packed;
449503 
504
+struct afe_param_id_cdc_dma_cfg {
505
+	u32	cdc_dma_cfg_minor_version;
506
+	u32	sample_rate;
507
+	u16	bit_width;
508
+	u16	data_format;
509
+	u16	num_channels;
510
+	u16	active_channels_mask;
511
+} __packed;
512
+
450513 union afe_port_config {
451514 	struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
452515 	struct afe_param_id_slimbus_cfg           slim_cfg;
453516 	struct afe_param_id_i2s_cfg	i2s_cfg;
454517 	struct afe_param_id_tdm_cfg	tdm_cfg;
518
+	struct afe_param_id_cdc_dma_cfg	dma_cfg;
455519 } __packed;
456520 
457521 
....@@ -484,6 +548,18 @@
484548 	struct kref refcount;
485549 	struct list_head node;
486550 };
551
+
552
+struct afe_cmd_remote_lpass_core_hw_vote_request {
553
+        uint32_t  hw_block_id;
554
+        char client_name[8];
555
+} __packed;
556
+
557
+struct afe_cmd_remote_lpass_core_hw_devote_request {
558
+        uint32_t  hw_block_id;
559
+        uint32_t client_handle;
560
+} __packed;
561
+
562
+
487563 
488564 struct afe_port_map {
489565 	int port_id;
....@@ -704,6 +780,52 @@
704780 				QUINARY_TDM_RX_7, 1, 1},
705781 	[QUINARY_TDM_TX_7] =  { AFE_PORT_ID_QUINARY_TDM_TX_7,
706782 				QUINARY_TDM_TX_7, 0, 1},
783
+	[DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX,
784
+				DISPLAY_PORT_RX, 1, 1},
785
+	[WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0,
786
+				WSA_CODEC_DMA_RX_0, 1, 1},
787
+	[WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0,
788
+				WSA_CODEC_DMA_TX_0, 0, 1},
789
+	[WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1,
790
+				WSA_CODEC_DMA_RX_1, 1, 1},
791
+	[WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1,
792
+				WSA_CODEC_DMA_TX_1, 0, 1},
793
+	[WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2,
794
+				WSA_CODEC_DMA_TX_2, 0, 1},
795
+	[VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0,
796
+				VA_CODEC_DMA_TX_0, 0, 1},
797
+	[VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1,
798
+				VA_CODEC_DMA_TX_1, 0, 1},
799
+	[VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2,
800
+				VA_CODEC_DMA_TX_2, 0, 1},
801
+	[RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0,
802
+				RX_CODEC_DMA_RX_0, 1, 1},
803
+	[TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0,
804
+				TX_CODEC_DMA_TX_0, 0, 1},
805
+	[RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1,
806
+				RX_CODEC_DMA_RX_1, 1, 1},
807
+	[TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1,
808
+				TX_CODEC_DMA_TX_1, 0, 1},
809
+	[RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2,
810
+				RX_CODEC_DMA_RX_2, 1, 1},
811
+	[TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2,
812
+				TX_CODEC_DMA_TX_2, 0, 1},
813
+	[RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3,
814
+				RX_CODEC_DMA_RX_3, 1, 1},
815
+	[TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3,
816
+				TX_CODEC_DMA_TX_3, 0, 1},
817
+	[RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4,
818
+				RX_CODEC_DMA_RX_4, 1, 1},
819
+	[TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4,
820
+				TX_CODEC_DMA_TX_4, 0, 1},
821
+	[RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5,
822
+				RX_CODEC_DMA_RX_5, 1, 1},
823
+	[TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5,
824
+				TX_CODEC_DMA_TX_5, 0, 1},
825
+	[RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6,
826
+				RX_CODEC_DMA_RX_6, 1, 1},
827
+	[RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7,
828
+				RX_CODEC_DMA_RX_7, 1, 1},
707829 };
708830 
709831 static void q6afe_port_free(struct kref *ref)
....@@ -766,6 +888,9 @@
766888 				port->result = *res;
767889 				wake_up(&port->wait);
768890 				kref_put(&port->refcount, q6afe_port_free);
891
+			} else if (hdr->token == AFE_CLK_TOKEN) {
892
+				afe->result = *res;
893
+				wake_up(&afe->wait);
769894 			}
770895 			break;
771896 		default:
....@@ -773,6 +898,11 @@
773898 			break;
774899 		}
775900 	}
901
+		break;
902
+	case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST:
903
+		afe->result.opcode = hdr->opcode;
904
+		afe->result.status = res->status;
905
+		wake_up(&afe->wait);
776906 		break;
777907 	default:
778908 		break;
....@@ -798,15 +928,23 @@
798928 EXPORT_SYMBOL_GPL(q6afe_get_port_id);
799929 
800930 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt,
801
-			    struct q6afe_port *port)
931
+			    struct q6afe_port *port, uint32_t rsp_opcode)
802932 {
803933 	wait_queue_head_t *wait = &port->wait;
804
-	struct apr_hdr *hdr = &pkt->hdr;
934
+	struct aprv2_ibasic_rsp_result_t *result;
805935 	int ret;
806936 
807937 	mutex_lock(&afe->lock);
808
-	port->result.opcode = 0;
809
-	port->result.status = 0;
938
+	if (port) {
939
+		wait = &port->wait;
940
+		result = &port->result;
941
+	} else {
942
+		result = &afe->result;
943
+		wait = &afe->wait;
944
+	}
945
+
946
+	result->opcode = 0;
947
+	result->status = 0;
810948 
811949 	ret = apr_send_pkt(afe->apr, pkt);
812950 	if (ret < 0) {
....@@ -815,13 +953,13 @@
815953 		goto err;
816954 	}
817955 
818
-	ret = wait_event_timeout(*wait, (port->result.opcode == hdr->opcode),
956
+	ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode),
819957 				 msecs_to_jiffies(TIMEOUT_MS));
820958 	if (!ret) {
821959 		ret = -ETIMEDOUT;
822
-	} else if (port->result.status > 0) {
960
+	} else if (result->status > 0) {
823961 		dev_err(afe->dev, "DSP returned error[%x]\n",
824
-			port->result.status);
962
+			result->status);
825963 		ret = -EINVAL;
826964 	} else {
827965 		ret = 0;
....@@ -833,14 +971,13 @@
833971 	return ret;
834972 }
835973 
836
-static int q6afe_port_set_param(struct q6afe_port *port, void *data,
837
-				int param_id, int module_id, int psize)
974
+static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port,
975
+			   void *data, int param_id, int module_id, int psize,
976
+			   int token)
838977 {
839978 	struct afe_svc_cmd_set_param *param;
840979 	struct afe_port_param_data_v2 *pdata;
841
-	struct q6afe *afe = port->afe;
842980 	struct apr_pkt *pkt;
843
-	u16 port_id = port->id;
844981 	int ret, pkt_size;
845982 	void *p, *pl;
846983 
....@@ -861,7 +998,7 @@
861998 	pkt->hdr.pkt_size = pkt_size;
862999 	pkt->hdr.src_port = 0;
8631000 	pkt->hdr.dest_port = 0;
864
-	pkt->hdr.token = port->token;
1001
+	pkt->hdr.token = token;
8651002 	pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM;
8661003 
8671004 	param->payload_size = sizeof(*pdata) + psize;
....@@ -872,13 +1009,19 @@
8721009 	pdata->param_id = param_id;
8731010 	pdata->param_size = psize;
8741011 
875
-	ret = afe_apr_send_pkt(afe, pkt, port);
1012
+	ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM);
8761013 	if (ret)
877
-		dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
878
-		       port_id, ret);
1014
+		dev_err(afe->dev, "AFE set params failed %d\n", ret);
8791015 
8801016 	kfree(pkt);
8811017 	return ret;
1018
+}
1019
+
1020
+static int q6afe_port_set_param(struct q6afe_port *port, void *data,
1021
+				int param_id, int module_id, int psize)
1022
+{
1023
+	return q6afe_set_param(port->afe, port, data, param_id, module_id,
1024
+			       psize, port->token);
8821025 }
8831026 
8841027 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data,
....@@ -921,7 +1064,7 @@
9211064 	pdata->param_id = param_id;
9221065 	pdata->param_size = psize;
9231066 
924
-	ret = afe_apr_send_pkt(afe, pkt, port);
1067
+	ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2);
9251068 	if (ret)
9261069 		dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
9271070 		       port_id, ret);
....@@ -930,7 +1073,7 @@
9301073 	return ret;
9311074 }
9321075 
933
-static int q6afe_set_lpass_clock(struct q6afe_port *port,
1076
+static int q6afe_port_set_lpass_clock(struct q6afe_port *port,
9341077 				 struct afe_clk_cfg *cfg)
9351078 {
9361079 	return q6afe_port_set_param_v2(port, cfg,
....@@ -955,6 +1098,25 @@
9551098 				       sizeof(*cfg));
9561099 }
9571100 
1101
+int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
1102
+			  int clk_root, unsigned int freq)
1103
+{
1104
+	struct q6afe *afe = dev_get_drvdata(dev->parent);
1105
+	struct afe_clk_set cset = {0,};
1106
+
1107
+	cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
1108
+	cset.clk_id = clk_id;
1109
+	cset.clk_freq_in_hz = freq;
1110
+	cset.clk_attri = attri;
1111
+	cset.clk_root = clk_root;
1112
+	cset.enable = !!freq;
1113
+
1114
+	return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET,
1115
+			       AFE_MODULE_CLOCK_SET, sizeof(cset),
1116
+			       AFE_CLK_TOKEN);
1117
+}
1118
+EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock);
1119
+
9581120 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
9591121 			  int clk_src, int clk_root,
9601122 			  unsigned int freq, int dir)
....@@ -977,7 +1139,7 @@
9771139 		ccfg.clk_src = clk_src;
9781140 		ccfg.clk_root = clk_root;
9791141 		ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID;
980
-		ret = q6afe_set_lpass_clock(port, &ccfg);
1142
+		ret = q6afe_port_set_lpass_clock(port, &ccfg);
9811143 		break;
9821144 
9831145 	case LPAIF_OSR_CLK:
....@@ -986,11 +1148,12 @@
9861148 		ccfg.clk_src = clk_src;
9871149 		ccfg.clk_root = clk_root;
9881150 		ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
989
-		ret = q6afe_set_lpass_clock(port, &ccfg);
1151
+		ret = q6afe_port_set_lpass_clock(port, &ccfg);
9901152 		break;
9911153 	case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
9921154 	case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
9931155 	case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
1156
+	case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK:
9941157 		cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
9951158 		cset.clk_id = clk_id;
9961159 		cset.clk_freq_in_hz = freq;
....@@ -1051,7 +1214,7 @@
10511214 	stop->port_id = port_id;
10521215 	stop->reserved = 0;
10531216 
1054
-	ret = afe_apr_send_pkt(afe, pkt, port);
1217
+	ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP);
10551218 	if (ret)
10561219 		dev_err(afe->dev, "AFE close failed %d\n", ret);
10571220 
....@@ -1286,6 +1449,28 @@
12861449 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare);
12871450 
12881451 /**
1452
+ * q6afe_dam_port_prepare() - Prepare dma afe port.
1453
+ *
1454
+ * @port: Instance of afe port
1455
+ * @cfg: DMA configuration for the afe port
1456
+ *
1457
+ */
1458
+void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
1459
+				struct q6afe_cdc_dma_cfg *cfg)
1460
+{
1461
+	union afe_port_config *pcfg = &port->port_cfg;
1462
+	struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg;
1463
+
1464
+	dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG;
1465
+	dma_cfg->sample_rate = cfg->sample_rate;
1466
+	dma_cfg->bit_width = cfg->bit_width;
1467
+	dma_cfg->data_format = cfg->data_format;
1468
+	dma_cfg->num_channels = cfg->num_channels;
1469
+	if (!cfg->active_channels_mask)
1470
+		dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1;
1471
+}
1472
+EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare);
1473
+/**
12891474  * q6afe_port_start() - Start a afe port
12901475  *
12911476  * @port: Instance of port to start
....@@ -1341,7 +1526,7 @@
13411526 
13421527 	start->port_id = port_id;
13431528 
1344
-	ret = afe_apr_send_pkt(afe, pkt, port);
1529
+	ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START);
13451530 	if (ret)
13461531 		dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
13471532 			port_id, ret);
....@@ -1384,6 +1569,7 @@
13841569 
13851570 	switch (port_id) {
13861571 	case AFE_PORT_ID_MULTICHAN_HDMI_RX:
1572
+	case AFE_PORT_ID_HDMI_OVER_DP_RX:
13871573 		cfg_type = AFE_PARAM_ID_HDMI_CONFIG;
13881574 		break;
13891575 	case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX:
....@@ -1416,7 +1602,9 @@
14161602 	case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
14171603 		cfg_type = AFE_PARAM_ID_TDM_CONFIG;
14181604 		break;
1419
-
1605
+	case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7:
1606
+		cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG;
1607
+	break;
14201608 	default:
14211609 		dev_err(dev, "Invalid port id 0x%x\n", port_id);
14221610 		return ERR_PTR(-EINVAL);
....@@ -1454,6 +1642,85 @@
14541642 }
14551643 EXPORT_SYMBOL_GPL(q6afe_port_put);
14561644 
1645
+int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
1646
+			       uint32_t client_handle)
1647
+{
1648
+	struct q6afe *afe = dev_get_drvdata(dev->parent);
1649
+	struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg;
1650
+	struct apr_pkt *pkt;
1651
+	int ret = 0;
1652
+	int pkt_size;
1653
+	void *p;
1654
+
1655
+	pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
1656
+	p = kzalloc(pkt_size, GFP_KERNEL);
1657
+	if (!p)
1658
+		return -ENOMEM;
1659
+
1660
+	pkt = p;
1661
+	vote_cfg = p + APR_HDR_SIZE;
1662
+
1663
+	pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
1664
+					   APR_HDR_LEN(APR_HDR_SIZE),
1665
+					   APR_PKT_VER);
1666
+	pkt->hdr.pkt_size = pkt_size;
1667
+	pkt->hdr.src_port = 0;
1668
+	pkt->hdr.dest_port = 0;
1669
+	pkt->hdr.token = hw_block_id;
1670
+	pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST;
1671
+	vote_cfg->hw_block_id = hw_block_id;
1672
+	vote_cfg->client_handle = client_handle;
1673
+
1674
+	ret = apr_send_pkt(afe->apr, pkt);
1675
+	if (ret < 0)
1676
+		dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id);
1677
+
1678
+	kfree(pkt);
1679
+	return ret;
1680
+}
1681
+EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw);
1682
+
1683
+int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
1684
+			     char *client_name, uint32_t *client_handle)
1685
+{
1686
+	struct q6afe *afe = dev_get_drvdata(dev->parent);
1687
+	struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg;
1688
+	struct apr_pkt *pkt;
1689
+	int ret = 0;
1690
+	int pkt_size;
1691
+	void *p;
1692
+
1693
+	pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
1694
+	p = kzalloc(pkt_size, GFP_KERNEL);
1695
+	if (!p)
1696
+		return -ENOMEM;
1697
+
1698
+	pkt = p;
1699
+	vote_cfg = p + APR_HDR_SIZE;
1700
+
1701
+	pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
1702
+					   APR_HDR_LEN(APR_HDR_SIZE),
1703
+					   APR_PKT_VER);
1704
+	pkt->hdr.pkt_size = pkt_size;
1705
+	pkt->hdr.src_port = 0;
1706
+	pkt->hdr.dest_port = 0;
1707
+	pkt->hdr.token = hw_block_id;
1708
+	pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST;
1709
+	vote_cfg->hw_block_id = hw_block_id;
1710
+	strlcpy(vote_cfg->client_name, client_name,
1711
+			sizeof(vote_cfg->client_name));
1712
+
1713
+	ret = afe_apr_send_pkt(afe, pkt, NULL,
1714
+			       AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST);
1715
+	if (ret)
1716
+		dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id);
1717
+
1718
+
1719
+	kfree(pkt);
1720
+	return ret;
1721
+}
1722
+EXPORT_SYMBOL(q6afe_vote_lpass_core_hw);
1723
+
14571724 static int q6afe_probe(struct apr_device *adev)
14581725 {
14591726 	struct q6afe *afe;
....@@ -1466,6 +1733,7 @@
14661733 	q6core_get_svc_api_info(adev->svc_id, &afe->ainfo);
14671734 	afe->apr = adev;
14681735 	mutex_init(&afe->lock);
1736
+	init_waitqueue_head(&afe->wait);
14691737 	afe->dev = dev;
14701738 	INIT_LIST_HEAD(&afe->port_list);
14711739 	spin_lock_init(&afe->port_list_lock);
....@@ -1482,11 +1750,13 @@
14821750 	return 0;
14831751 }
14841752 
1753
+#ifdef CONFIG_OF
14851754 static const struct of_device_id q6afe_device_id[]  = {
14861755 	{ .compatible = "qcom,q6afe" },
14871756 	{},
14881757 };
14891758 MODULE_DEVICE_TABLE(of, q6afe_device_id);
1759
+#endif
14901760 
14911761 static struct apr_driver qcom_q6afe_driver = {
14921762 	.probe = q6afe_probe,