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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/sound/soc/meson/axg-fifo.c
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@@ -19,7 +19,7 @@
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  * This file implements the platform operations common to the playback and
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  * capture frontend DAI. The logic behind this two types of fifo is very
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  * similar but some difference exist.
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- * These differences the respective DAI drivers
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+ * These differences are handled in the respective DAI drivers
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  */
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 static struct snd_pcm_hardware axg_fifo_hw = {
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@@ -34,7 +34,7 @@
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 	.rate_max = 192000,
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 	.channels_min = 1,
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 	.channels_max = AXG_FIFO_CH_MAX,
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-	.period_bytes_min = AXG_FIFO_MIN_DEPTH,
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+	.period_bytes_min = AXG_FIFO_BURST,
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 	.period_bytes_max = UINT_MAX,
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 	.periods_min = 2,
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 	.periods_max = UINT_MAX,
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@@ -47,7 +47,7 @@
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 {
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 	struct snd_soc_pcm_runtime *rtd = ss->private_data;
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-	return rtd->cpu_dai;
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+	return asoc_rtd_to_cpu(rtd, 0);
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 }
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 static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
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@@ -70,7 +70,8 @@
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 			   enable ? CTRL0_DMA_EN : 0);
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 }
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-static int axg_fifo_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
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+int axg_fifo_pcm_trigger(struct snd_soc_component *component,
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+			 struct snd_pcm_substream *ss, int cmd)
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 {
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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@@ -91,8 +92,10 @@
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 	return 0;
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 }
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_trigger);
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-static snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_pcm_substream *ss)
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+snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
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+				       struct snd_pcm_substream *ss)
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 {
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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 	struct snd_pcm_runtime *runtime = ss->runtime;
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@@ -102,19 +105,18 @@
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 	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
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 }
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_pointer);
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-static int axg_fifo_pcm_hw_params(struct snd_pcm_substream *ss,
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-				  struct snd_pcm_hw_params *params)
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+int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
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+			   struct snd_pcm_substream *ss,
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+			   struct snd_pcm_hw_params *params)
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 {
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 	struct snd_pcm_runtime *runtime = ss->runtime;
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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+	unsigned int burst_num, period, threshold;
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 	dma_addr_t end_ptr;
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-	unsigned int burst_num;
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-	int ret;
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-	ret = snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(params));
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-	if (ret < 0)
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-		return ret;
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+	period = params_period_bytes(params);
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 	/* Setup dma memory pointers */
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 	end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
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@@ -122,8 +124,23 @@
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 	regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
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 	/* Setup interrupt periodicity */
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-	burst_num = params_period_bytes(params) / AXG_FIFO_BURST;
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+	burst_num = period / AXG_FIFO_BURST;
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 	regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
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+
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+	/*
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+	 * Start the fifo request on the smallest of the following:
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+	 * - Half the fifo size
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+	 * - Half the period size
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+	 */
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+	threshold = min(period / 2, fifo->depth / 2);
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+
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+	/*
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+	 * With the threshold in bytes, register value is:
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+	 * V = (threshold / burst) - 1
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+	 */
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+	threshold /= AXG_FIFO_BURST;
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+	regmap_field_write(fifo->field_threshold,
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+			   threshold ? threshold - 1 : 0);
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 	/* Enable block count irq */
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 	regmap_update_bits(fifo->map, FIFO_CTRL0,
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@@ -132,8 +149,29 @@
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 	return 0;
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 }
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_params);
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153
 
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-static int axg_fifo_pcm_hw_free(struct snd_pcm_substream *ss)
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+int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
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+			    struct snd_pcm_substream *ss,
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+			    struct snd_pcm_hw_params *params)
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+{
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+	struct axg_fifo *fifo = axg_fifo_data(ss);
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+	struct snd_pcm_runtime *runtime = ss->runtime;
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+	int ret;
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+
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+	ret = axg_fifo_pcm_hw_params(component, ss, params);
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+	if (ret)
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+		return ret;
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+
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+	/* Set the initial memory address of the DMA */
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+	regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
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+
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+	return 0;
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+}
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+EXPORT_SYMBOL_GPL(g12a_fifo_pcm_hw_params);
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+
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+int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
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+			 struct snd_pcm_substream *ss)
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 {
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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@@ -141,8 +179,9 @@
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 	regmap_update_bits(fifo->map, FIFO_CTRL0,
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 			   CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
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-	return snd_pcm_lib_free_pages(ss);
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+	return 0;
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 }
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
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 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
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 {
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@@ -177,7 +216,8 @@
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 	return IRQ_RETVAL(status);
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 }
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-static int axg_fifo_pcm_open(struct snd_pcm_substream *ss)
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+int axg_fifo_pcm_open(struct snd_soc_component *component,
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+		      struct snd_pcm_substream *ss)
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 {
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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 	struct device *dev = axg_fifo_dev(ss);
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@@ -187,17 +227,17 @@
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 	/*
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 	 * Make sure the buffer and period size are multiple of the FIFO
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-	 * minimum depth size
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+	 * burst
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 	 */
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 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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 					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
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-					 AXG_FIFO_MIN_DEPTH);
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+					 AXG_FIFO_BURST);
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 	if (ret)
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 		return ret;
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 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
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 					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
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-					 AXG_FIFO_MIN_DEPTH);
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+					 AXG_FIFO_BURST);
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 	if (ret)
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 		return ret;
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@@ -239,8 +279,10 @@
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 	free_irq(fifo->irq, ss);
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 	return ret;
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 }
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_open);
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-static int axg_fifo_pcm_close(struct snd_pcm_substream *ss)
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+int axg_fifo_pcm_close(struct snd_soc_component *component,
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+		       struct snd_pcm_substream *ss)
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 {
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 	struct axg_fifo *fifo = axg_fifo_data(ss);
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 	int ret;
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@@ -256,26 +298,17 @@
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 	return ret;
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 }
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-
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-const struct snd_pcm_ops axg_fifo_pcm_ops = {
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-	.open =		axg_fifo_pcm_open,
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-	.close =        axg_fifo_pcm_close,
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-	.ioctl =	snd_pcm_lib_ioctl,
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-	.hw_params =	axg_fifo_pcm_hw_params,
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-	.hw_free =      axg_fifo_pcm_hw_free,
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-	.pointer =	axg_fifo_pcm_pointer,
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-	.trigger =	axg_fifo_pcm_trigger,
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-};
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-EXPORT_SYMBOL_GPL(axg_fifo_pcm_ops);
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+EXPORT_SYMBOL_GPL(axg_fifo_pcm_close);
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 int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
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 {
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 	struct snd_card *card = rtd->card->snd_card;
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 	size_t size = axg_fifo_hw.buffer_bytes_max;
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-	return snd_pcm_lib_preallocate_pages(rtd->pcm->streams[type].substream,
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-					     SNDRV_DMA_TYPE_DEV, card->dev,
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-					     size, size);
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+	snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,
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+				   SNDRV_DMA_TYPE_DEV, card->dev,
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+				   size, size);
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+	return 0;
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 }
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 EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
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@@ -283,7 +316,7 @@
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 	.reg_bits	= 32,
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 	.val_bits	= 32,
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 	.reg_stride	= 4,
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-	.max_register	= FIFO_STATUS2,
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+	.max_register	= FIFO_CTRL2,
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 };
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 int axg_fifo_probe(struct platform_device *pdev)
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@@ -291,8 +324,8 @@
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 	struct device *dev = &pdev->dev;
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 	const struct axg_fifo_match_data *data;
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 	struct axg_fifo *fifo;
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-	struct resource *res;
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 	void __iomem *regs;
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+	int ret;
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 	data = of_device_get_match_data(dev);
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 	if (!data) {
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@@ -305,8 +338,7 @@
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 		return -ENOMEM;
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 	platform_set_drvdata(pdev, fifo);
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	regs = devm_ioremap_resource(dev, res);
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+	regs = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(regs))
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 		return PTR_ERR(regs);
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@@ -339,11 +371,31 @@
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 		return fifo->irq;
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 	}
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+	fifo->field_threshold =
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+		devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
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+	if (IS_ERR(fifo->field_threshold))
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+		return PTR_ERR(fifo->field_threshold);
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+
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+	ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
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+				   &fifo->depth);
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+	if (ret) {
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+		/* Error out for anything but a missing property */
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+		if (ret != -EINVAL)
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+			return ret;
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+		/*
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+		 * If the property is missing, it might be because of an old
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+		 * DT. In such case, assume the smallest known fifo depth
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+		 */
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+		fifo->depth = 256;
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+		dev_warn(dev, "fifo depth not found, assume %u bytes\n",
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+			 fifo->depth);
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+	}
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+
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 	return devm_snd_soc_register_component(dev, data->component_drv,
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 					       data->dai_drv, 1);
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 }
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 EXPORT_SYMBOL_GPL(axg_fifo_probe);
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-MODULE_DESCRIPTION("Amlogic AXG fifo driver");
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+MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
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 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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 MODULE_LICENSE("GPL v2");