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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration. |
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3 | 4 | * |
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.. | .. |
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5 | 6 | * |
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6 | 7 | * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com> |
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7 | 8 | * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com> |
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8 | | - * |
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9 | | - * This program is free software; you can redistribute it and/or modify it |
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10 | | - * under the terms and conditions of the GNU General Public License, |
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11 | | - * version 2, as published by the Free Software Foundation. |
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12 | | - * |
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13 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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14 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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15 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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16 | | - * more details. |
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17 | | - * |
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18 | | - * |
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19 | 9 | */ |
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20 | 10 | |
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21 | 11 | #include <linux/module.h> |
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.. | .. |
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38 | 28 | #include <acpi/platform/aclinux.h> |
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39 | 29 | #include <acpi/actypes.h> |
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40 | 30 | #include <acpi/acpi_bus.h> |
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41 | | -#include <asm/cpu_device_id.h> |
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42 | | -#include <asm/iosf_mbi.h> |
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43 | 31 | #include <sound/soc-acpi.h> |
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44 | 32 | #include <sound/soc-acpi-intel-match.h> |
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45 | 33 | #include "../sst-mfld-platform.h" |
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46 | | -#include "../../common/sst-dsp.h" |
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| 34 | +#include "../../common/soc-intel-quirks.h" |
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47 | 35 | #include "sst.h" |
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48 | 36 | |
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49 | 37 | /* LPE viewpoint addresses */ |
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.. | .. |
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176 | 164 | ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset; |
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177 | 165 | ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1; |
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178 | 166 | dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base); |
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179 | | - ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base, |
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| 167 | + ctx->iram = devm_ioremap(ctx->dev, ctx->iram_base, |
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180 | 168 | ctx->pdata->res_info->iram_size); |
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181 | 169 | if (!ctx->iram) { |
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182 | 170 | dev_err(ctx->dev, "unable to map IRAM\n"); |
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.. | .. |
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186 | 174 | ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset; |
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187 | 175 | ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1; |
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188 | 176 | dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base); |
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189 | | - ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base, |
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| 177 | + ctx->dram = devm_ioremap(ctx->dev, ctx->dram_base, |
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190 | 178 | ctx->pdata->res_info->dram_size); |
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191 | 179 | if (!ctx->dram) { |
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192 | 180 | dev_err(ctx->dev, "unable to map DRAM\n"); |
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.. | .. |
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195 | 183 | |
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196 | 184 | ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset; |
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197 | 185 | dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add); |
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198 | | - ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add, |
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| 186 | + ctx->shim = devm_ioremap(ctx->dev, ctx->shim_phy_add, |
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199 | 187 | ctx->pdata->res_info->shim_size); |
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200 | 188 | if (!ctx->shim) { |
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201 | 189 | dev_err(ctx->dev, "unable to map SHIM\n"); |
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.. | .. |
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208 | 196 | /* Get mailbox addr */ |
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209 | 197 | ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset; |
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210 | 198 | dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add); |
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211 | | - ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add, |
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| 199 | + ctx->mailbox = devm_ioremap(ctx->dev, ctx->mailbox_add, |
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212 | 200 | ctx->pdata->res_info->mbox_size); |
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213 | 201 | if (!ctx->mailbox) { |
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214 | 202 | dev_err(ctx->dev, "unable to map mailbox\n"); |
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.. | .. |
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227 | 215 | ctx->ddr_base = rsrc->start; |
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228 | 216 | ctx->ddr_end = rsrc->end; |
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229 | 217 | dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base); |
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230 | | - ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base, |
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| 218 | + ctx->ddr = devm_ioremap(ctx->dev, ctx->ddr_base, |
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231 | 219 | resource_size(rsrc)); |
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232 | 220 | if (!ctx->ddr) { |
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233 | 221 | dev_err(ctx->dev, "unable to map DDR\n"); |
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.. | .. |
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243 | 231 | return 0; |
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244 | 232 | } |
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245 | 233 | |
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246 | | -static int is_byt(void) |
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247 | | -{ |
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248 | | - bool status = false; |
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249 | | - static const struct x86_cpu_id cpu_ids[] = { |
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250 | | - { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ |
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251 | | - {} |
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252 | | - }; |
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253 | | - if (x86_match_cpu(cpu_ids)) |
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254 | | - status = true; |
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255 | | - return status; |
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256 | | -} |
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257 | | - |
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258 | | -static int is_byt_cr(struct device *dev, bool *bytcr) |
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259 | | -{ |
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260 | | - int status = 0; |
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261 | | - |
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262 | | - if (IS_ENABLED(CONFIG_IOSF_MBI)) { |
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263 | | - u32 bios_status; |
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264 | | - |
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265 | | - if (!is_byt() || !iosf_mbi_available()) { |
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266 | | - /* bail silently */ |
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267 | | - return status; |
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268 | | - } |
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269 | | - |
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270 | | - status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ |
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271 | | - MBI_REG_READ, /* 0x10 */ |
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272 | | - 0x006, /* BIOS_CONFIG */ |
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273 | | - &bios_status); |
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274 | | - |
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275 | | - if (status) { |
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276 | | - dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); |
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277 | | - } else { |
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278 | | - /* bits 26:27 mirror PMIC options */ |
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279 | | - bios_status = (bios_status >> 26) & 3; |
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280 | | - |
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281 | | - if ((bios_status == 1) || (bios_status == 3)) |
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282 | | - *bytcr = true; |
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283 | | - else |
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284 | | - dev_info(dev, "BYT-CR not detected\n"); |
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285 | | - } |
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286 | | - } else { |
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287 | | - dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n"); |
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288 | | - } |
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289 | | - return status; |
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290 | | -} |
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291 | | - |
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292 | | - |
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293 | 234 | static int sst_acpi_probe(struct platform_device *pdev) |
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294 | 235 | { |
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295 | 236 | struct device *dev = &pdev->dev; |
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.. | .. |
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301 | 242 | struct platform_device *plat_dev; |
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302 | 243 | struct sst_platform_info *pdata; |
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303 | 244 | unsigned int dev_id; |
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304 | | - bool bytcr = false; |
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305 | 245 | |
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306 | 246 | id = acpi_match_device(dev->driver->acpi_match_table, dev); |
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307 | 247 | if (!id) |
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.. | .. |
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315 | 255 | return -ENODEV; |
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316 | 256 | } |
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317 | 257 | |
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318 | | - if (is_byt()) |
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| 258 | + if (soc_intel_is_byt()) |
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319 | 259 | mach->pdata = &byt_rvp_platform_data; |
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320 | 260 | else |
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321 | 261 | mach->pdata = &chv_platform_data; |
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.. | .. |
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333 | 273 | if (ret < 0) |
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334 | 274 | return ret; |
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335 | 275 | |
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336 | | - ret = is_byt_cr(dev, &bytcr); |
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337 | | - if (!((ret < 0) || (bytcr == false))) { |
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338 | | - dev_info(dev, "Detected Baytrail-CR platform\n"); |
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339 | | - |
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| 276 | + if (soc_intel_is_byt_cr(pdev)) { |
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340 | 277 | /* override resource info */ |
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341 | 278 | byt_rvp_platform_data.res_info = &bytcr_res_info; |
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342 | 279 | } |
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343 | 280 | |
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| 281 | + /* update machine parameters */ |
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| 282 | + mach->mach_params.acpi_ipc_irq_index = |
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| 283 | + pdata->res_info->acpi_ipc_irq_index; |
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| 284 | + |
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344 | 285 | plat_dev = platform_device_register_data(dev, pdata->platform, -1, |
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345 | 286 | NULL, 0); |
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346 | 287 | if (IS_ERR(plat_dev)) { |
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