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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4

 kernel/sound/soc/codecs/tlv320aic31xx.h
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@@ -2,7 +2,7 @@
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 /*
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  * ALSA SoC TLV320AIC31xx CODEC Driver Definitions
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  *
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- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
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  */
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 #ifndef _TLV320AIC31XX_H
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@@ -19,6 +19,10 @@
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 #define AIC31XX_STEREO_CLASS_D_BIT	BIT(1)
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 #define AIC31XX_MINIDSP_BIT		BIT(2)
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 #define DAC31XX_BIT			BIT(3)
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+
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+#define AIC31XX_JACK_MASK (SND_JACK_HEADPHONE | \
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+			   SND_JACK_HEADSET | \
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+			   SND_JACK_BTN_0)
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 enum aic31xx_type {
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 	AIC3100	= 0,
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@@ -173,6 +177,13 @@
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 #define AIC31XX_HPRDRVPWRSTATUS_MASK	BIT(1)
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 #define AIC31XX_SPRDRVPWRSTATUS_MASK	BIT(0)
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+/* AIC31XX_OFFLAG */
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+#define AIC31XX_DAC_OF_LEFT		BIT(7)
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+#define AIC31XX_DAC_OF_RIGHT		BIT(6)
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+#define AIC31XX_DAC_OF_SHIFTER		BIT(5)
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+#define AIC31XX_ADC_OF			BIT(3)
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+#define AIC31XX_ADC_OF_SHIFTER		BIT(1)
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+
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 /* AIC31XX_INTRDACFLAG */
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 #define AIC31XX_HPLSCDETECT		BIT(7)
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 #define AIC31XX_HPRSCDETECT		BIT(6)
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@@ -191,12 +202,41 @@
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 #define AIC31XX_SC			BIT(3)
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 #define AIC31XX_ENGINE			BIT(2)
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-/* AIC31XX_DACSETUP */
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-#define AIC31XX_SOFTSTEP_MASK		GENMASK(1, 0)
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+/* AIC31XX_GPIO1 */
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+#define AIC31XX_GPIO1_FUNC_MASK		GENMASK(5, 2)
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+#define AIC31XX_GPIO1_FUNC_SHIFT	2
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+#define AIC31XX_GPIO1_DISABLED		0x00
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+#define AIC31XX_GPIO1_INPUT		0x01
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+#define AIC31XX_GPIO1_GPI		0x02
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+#define AIC31XX_GPIO1_GPO		0x03
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+#define AIC31XX_GPIO1_CLKOUT		0x04
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+#define AIC31XX_GPIO1_INT1		0x05
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+#define AIC31XX_GPIO1_INT2		0x06
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+#define AIC31XX_GPIO1_ADC_WCLK		0x07
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+#define AIC31XX_GPIO1_SBCLK		0x08
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+#define AIC31XX_GPIO1_SWCLK		0x09
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+#define AIC31XX_GPIO1_ADC_MOD_CLK	0x10
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+#define AIC31XX_GPIO1_SDOUT		0x11
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 /* AIC31XX_DACMUTE */
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 #define AIC31XX_DACMUTE_MASK		GENMASK(3, 2)
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+/* AIC31XX_HSDETECT */
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+#define AIC31XX_HSD_ENABLE		BIT(7)
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+#define AIC31XX_HSD_TYPE_MASK		GENMASK(6, 5)
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+#define AIC31XX_HSD_TYPE_SHIFT		5
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+#define AIC31XX_HSD_NONE		0x00
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+#define AIC31XX_HSD_HP			0x01
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+#define AIC31XX_HSD_HS			0x03
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+
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+/* AIC31XX_HPDRIVER */
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+#define AIC31XX_HPD_OCMV_MASK		GENMASK(4, 3)
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+#define AIC31XX_HPD_OCMV_SHIFT		3
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+#define AIC31XX_HPD_OCMV_1_35V		0x0
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+#define AIC31XX_HPD_OCMV_1_5V		0x1
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+#define AIC31XX_HPD_OCMV_1_65V		0x2
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+#define AIC31XX_HPD_OCMV_1_8V		0x3
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+
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 /* AIC31XX_MICBIAS */
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 #define AIC31XX_MICBIAS_MASK		GENMASK(1, 0)
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 #define AIC31XX_MICBIAS_SHIFT		0