forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/sound/soc/codecs/es8396.c
....@@ -442,7 +442,7 @@
442442 		/* power up class d */
443443 		pr_debug("SND_SOC_DAPM_PRE_PMU = 0x%x\n", event);
444444 		/* read the clock configure */
445
-		regv1 = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
445
+		regv1 = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
446446 		regv1 &= 0xcf;
447447 		/* enable class d clock */
448448 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv1);
....@@ -452,7 +452,7 @@
452452 		snd_soc_component_update_bits(component, ES8396_DAC_REF_PWR_CTRL_REG6E,
453453 					      0xff, 0x34);
454454 
455
-		regv2 = snd_soc_component_read32(component, ES8396_SPK_CTRL_1_REG3C);
455
+		regv2 = snd_soc_component_read(component, ES8396_SPK_CTRL_1_REG3C);
456456 		/* set speaker ldo level */
457457 		if (es8396_valid_spkldo(es8396->spk_ldo_lvl) == false) {
458458 			pr_err("speaker LDO Level error.\n");
....@@ -473,7 +473,7 @@
473473 
474474 		snd_soc_component_write(component, ES8396_SPK_CTRL_2_REG3D, 0x10);
475475 
476
-		regv1 = snd_soc_component_read32(component, ES8396_SPK_MIXER_REG26);
476
+		regv1 = snd_soc_component_read(component, ES8396_SPK_MIXER_REG26);
477477 		/* clear pdnspkl_biasgen, clear pdnspkr_biasgen */
478478 		regv1 &= 0xee;
479479 		snd_soc_component_write(component, ES8396_SPK_MIXER_REG26, regv1);
....@@ -484,19 +484,19 @@
484484 		snd_soc_component_write(component, ES8396_DAC_LDAC_VOL_REG6A, 0x00);
485485 		snd_soc_component_write(component, ES8396_DAC_RDAC_VOL_REG6B, 0x00);
486486 
487
-		regv1 = snd_soc_component_read32(component, ES8396_HP_MIXER_BOOST_REG2B);
487
+		regv1 = snd_soc_component_read(component, ES8396_HP_MIXER_BOOST_REG2B);
488488 		regv1 &= 0xcc;
489489 		snd_soc_component_write(component, ES8396_HP_MIXER_BOOST_REG2B, regv1);
490490 
491
-		regv1 = snd_soc_component_read32(component, ES8396_CPHP_CTRL_3_REG44);
491
+		regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_3_REG44);
492492 		regv1 &= 0xcc;
493493 		snd_soc_component_write(component, ES8396_CPHP_CTRL_3_REG44, regv1);
494494 
495
-		regv1 = snd_soc_component_read32(component, ES8396_CPHP_CTRL_1_REG42);
495
+		regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_1_REG42);
496496 		regv1 &= 0xdf;
497497 		snd_soc_component_write(component, ES8396_CPHP_CTRL_1_REG42, regv1);
498498 
499
-		regv1 = snd_soc_component_read32(component, ES8396_CPHP_CTRL_2_REG43);
499
+		regv1 = snd_soc_component_read(component, ES8396_CPHP_CTRL_2_REG43);
500500 		regv1 &= 0x7f;
501501 		snd_soc_component_write(component, ES8396_CPHP_CTRL_2_REG43, regv1);
502502 		es8396->output_device_selected = 0;
....@@ -509,22 +509,22 @@
509509 	case SND_SOC_DAPM_PRE_PMD:	/* prepare power down */
510510 		pr_debug("SND_SOC_DAPM_PRE_PMD = 0x%x\n", event);
511511 		/* read the clock configure */
512
-		regv1 = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
512
+		regv1 = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
513513 		regv1 |= 0x10;
514514 		/* stop class d clock */
515515 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv1);
516516 		/* dac csm startup, dac digital still on */
517517 		/* snd_soc_component_update_bits(w->component, ES8396_DAC_CSM_REG66,
518518 				       0x01, 0x01); */
519
-		regv1 = snd_soc_component_read32(component, ES8396_SPK_EN_VOL_REG3B);
519
+		regv1 = snd_soc_component_read(component, ES8396_SPK_EN_VOL_REG3B);
520520 		regv1 &= 0x77;
521521 		/* clear enspk_l,enspk_r */
522522 		snd_soc_component_write(component, ES8396_SPK_EN_VOL_REG3B, regv1);
523523 
524
-		regv1 = snd_soc_component_read32(component, ES8396_SPK_CTRL_SRC_REG3A);
524
+		regv1 = snd_soc_component_read(component, ES8396_SPK_CTRL_SRC_REG3A);
525525 		regv1 |= 0x44;	/* set pdnspkl_biasgen, set pdnspkr_biasgen */
526526 		snd_soc_component_write(component, ES8396_SPK_CTRL_SRC_REG3A, regv1);
527
-		regv1 = snd_soc_component_read32(component, ES8396_SPK_MIXER_REG26);
527
+		regv1 = snd_soc_component_read(component, ES8396_SPK_MIXER_REG26);
528528 		/* clear pdnspkl_biasgen, clear pdnspkr_biasgen */
529529 		regv1 |= 0x11;
530530 		snd_soc_component_write(component, ES8396_SPK_MIXER_REG26, regv1);
....@@ -560,7 +560,7 @@
560560 			snd_soc_component_write(component, ES8396_SYS_MICBIAS_CTRL_REG74,
561561 						regv);
562562 		}
563
-		regv = snd_soc_component_read32(component, ES8396_ALRCK_GPIO_SEL_REG15);
563
+		regv = snd_soc_component_read(component, ES8396_ALRCK_GPIO_SEL_REG15);
564564 		if (es8396->dmic_amic == MIC_DMIC) {
565565 			regv &= 0xf0;	/* enable DMIC CLK */
566566 			regv |= 0x0A;
....@@ -570,7 +570,7 @@
570570 		snd_soc_component_write(component, ES8396_ALRCK_GPIO_SEL_REG15, regv);
571571 		break;
572572 	case SND_SOC_DAPM_POST_PMD:
573
-		regv = snd_soc_component_read32(component, ES8396_ALRCK_GPIO_SEL_REG15);
573
+		regv = snd_soc_component_read(component, ES8396_ALRCK_GPIO_SEL_REG15);
574574 		regv &= 0xf0;	/* disable DMIC CLK */
575575 		snd_soc_component_write(component, ES8396_ALRCK_GPIO_SEL_REG15, regv);
576576 		break;
....@@ -618,7 +618,7 @@
618618 		snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
619619 
620620 		/* axMixer Gain boost */
621
-		regv = snd_soc_component_read32(component, ES8396_AX_MIXER_BOOST_REG2F);
621
+		regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
622622 		regv |= 0x88;
623623 		snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
624624 		/* axmixer vol = +12db */
....@@ -627,7 +627,7 @@
627627 		snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
628628 
629629 		/* MNMixer Gain boost */
630
-		regv = snd_soc_component_read32(component, ES8396_MN_MIXER_BOOST_REG37);
630
+		regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
631631 		regv |= 0x88;
632632 		snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
633633 		/* mnmixer vol = +12db */
....@@ -700,12 +700,12 @@
700700 		snd_soc_component_update_bits(component, ES8396_DAC_REF_PWR_CTRL_REG6E,
701701 					      0xC0, 0xC0);
702702 		/* read the clock configure */
703
-		regv = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
703
+		regv = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
704704 		regv |= 0x20;
705705 		/* stop charge pump clock */
706706 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, regv);
707707 
708
-		regv = snd_soc_component_read32(component, ES8396_HP_MIXER_BOOST_REG2B);
708
+		regv = snd_soc_component_read(component, ES8396_HP_MIXER_BOOST_REG2B);
709709 		regv |= 0x11;
710710 		snd_soc_component_write(component, ES8396_HP_MIXER_BOOST_REG2B, regv);
711711 		break;
....@@ -1967,7 +1967,7 @@
19671967 		/* Allow no source specification when stopping */
19681968 		if (freq_out)
19691969 			return -EINVAL;
1970
-		reg = snd_soc_component_read32(component, ES8396_CLK_SRC_SEL_REG01);
1970
+		reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
19711971 		reg &= 0xF0;
19721972 		if (source == 0)
19731973 			reg |= 0x01;	/* clksrc2= 0, clksrc1 = 1 */
....@@ -1975,29 +1975,29 @@
19751975 			reg |= 0x09;	/* clksrc2= 1, clksrc1 = 1 */
19761976 
19771977 		snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
1978
-		reg = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
1978
+		reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
19791979 		reg |= 0x0F;
19801980 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
19811981 		pr_debug("ES8396 PLL No Clock source\n");
19821982 		break;
19831983 	case ES8396_PLL_SRC_FRM_MCLK:
1984
-		reg = snd_soc_component_read32(component, ES8396_CLK_SRC_SEL_REG01);
1984
+		reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
19851985 		reg &= 0xF3;
19861986 		reg |= 0x04;	/* clksrc2= mclk */
19871987 		/* use clk2 for pll clk source */
19881988 		snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
1989
-		reg = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
1989
+		reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
19901990 		reg |= 0x0F;
19911991 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
19921992 		pr_debug("ES8396 PLL Clock Source from MCLK pin\n");
19931993 		break;
19941994 	case ES8396_PLL_SRC_FRM_BCLK:
1995
-		reg = snd_soc_component_read32(component, ES8396_CLK_SRC_SEL_REG01);
1995
+		reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
19961996 		reg &= 0xF3;
19971997 		reg |= 0x0c;	/* clksrc2= bclk, */
19981998 		/* use clk2 for pll clk source */
19991999 		snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
2000
-		reg = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
2000
+		reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
20012001 		reg |= 0x0F;
20022002 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
20032003 		pr_debug("ES8396 PLL Clock Source from BCLK signal\n");
....@@ -2116,13 +2116,13 @@
21162116 	switch (clk_id) {
21172117 	/* the clock source form MCLK pin, don't use PLL */
21182118 	case ES8396_CLKID_MCLK:
2119
-		reg = snd_soc_component_read32(component, ES8396_CLK_SRC_SEL_REG01);
2119
+		reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
21202120 		reg &= 0xFC;
21212121 		reg |= 0x00;	/* clksrc1= mclk */
21222122 		snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
21232123 
21242124 		/* always use clk1 */
2125
-		reg = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
2125
+		reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
21262126 		reg &= 0xf0;
21272127 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
21282128 
....@@ -2158,12 +2158,12 @@
21582158 		break;
21592159 	/* the clock source form internal BCLK signal, don't use PLL */
21602160 	case ES8396_CLKID_BCLK:
2161
-		reg = snd_soc_component_read32(component, ES8396_CLK_SRC_SEL_REG01);
2161
+		reg = snd_soc_component_read(component, ES8396_CLK_SRC_SEL_REG01);
21622162 		reg &= 0xFC;
21632163 		reg |= 0x03;	/* clksrc1= bclk */
21642164 		snd_soc_component_write(component, ES8396_CLK_SRC_SEL_REG01, reg);
21652165 		/* always use clk1 */
2166
-		reg = snd_soc_component_read32(component, ES8396_CLK_CTRL_REG08);
2166
+		reg = snd_soc_component_read(component, ES8396_CLK_CTRL_REG08);
21672167 		reg &= 0xf0;
21682168 		snd_soc_component_write(component, ES8396_CLK_CTRL_REG08, reg);
21692169 
....@@ -2301,16 +2301,16 @@
23012301 
23022302 	switch (id) {
23032303 	case ES8396_SDP1:
2304
-		spc = snd_soc_component_read32(component, ES8396_SDP1_IN_FMT_REG1F) & 0x3f;
2305
-		mmcc = snd_soc_component_read32(component, ES8396_SDP_1_MS_REG12);
2304
+		spc = snd_soc_component_read(component, ES8396_SDP1_IN_FMT_REG1F) & 0x3f;
2305
+		mmcc = snd_soc_component_read(component, ES8396_SDP_1_MS_REG12);
23062306 		break;
23072307 	case ES8396_SDP2:
2308
-		spc = snd_soc_component_read32(component, ES8396_SDP2_IN_FMT_REG22) & 0x3f;
2309
-		mmcc = snd_soc_component_read32(component, ES8396_SDP_2_MS_REG13);
2308
+		spc = snd_soc_component_read(component, ES8396_SDP2_IN_FMT_REG22) & 0x3f;
2309
+		mmcc = snd_soc_component_read(component, ES8396_SDP_2_MS_REG13);
23102310 		break;
23112311 	case ES8396_SDP3:
2312
-		spc = snd_soc_component_read32(component, ES8396_SDP3_IN_FMT_REG24) & 0x3f;
2313
-		mmcc = snd_soc_component_read32(component, ES8396_SDP_3_MS_REG14);
2312
+		spc = snd_soc_component_read(component, ES8396_SDP3_IN_FMT_REG24) & 0x3f;
2313
+		mmcc = snd_soc_component_read(component, ES8396_SDP_3_MS_REG14);
23142314 		break;
23152315 	default:
23162316 		return -EINVAL;
....@@ -2398,10 +2398,10 @@
23982398 
23992399 	switch (id) {
24002400 	case ES8396_SDP1:
2401
-		bdiv = snd_soc_component_read32(component, ES8396_BCLK_DIV_M2_REG0F);
2401
+		bdiv = snd_soc_component_read(component, ES8396_BCLK_DIV_M2_REG0F);
24022402 		bdiv &= 0xe0;
24032403 		bdiv |= es8396_mclk_coeffs[mclk_coeff].bclkdiv;
2404
-		lrdiv = snd_soc_component_read32(component, ES8396_LRCK_DIV_M4_REG11);
2404
+		lrdiv = snd_soc_component_read(component, ES8396_LRCK_DIV_M4_REG11);
24052405 		lrdiv &= 0xe0;
24062406 		lrdiv |= 0x22;	/* es8396_mclk_coeffs[mclk_coeff].lrcdiv; */
24072407 		snd_soc_component_write(component, ES8396_BCLK_DIV_M2_REG0F, bdiv);
....@@ -2412,10 +2412,10 @@
24122412 		break;
24132413 	case ES8396_SDP2:
24142414 	case ES8396_SDP3:
2415
-		bdiv = snd_soc_component_read32(component, ES8396_BCLK_DIV_M1_REG0E);
2415
+		bdiv = snd_soc_component_read(component, ES8396_BCLK_DIV_M1_REG0E);
24162416 		bdiv &= 0xe0;
24172417 		bdiv |= es8396_mclk_coeffs[mclk_coeff].bclkdiv;
2418
-		lrdiv = snd_soc_component_read32(component, ES8396_LRCK_DIV_M3_REG10);
2418
+		lrdiv = snd_soc_component_read(component, ES8396_LRCK_DIV_M3_REG10);
24192419 		lrdiv &= 0xe0;
24202420 		lrdiv |= es8396_mclk_coeffs[mclk_coeff].lrcdiv;
24212421 		snd_soc_component_write(component, ES8396_BCLK_DIV_M1_REG0E, bdiv);
....@@ -2511,7 +2511,7 @@
25112511 	int i;
25122512 
25132513 	pr_debug(">>>>>>>>es8396_pcm_startup\n");
2514
-	ret = snd_soc_component_read32(component, ES8396_ADC_CSM_REG53);
2514
+	ret = snd_soc_component_read(component, ES8396_ADC_CSM_REG53);
25152515 	pr_debug("ES8396_ADC_CSM_REG53===0x%x\n", ret);
25162516 	/*
25172517 	 * set the clock source to MCLK pin
....@@ -2571,7 +2571,7 @@
25712571 		snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
25722572 
25732573 		/* axMixer Gain boost */
2574
-		regv = snd_soc_component_read32(component, ES8396_AX_MIXER_BOOST_REG2F);
2574
+		regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
25752575 		regv |= 0x88;
25762576 		snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
25772577 		/* axmixer vol = +12db */
....@@ -2580,7 +2580,7 @@
25802580 		snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
25812581 		snd_soc_component_write(component, 0x33, 0);
25822582 		/* MNMixer Gain boost */
2583
-		regv = snd_soc_component_read32(component, ES8396_MN_MIXER_BOOST_REG37);
2583
+		regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
25842584 		regv |= 0x88;
25852585 		snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
25862586 		/* mnmixer vol = +12db */
....@@ -2697,7 +2697,7 @@
26972697 		snd_soc_component_write(component, ES8396_SYS_MIC_IBIAS_EN_REG75, 0x02);
26982698 
26992699 		/* axMixer Gain boost */
2700
-		regv = snd_soc_component_read32(component, ES8396_AX_MIXER_BOOST_REG2F);
2700
+		regv = snd_soc_component_read(component, ES8396_AX_MIXER_BOOST_REG2F);
27012701 		regv |= 0x88;
27022702 		snd_soc_component_write(component, ES8396_AX_MIXER_BOOST_REG2F, regv);
27032703 		/* axmixer vol = +12db */
....@@ -2706,7 +2706,7 @@
27062706 		snd_soc_component_write(component, ES8396_AX_MIXER_REF_LP_REG31, 0x02);
27072707 		snd_soc_component_write(component, 0x33, 0);
27082708 		/* MNMixer Gain boost */
2709
-		regv = snd_soc_component_read32(component, ES8396_MN_MIXER_BOOST_REG37);
2709
+		regv = snd_soc_component_read(component, ES8396_MN_MIXER_BOOST_REG37);
27102710 		regv |= 0x88;
27112711 		snd_soc_component_write(component, ES8396_MN_MIXER_BOOST_REG37, regv);
27122712 		/* mnmixer vol = +12db */
....@@ -2757,7 +2757,7 @@
27572757 /*
27582758  * Only mute SDP IN(for dac)
27592759  */
2760
-static int es8396_aif1_mute(struct snd_soc_dai *codec_dai, int mute)
2760
+static int es8396_aif1_mute(struct snd_soc_dai *codec_dai, int mute, int stream)
27612761 {
27622762 	struct snd_soc_component *component = codec_dai->component;
27632763 	struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
....@@ -2779,7 +2779,7 @@
27792779 	return 0;
27802780 }
27812781 
2782
-static int es8396_aif2_mute(struct snd_soc_dai *codec_dai, int mute)
2782
+static int es8396_aif2_mute(struct snd_soc_dai *codec_dai, int mute, int stream)
27832783 {
27842784 	struct snd_soc_component *component = codec_dai->component;
27852785 	struct es8396_private *es8396 = snd_soc_component_get_drvdata(component);
....@@ -2812,9 +2812,10 @@
28122812 	.set_sysclk = es8396_set_dai_sysclk,
28132813 	.set_fmt = es8396_set_dai_fmt,
28142814 	.hw_params = es8396_pcm_hw_params,
2815
-	.digital_mute = es8396_aif1_mute,
2815
+	.mute_stream = es8396_aif1_mute,
28162816 	.set_pll = es8396_set_pll,
28172817 	.set_tristate = es8396_set_tristate,
2818
+	.no_capture_mute = 1,
28182819 };
28192820 
28202821 static const struct snd_soc_dai_ops es8396_aif2_dai_ops = {
....@@ -2823,8 +2824,9 @@
28232824 	.set_sysclk = es8396_set_dai_sysclk,
28242825 	.set_fmt = es8396_set_dai_fmt,
28252826 	.hw_params = es8396_pcm_hw_params,
2826
-	.digital_mute = es8396_aif2_mute,
2827
+	.mute_stream = es8396_aif2_mute,
28272828 	.set_pll = es8396_set_pll,
2829
+	.no_capture_mute = 1,
28282830 };
28292831 
28302832 static struct snd_soc_dai_driver es8396_dai[] = {
....@@ -2889,7 +2891,7 @@
28892891 	ret = clk_prepare_enable(es8396->mclk_clock);
28902892 	if (ret)
28912893 		return ret;
2892
-	regv = snd_soc_component_read32(component, ES8396_PLL_K2_REG05);
2894
+	regv = snd_soc_component_read(component, ES8396_PLL_K2_REG05);
28932895 
28942896 	if (regv == 0x00) {
28952897 		/*