hc
2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4
kernel/include/sound/hda_register.h
....@@ -79,6 +79,7 @@
7979
8080 /* stream register offsets from stream base */
8181 #define AZX_REG_SD_CTL 0x00
82
+#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */
8283 #define AZX_REG_SD_STS 0x03
8384 #define AZX_REG_SD_LPIB 0x04
8485 #define AZX_REG_SD_CBL 0x08
....@@ -118,7 +119,7 @@
118119 #define AZX_REG_VS_EM3U 0x103C
119120 #define AZX_REG_VS_EM4L 0x1040
120121 #define AZX_REG_VS_EM4U 0x1044
121
-#define AZX_REG_VS_LTRC 0x1048
122
+#define AZX_REG_VS_LTRP 0x1048
122123 #define AZX_REG_VS_D0I3C 0x104A
123124 #define AZX_REG_VS_PCE 0x104B
124125 #define AZX_REG_VS_L2MAGC 0x1050
....@@ -165,6 +166,7 @@
165166 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
166167 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
167168 SD_INT_COMPLETE)
169
+#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */
168170
169171 /* SD_STS */
170172 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
....@@ -262,6 +264,9 @@
262264 #define AZX_REG_ML_LOUTPAY 0x20
263265 #define AZX_REG_ML_LINPAY 0x30
264266
267
+/* bit0 is reserved, with BIT(1) mapping to stream1 */
268
+#define ML_LOSIDV_STREAM_MASK 0xFFFE
269
+
265270 #define ML_LCTL_SCF_MASK 0xF
266271 #define AZX_MLCTL_SPA (0x1 << 16)
267272 #define AZX_MLCTL_CPA (0x1 << 23)