.. | .. |
---|
79 | 79 | |
---|
80 | 80 | /* stream register offsets from stream base */ |
---|
81 | 81 | #define AZX_REG_SD_CTL 0x00 |
---|
| 82 | +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ |
---|
82 | 83 | #define AZX_REG_SD_STS 0x03 |
---|
83 | 84 | #define AZX_REG_SD_LPIB 0x04 |
---|
84 | 85 | #define AZX_REG_SD_CBL 0x08 |
---|
.. | .. |
---|
118 | 119 | #define AZX_REG_VS_EM3U 0x103C |
---|
119 | 120 | #define AZX_REG_VS_EM4L 0x1040 |
---|
120 | 121 | #define AZX_REG_VS_EM4U 0x1044 |
---|
121 | | -#define AZX_REG_VS_LTRC 0x1048 |
---|
| 122 | +#define AZX_REG_VS_LTRP 0x1048 |
---|
122 | 123 | #define AZX_REG_VS_D0I3C 0x104A |
---|
123 | 124 | #define AZX_REG_VS_PCE 0x104B |
---|
124 | 125 | #define AZX_REG_VS_L2MAGC 0x1050 |
---|
.. | .. |
---|
165 | 166 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ |
---|
166 | 167 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
---|
167 | 168 | SD_INT_COMPLETE) |
---|
| 169 | +#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ |
---|
168 | 170 | |
---|
169 | 171 | /* SD_STS */ |
---|
170 | 172 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ |
---|
.. | .. |
---|
262 | 264 | #define AZX_REG_ML_LOUTPAY 0x20 |
---|
263 | 265 | #define AZX_REG_ML_LINPAY 0x30 |
---|
264 | 266 | |
---|
| 267 | +/* bit0 is reserved, with BIT(1) mapping to stream1 */ |
---|
| 268 | +#define ML_LOSIDV_STREAM_MASK 0xFFFE |
---|
| 269 | + |
---|
265 | 270 | #define ML_LCTL_SCF_MASK 0xF |
---|
266 | 271 | #define AZX_MLCTL_SPA (0x1 << 16) |
---|
267 | 272 | #define AZX_MLCTL_CPA (0x1 << 23) |
---|