.. | .. |
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12 | 12 | #include <linux/slab.h> |
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13 | 13 | #include <linux/module.h> |
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14 | 14 | #include <linux/acpi.h> |
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| 15 | +#include <linux/reset.h> |
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15 | 16 | |
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16 | 17 | #include "xhci.h" |
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17 | 18 | #include "xhci-trace.h" |
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| 19 | +#include "xhci-pci.h" |
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18 | 20 | |
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19 | 21 | #define SSIC_PORT_NUM 2 |
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20 | 22 | #define SSIC_PORT_CFG2 0x880c |
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.. | .. |
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44 | 46 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
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45 | 47 | #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 |
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46 | 48 | #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 |
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| 49 | +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 |
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| 50 | +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 |
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| 51 | +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1 |
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| 52 | +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db |
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| 53 | +#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 |
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| 54 | +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 |
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| 55 | +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec |
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| 56 | +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 |
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| 57 | +#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13 |
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47 | 58 | #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af |
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| 59 | +#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13 |
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| 60 | +#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 |
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| 61 | +#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed |
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| 62 | +#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed |
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48 | 63 | |
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49 | 64 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 |
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50 | 65 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba |
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51 | 66 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb |
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52 | 67 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc |
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| 68 | + |
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53 | 69 | #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042 |
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54 | 70 | #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 |
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55 | 71 | #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242 |
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.. | .. |
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85 | 101 | |
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86 | 102 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
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87 | 103 | { |
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88 | | - struct pci_dev *pdev = to_pci_dev(dev); |
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| 104 | + struct pci_dev *pdev = to_pci_dev(dev); |
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| 105 | + struct xhci_driver_data *driver_data; |
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| 106 | + const struct pci_device_id *id; |
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| 107 | + |
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| 108 | + id = pci_match_id(pdev->driver->id_table, pdev); |
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| 109 | + |
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| 110 | + if (id && id->driver_data) { |
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| 111 | + driver_data = (struct xhci_driver_data *)id->driver_data; |
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| 112 | + xhci->quirks |= driver_data->quirks; |
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| 113 | + } |
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89 | 114 | |
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90 | 115 | /* Look for vendor-specific quirks */ |
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91 | 116 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
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.. | .. |
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135 | 160 | xhci->quirks |= XHCI_AMD_0x96_HOST; |
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136 | 161 | |
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137 | 162 | /* AMD PLL quirk */ |
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138 | | - if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) |
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| 163 | + if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) |
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139 | 164 | xhci->quirks |= XHCI_AMD_PLL_FIX; |
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140 | 165 | |
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141 | 166 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
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.. | .. |
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217 | 242 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) |
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218 | 243 | xhci->quirks |= XHCI_MISSING_CAS; |
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219 | 244 | |
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| 245 | + if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
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| 246 | + (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI || |
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| 247 | + pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI)) |
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| 248 | + xhci->quirks |= XHCI_RESET_TO_DEFAULT; |
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| 249 | + |
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| 250 | + if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
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| 251 | + (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || |
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| 252 | + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || |
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| 253 | + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI || |
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| 254 | + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || |
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| 255 | + pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || |
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| 256 | + pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || |
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| 257 | + pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || |
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| 258 | + pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI || |
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| 259 | + pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI || |
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| 260 | + pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI || |
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| 261 | + pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI)) |
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| 262 | + xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; |
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| 263 | + |
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220 | 264 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
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221 | 265 | pdev->device == PCI_DEVICE_ID_EJ168) { |
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222 | 266 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
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.. | .. |
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241 | 285 | pdev->device == 0x3432) |
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242 | 286 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
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243 | 287 | |
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| 288 | + if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { |
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| 289 | + xhci->quirks |= XHCI_LPM_SUPPORT; |
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| 290 | + xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; |
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| 291 | + } |
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| 292 | + |
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244 | 293 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
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245 | | - pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) |
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| 294 | + pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { |
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| 295 | + /* |
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| 296 | + * try to tame the ASMedia 1042 controller which reports 0.96 |
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| 297 | + * but appears to behave more like 1.0 |
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| 298 | + */ |
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| 299 | + xhci->quirks |= XHCI_SPURIOUS_SUCCESS; |
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246 | 300 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
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| 301 | + } |
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247 | 302 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
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248 | 303 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) { |
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249 | 304 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
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.. | .. |
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266 | 321 | pdev->vendor == PCI_VENDOR_ID_CAVIUM) && |
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267 | 322 | pdev->device == 0x9026) |
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268 | 323 | xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; |
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| 324 | + |
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| 325 | + if (pdev->vendor == PCI_VENDOR_ID_AMD && |
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| 326 | + (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 || |
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| 327 | + pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4)) |
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| 328 | + xhci->quirks |= XHCI_NO_SOFT_RETRY; |
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| 329 | + |
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| 330 | + /* xHC spec requires PCI devices to support D3hot and D3cold */ |
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| 331 | + if (xhci->hci_version >= 0x120) |
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| 332 | + xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; |
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269 | 333 | |
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270 | 334 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
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271 | 335 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
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.. | .. |
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326 | 390 | { |
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327 | 391 | int retval; |
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328 | 392 | struct xhci_hcd *xhci; |
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329 | | - struct hc_driver *driver; |
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330 | 393 | struct usb_hcd *hcd; |
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| 394 | + struct xhci_driver_data *driver_data; |
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| 395 | + struct reset_control *reset; |
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331 | 396 | |
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332 | | - driver = (struct hc_driver *)id->driver_data; |
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| 397 | + driver_data = (struct xhci_driver_data *)id->driver_data; |
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| 398 | + if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) { |
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| 399 | + retval = renesas_xhci_check_request_fw(dev, id); |
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| 400 | + if (retval) |
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| 401 | + return retval; |
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| 402 | + } |
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| 403 | + |
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| 404 | + reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); |
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| 405 | + if (IS_ERR(reset)) |
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| 406 | + return PTR_ERR(reset); |
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| 407 | + reset_control_reset(reset); |
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333 | 408 | |
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334 | 409 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ |
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335 | 410 | pm_runtime_get_noresume(&dev->dev); |
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.. | .. |
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340 | 415 | * to say USB 2.0, but I'm not sure what the implications would be in |
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341 | 416 | * the other parts of the HCD code. |
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342 | 417 | */ |
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343 | | - retval = usb_hcd_pci_probe(dev, id); |
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| 418 | + retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver); |
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344 | 419 | |
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345 | 420 | if (retval) |
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346 | 421 | goto put_runtime_pm; |
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.. | .. |
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348 | 423 | /* USB 2.0 roothub is stored in the PCI device now. */ |
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349 | 424 | hcd = dev_get_drvdata(&dev->dev); |
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350 | 425 | xhci = hcd_to_xhci(hcd); |
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351 | | - xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, |
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352 | | - pci_name(dev), hcd); |
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| 426 | + xhci->reset = reset; |
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| 427 | + xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, |
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| 428 | + pci_name(dev), hcd); |
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353 | 429 | if (!xhci->shared_hcd) { |
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354 | 430 | retval = -ENOMEM; |
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355 | 431 | goto dealloc_usb2_hcd; |
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.. | .. |
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372 | 448 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
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373 | 449 | pm_runtime_put_noidle(&dev->dev); |
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374 | 450 | |
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| 451 | + if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) |
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| 452 | + pm_runtime_allow(&dev->dev); |
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| 453 | + |
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375 | 454 | return 0; |
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376 | 455 | |
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377 | 456 | put_usb3_hcd: |
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.. | .. |
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388 | 467 | struct xhci_hcd *xhci; |
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389 | 468 | |
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390 | 469 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); |
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| 470 | + if (xhci->quirks & XHCI_RENESAS_FW_QUIRK) |
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| 471 | + renesas_xhci_pci_exit(dev); |
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| 472 | + |
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391 | 473 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
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| 474 | + |
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| 475 | + if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) |
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| 476 | + pm_runtime_forbid(&dev->dev); |
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| 477 | + |
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392 | 478 | if (xhci->shared_hcd) { |
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393 | 479 | usb_remove_hcd(xhci->shared_hcd); |
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394 | 480 | usb_put_hcd(xhci->shared_hcd); |
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.. | .. |
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501 | 587 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
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502 | 588 | int retval = 0; |
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503 | 589 | |
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| 590 | + reset_control_reset(xhci->reset); |
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| 591 | + |
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504 | 592 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
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505 | 593 | * not support xHCI natively. That means that during system resume, it |
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506 | 594 | * may switch the ports back to EHCI so that users can use their |
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.. | .. |
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547 | 635 | |
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548 | 636 | /*-------------------------------------------------------------------------*/ |
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549 | 637 | |
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| 638 | +static const struct xhci_driver_data reneses_data = { |
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| 639 | + .quirks = XHCI_RENESAS_FW_QUIRK, |
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| 640 | + .firmware = "renesas_usb_fw.mem", |
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| 641 | +}; |
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| 642 | + |
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550 | 643 | /* PCI driver selection metadata; PCI hotplugging uses this */ |
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551 | | -static const struct pci_device_id pci_ids[] = { { |
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| 644 | +static const struct pci_device_id pci_ids[] = { |
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| 645 | + { PCI_DEVICE(0x1912, 0x0014), |
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| 646 | + .driver_data = (unsigned long)&reneses_data, |
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| 647 | + }, |
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| 648 | + { PCI_DEVICE(0x1912, 0x0015), |
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| 649 | + .driver_data = (unsigned long)&reneses_data, |
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| 650 | + }, |
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552 | 651 | /* handle any USB 3.0 xHCI controller */ |
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553 | | - PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), |
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554 | | - .driver_data = (unsigned long) &xhci_pci_hc_driver, |
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| 652 | + { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), |
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555 | 653 | }, |
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556 | 654 | { /* end: all zeroes */ } |
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557 | 655 | }; |
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558 | 656 | MODULE_DEVICE_TABLE(pci, pci_ids); |
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559 | 657 | |
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| 658 | +/* |
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| 659 | + * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't |
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| 660 | + * load firmware, so don't encumber the xhci-pci driver with it. |
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| 661 | + */ |
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| 662 | +#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS) |
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| 663 | +MODULE_FIRMWARE("renesas_usb_fw.mem"); |
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| 664 | +#endif |
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| 665 | + |
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560 | 666 | /* pci driver glue; this is a "new style" PCI driver module */ |
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561 | 667 | static struct pci_driver xhci_pci_driver = { |
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562 | | - .name = (char *) hcd_name, |
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| 668 | + .name = hcd_name, |
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563 | 669 | .id_table = pci_ids, |
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564 | 670 | |
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565 | 671 | .probe = xhci_pci_probe, |
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