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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/drivers/pinctrl/pinctrl-amd.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * GPIO driver for AMD
34  *
....@@ -5,13 +6,8 @@
56  * Authors: Ken Xue <Ken.Xue@amd.com>
67  *      Wu, Jeff <Jeff.Wu@amd.com>
78  *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms and conditions of the GNU General Public License,
10
- * version 2, as published by the Free Software Foundation.
11
- *
129  * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
1310  *			Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14
- *
1511  */
1612 
1713 #include <linux/err.h>
....@@ -24,7 +20,7 @@
2420 #include <linux/errno.h>
2521 #include <linux/log2.h>
2622 #include <linux/io.h>
27
-#include <linux/gpio.h>
23
+#include <linux/gpio/driver.h>
2824 #include <linux/slab.h>
2925 #include <linux/platform_device.h>
3026 #include <linux/mutex.h>
....@@ -50,7 +46,10 @@
5046 	pin_reg = readl(gpio_dev->base + offset * 4);
5147 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
5248 
53
-	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
49
+	if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50
+		return GPIO_LINE_DIRECTION_OUT;
51
+
52
+	return GPIO_LINE_DIRECTION_IN;
5453 }
5554 
5655 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
....@@ -418,21 +417,12 @@
418417 {
419418 	int ret = 0;
420419 	u32 pin_reg, pin_reg_irq_en, mask;
421
-	unsigned long flags, irq_flags;
420
+	unsigned long flags;
422421 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423422 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
424423 
425424 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
426425 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
427
-
428
-	/* Ignore the settings coming from the client and
429
-	 * read the values from the ACPI tables
430
-	 * while setting the trigger type
431
-	 */
432
-
433
-	irq_flags = irq_get_trigger_type(d->irq);
434
-	if (irq_flags != IRQ_TYPE_NONE)
435
-		type = irq_flags;
436426 
437427 	switch (type & IRQ_TYPE_SENSE_MASK) {
438428 	case IRQ_TYPE_EDGE_RISING:
....@@ -482,7 +472,7 @@
482472 	/*
483473 	 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
484474 	 * debounce registers of any GPIO will block wake/interrupt status
485
-	 * generation for *all* GPIOs for a lenght of time that depends on
475
+	 * generation for *all* GPIOs for a length of time that depends on
486476 	 * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
487477 	 * INTERRUPT_ENABLE bit will read as 0.
488478 	 *
....@@ -774,6 +764,34 @@
774764 	.pin_config_group_set = amd_pinconf_group_set,
775765 };
776766 
767
+static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
768
+{
769
+	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
770
+	unsigned long flags;
771
+	u32 pin_reg, mask;
772
+	int i;
773
+
774
+	mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
775
+		BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
776
+		BIT(WAKE_CNTRL_OFF_S4);
777
+
778
+	for (i = 0; i < desc->npins; i++) {
779
+		int pin = desc->pins[i].number;
780
+		const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
781
+
782
+		if (!pd)
783
+			continue;
784
+
785
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
786
+
787
+		pin_reg = readl(gpio_dev->base + i * 4);
788
+		pin_reg &= ~mask;
789
+		writel(pin_reg, gpio_dev->base + i * 4);
790
+
791
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
792
+	}
793
+}
794
+
777795 #ifdef CONFIG_PM_SLEEP
778796 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
779797 {
....@@ -795,9 +813,9 @@
795813 
796814 static int amd_gpio_suspend(struct device *dev)
797815 {
798
-	struct platform_device *pdev = to_platform_device(dev);
799
-	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
816
+	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
800817 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
818
+	unsigned long flags;
801819 	int i;
802820 
803821 	for (i = 0; i < desc->npins; i++) {
....@@ -806,7 +824,9 @@
806824 		if (!amd_gpio_should_save(gpio_dev, pin))
807825 			continue;
808826 
809
-		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
827
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
828
+		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
829
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
810830 	}
811831 
812832 	return 0;
....@@ -814,9 +834,9 @@
814834 
815835 static int amd_gpio_resume(struct device *dev)
816836 {
817
-	struct platform_device *pdev = to_platform_device(dev);
818
-	struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
837
+	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
819838 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
839
+	unsigned long flags;
820840 	int i;
821841 
822842 	for (i = 0; i < desc->npins; i++) {
....@@ -825,7 +845,10 @@
825845 		if (!amd_gpio_should_save(gpio_dev, pin))
826846 			continue;
827847 
828
-		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
848
+		raw_spin_lock_irqsave(&gpio_dev->lock, flags);
849
+		gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
850
+		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
851
+		raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
829852 	}
830853 
831854 	return 0;
....@@ -851,6 +874,7 @@
851874 	int irq_base;
852875 	struct resource *res;
853876 	struct amd_gpio *gpio_dev;
877
+	struct gpio_irq_chip *girq;
854878 
855879 	gpio_dev = devm_kzalloc(&pdev->dev,
856880 				sizeof(struct amd_gpio), GFP_KERNEL);
....@@ -865,16 +889,14 @@
865889 		return -EINVAL;
866890 	}
867891 
868
-	gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
892
+	gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
869893 						resource_size(res));
870894 	if (!gpio_dev->base)
871895 		return -ENOMEM;
872896 
873897 	irq_base = platform_get_irq(pdev, 0);
874
-	if (irq_base < 0) {
875
-		dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
898
+	if (irq_base < 0)
876899 		return irq_base;
877
-	}
878900 
879901 #ifdef CONFIG_PM_SLEEP
880902 	gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
....@@ -914,6 +936,18 @@
914936 		return PTR_ERR(gpio_dev->pctrl);
915937 	}
916938 
939
+	/* Disable and mask interrupts */
940
+	amd_gpio_irq_init(gpio_dev);
941
+
942
+	girq = &gpio_dev->gc.irq;
943
+	girq->chip = &amd_gpio_irqchip;
944
+	/* This will let us handle the parent IRQ in the driver */
945
+	girq->parent_handler = NULL;
946
+	girq->num_parents = 0;
947
+	girq->parents = NULL;
948
+	girq->default_type = IRQ_TYPE_NONE;
949
+	girq->handler = handle_simple_irq;
950
+
917951 	ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
918952 	if (ret)
919953 		return ret;
....@@ -925,19 +959,8 @@
925959 		goto out2;
926960 	}
927961 
928
-	ret = gpiochip_irqchip_add(&gpio_dev->gc,
929
-				&amd_gpio_irqchip,
930
-				0,
931
-				handle_simple_irq,
932
-				IRQ_TYPE_NONE);
933
-	if (ret) {
934
-		dev_err(&pdev->dev, "could not add irqchip\n");
935
-		ret = -ENODEV;
936
-		goto out2;
937
-	}
938
-
939
-	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
940
-			       KBUILD_MODNAME, gpio_dev);
962
+	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
963
+			       IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
941964 	if (ret)
942965 		goto out2;
943966 
....@@ -963,6 +986,7 @@
963986 	return 0;
964987 }
965988 
989
+#ifdef CONFIG_ACPI
966990 static const struct acpi_device_id amd_gpio_acpi_match[] = {
967991 	{ "AMD0030", 0 },
968992 	{ "AMDI0030", 0},
....@@ -970,6 +994,7 @@
970994 	{ },
971995 };
972996 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
997
+#endif
973998 
974999 static struct platform_driver amd_gpio_driver = {
9751000 	.driver		= {