forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 
 kernel/drivers/pinctrl/intel/pinctrl-merrifield.c
....@@ -6,7 +6,7 @@
66  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
77  */
88 
9
-#include <linux/bitops.h>
9
+#include <linux/bits.h>
1010 #include <linux/err.h>
1111 #include <linux/io.h>
1212 #include <linux/module.h>
....@@ -135,7 +135,7 @@
135135 	PINCTRL_PIN(43, "GP83_SD_D3"),
136136 	PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
137137 	PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
138
-	PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"),
138
+	PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
139139 	PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
140140 	PINCTRL_PIN(48, "GP87_SD_PD"),
141141 	PINCTRL_PIN(49, "GP89_SD_WP"),
....@@ -171,28 +171,28 @@
171171 	PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
172172 	PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
173173 	/* Family 6: GP SSP (22 pins) */
174
-	PINCTRL_PIN(79, "GP120_SPI_3_CLK"),
175
-	PINCTRL_PIN(80, "GP121_SPI_3_SS"),
176
-	PINCTRL_PIN(81, "GP122_SPI_3_RXD"),
177
-	PINCTRL_PIN(82, "GP123_SPI_3_TXD"),
178
-	PINCTRL_PIN(83, "GP102_SPI_4_CLK"),
179
-	PINCTRL_PIN(84, "GP103_SPI_4_SS_0"),
180
-	PINCTRL_PIN(85, "GP104_SPI_4_SS_1"),
181
-	PINCTRL_PIN(86, "GP105_SPI_4_SS_2"),
182
-	PINCTRL_PIN(87, "GP106_SPI_4_SS_3"),
183
-	PINCTRL_PIN(88, "GP107_SPI_4_RXD"),
184
-	PINCTRL_PIN(89, "GP108_SPI_4_TXD"),
185
-	PINCTRL_PIN(90, "GP109_SPI_5_CLK"),
186
-	PINCTRL_PIN(91, "GP110_SPI_5_SS_0"),
187
-	PINCTRL_PIN(92, "GP111_SPI_5_SS_1"),
188
-	PINCTRL_PIN(93, "GP112_SPI_5_SS_2"),
189
-	PINCTRL_PIN(94, "GP113_SPI_5_SS_3"),
190
-	PINCTRL_PIN(95, "GP114_SPI_5_RXD"),
191
-	PINCTRL_PIN(96, "GP115_SPI_5_TXD"),
192
-	PINCTRL_PIN(97, "GP116_SPI_6_CLK"),
193
-	PINCTRL_PIN(98, "GP117_SPI_6_SS"),
194
-	PINCTRL_PIN(99, "GP118_SPI_6_RXD"),
195
-	PINCTRL_PIN(100, "GP119_SPI_6_TXD"),
174
+	PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
175
+	PINCTRL_PIN(80, "GP121_SPI_0_SS"),
176
+	PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
177
+	PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
178
+	PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
179
+	PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
180
+	PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
181
+	PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
182
+	PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
183
+	PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
184
+	PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
185
+	PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
186
+	PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
187
+	PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
188
+	PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
189
+	PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
190
+	PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
191
+	PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
192
+	PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
193
+	PINCTRL_PIN(98, "GP117_SPI_3_SS"),
194
+	PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
195
+	PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
196196 	/* Family 7: I2C (14 pins) */
197197 	PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
198198 	PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
....@@ -340,6 +340,7 @@
340340 };
341341 
342342 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
343
+static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
343344 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
344345 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
345346 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
....@@ -351,6 +352,7 @@
351352 
352353 static const struct intel_pingroup mrfld_groups[] = {
353354 	PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
355
+	PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
354356 	PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
355357 	PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
356358 	PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
....@@ -362,6 +364,7 @@
362364 };
363365 
364366 static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
367
+static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
365368 static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
366369 static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
367370 static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
....@@ -373,6 +376,7 @@
373376 
374377 static const struct intel_function mrfld_functions[] = {
375378 	FUNCTION("sdio", mrfld_sdio_groups),
379
+	FUNCTION("i2s2", mrfld_i2s2_groups),
376380 	FUNCTION("spi5", mrfld_spi5_groups),
377381 	FUNCTION("uart0", mrfld_uart0_groups),
378382 	FUNCTION("uart1", mrfld_uart1_groups),
....@@ -476,6 +480,34 @@
476480 	return family->regs + BUFCFG_OFFSET + bufno * 4;
477481 }
478482 
483
+static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
484
+{
485
+	void __iomem *bufcfg;
486
+
487
+	if (!mrfld_buf_available(mp, pin))
488
+		return -EBUSY;
489
+
490
+	bufcfg = mrfld_get_bufcfg(mp, pin);
491
+	*value = readl(bufcfg);
492
+
493
+	return 0;
494
+}
495
+
496
+static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
497
+				u32 bits, u32 mask)
498
+{
499
+	void __iomem *bufcfg;
500
+	u32 value;
501
+
502
+	bufcfg = mrfld_get_bufcfg(mp, pin);
503
+	value = readl(bufcfg);
504
+
505
+	value &= ~mask;
506
+	value |= bits & mask;
507
+
508
+	writel(value, bufcfg);
509
+}
510
+
479511 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
480512 {
481513 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
....@@ -505,16 +537,14 @@
505537 			       unsigned int pin)
506538 {
507539 	struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
508
-	void __iomem *bufcfg;
509540 	u32 value, mode;
541
+	int ret;
510542 
511
-	if (!mrfld_buf_available(mp, pin)) {
543
+	ret = mrfld_read_bufcfg(mp, pin, &value);
544
+	if (ret) {
512545 		seq_puts(s, "not available");
513546 		return;
514547 	}
515
-
516
-	bufcfg = mrfld_get_bufcfg(mp, pin);
517
-	value = readl(bufcfg);
518548 
519549 	mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
520550 	if (!mode)
....@@ -557,21 +587,6 @@
557587 	*groups = mp->functions[function].groups;
558588 	*ngroups = mp->functions[function].ngroups;
559589 	return 0;
560
-}
561
-
562
-static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
563
-				u32 bits, u32 mask)
564
-{
565
-	void __iomem *bufcfg;
566
-	u32 value;
567
-
568
-	bufcfg = mrfld_get_bufcfg(mp, pin);
569
-	value = readl(bufcfg);
570
-
571
-	value &= ~mask;
572
-	value |= bits & mask;
573
-
574
-	writel(value, bufcfg);
575590 }
576591 
577592 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
....@@ -637,11 +652,12 @@
637652 	enum pin_config_param param = pinconf_to_config_param(*config);
638653 	u32 value, term;
639654 	u16 arg = 0;
655
+	int ret;
640656 
641
-	if (!mrfld_buf_available(mp, pin))
657
+	ret = mrfld_read_bufcfg(mp, pin, &value);
658
+	if (ret)
642659 		return -ENOTSUPP;
643660 
644
-	value = readl(mrfld_get_bufcfg(mp, pin));
645661 	term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
646662 
647663 	switch (param) {
....@@ -881,7 +897,6 @@
881897 {
882898 	struct mrfld_family *families;
883899 	struct mrfld_pinctrl *mp;
884
-	struct resource *mem;
885900 	void __iomem *regs;
886901 	size_t nfamilies;
887902 	unsigned int i;
....@@ -893,8 +908,7 @@
893908 	mp->dev = &pdev->dev;
894909 	raw_spin_lock_init(&mp->lock);
895910 
896
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897
-	regs = devm_ioremap_resource(&pdev->dev, mem);
911
+	regs = devm_platform_ioremap_resource(pdev, 0);
898912 	if (IS_ERR(regs))
899913 		return PTR_ERR(regs);
900914