~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,18 +1,9 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright © 2010-2015 Broadcom Corporation
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 as
6		- * published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14	6	#include <linux/clk.h>
15		-#include <linux/version.h>
16	7	#include <linux/module.h>
17	8	#include <linux/init.h>
18	9	#include <linux/delay.h>
..	..	@@ -92,6 +83,12 @@
92	83	#define FLASH_DMA_ECC_ERROR (1 << 8)
93	84	#define FLASH_DMA_CORR_ERROR (1 << 9)
94	85
	86	+/* Bitfields for DMA_MODE */
	87	+#define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
	88	+#define FLASH_DMA_MODE_MODE BIT(0) /* link list */
	89	+#define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR \| \
	90	+ FLASH_DMA_MODE_MODE)
	91	+
95	92	/* 512B flash cache in the NAND controller HW */
96	93	#define FC_SHIFT 9U
97	94	#define FC_BYTES 512U
..	..	@@ -104,6 +101,102 @@
104	101	#define NAND_CTRL_RDY (INTFC_CTLR_READY \| INTFC_FLASH_READY)
105	102	#define NAND_POLL_STATUS_TIMEOUT_MS 100
106	103
	104	+#define EDU_CMD_WRITE 0x00
	105	+#define EDU_CMD_READ 0x01
	106	+#define EDU_STATUS_ACTIVE BIT(0)
	107	+#define EDU_ERR_STATUS_ERRACK BIT(0)
	108	+#define EDU_DONE_MASK GENMASK(1, 0)
	109	+
	110	+#define EDU_CONFIG_MODE_NAND BIT(0)
	111	+#define EDU_CONFIG_SWAP_BYTE BIT(1)
	112	+#ifdef CONFIG_CPU_BIG_ENDIAN
	113	+#define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE
	114	+#else
	115	+#define EDU_CONFIG_SWAP_CFG 0
	116	+#endif
	117	+
	118	+/* edu registers */
	119	+enum edu_reg {
	120	+ EDU_CONFIG = 0,
	121	+ EDU_DRAM_ADDR,
	122	+ EDU_EXT_ADDR,
	123	+ EDU_LENGTH,
	124	+ EDU_CMD,
	125	+ EDU_STOP,
	126	+ EDU_STATUS,
	127	+ EDU_DONE,
	128	+ EDU_ERR_STATUS,
	129	+};
	130	+
	131	+static const u16 edu_regs[] = {
	132	+ [EDU_CONFIG] = 0x00,
	133	+ [EDU_DRAM_ADDR] = 0x04,
	134	+ [EDU_EXT_ADDR] = 0x08,
	135	+ [EDU_LENGTH] = 0x0c,
	136	+ [EDU_CMD] = 0x10,
	137	+ [EDU_STOP] = 0x14,
	138	+ [EDU_STATUS] = 0x18,
	139	+ [EDU_DONE] = 0x1c,
	140	+ [EDU_ERR_STATUS] = 0x20,
	141	+};
	142	+
	143	+/* flash_dma registers */
	144	+enum flash_dma_reg {
	145	+ FLASH_DMA_REVISION = 0,
	146	+ FLASH_DMA_FIRST_DESC,
	147	+ FLASH_DMA_FIRST_DESC_EXT,
	148	+ FLASH_DMA_CTRL,
	149	+ FLASH_DMA_MODE,
	150	+ FLASH_DMA_STATUS,
	151	+ FLASH_DMA_INTERRUPT_DESC,
	152	+ FLASH_DMA_INTERRUPT_DESC_EXT,
	153	+ FLASH_DMA_ERROR_STATUS,
	154	+ FLASH_DMA_CURRENT_DESC,
	155	+ FLASH_DMA_CURRENT_DESC_EXT,
	156	+};
	157	+
	158	+/* flash_dma registers v0*/
	159	+static const u16 flash_dma_regs_v0[] = {
	160	+ [FLASH_DMA_REVISION] = 0x00,
	161	+ [FLASH_DMA_FIRST_DESC] = 0x04,
	162	+ [FLASH_DMA_CTRL] = 0x08,
	163	+ [FLASH_DMA_MODE] = 0x0c,
	164	+ [FLASH_DMA_STATUS] = 0x10,
	165	+ [FLASH_DMA_INTERRUPT_DESC] = 0x14,
	166	+ [FLASH_DMA_ERROR_STATUS] = 0x18,
	167	+ [FLASH_DMA_CURRENT_DESC] = 0x1c,
	168	+};
	169	+
	170	+/* flash_dma registers v1*/
	171	+static const u16 flash_dma_regs_v1[] = {
	172	+ [FLASH_DMA_REVISION] = 0x00,
	173	+ [FLASH_DMA_FIRST_DESC] = 0x04,
	174	+ [FLASH_DMA_FIRST_DESC_EXT] = 0x08,
	175	+ [FLASH_DMA_CTRL] = 0x0c,
	176	+ [FLASH_DMA_MODE] = 0x10,
	177	+ [FLASH_DMA_STATUS] = 0x14,
	178	+ [FLASH_DMA_INTERRUPT_DESC] = 0x18,
	179	+ [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c,
	180	+ [FLASH_DMA_ERROR_STATUS] = 0x20,
	181	+ [FLASH_DMA_CURRENT_DESC] = 0x24,
	182	+ [FLASH_DMA_CURRENT_DESC_EXT] = 0x28,
	183	+};
	184	+
	185	+/* flash_dma registers v4 */
	186	+static const u16 flash_dma_regs_v4[] = {
	187	+ [FLASH_DMA_REVISION] = 0x00,
	188	+ [FLASH_DMA_FIRST_DESC] = 0x08,
	189	+ [FLASH_DMA_FIRST_DESC_EXT] = 0x0c,
	190	+ [FLASH_DMA_CTRL] = 0x10,
	191	+ [FLASH_DMA_MODE] = 0x14,
	192	+ [FLASH_DMA_STATUS] = 0x18,
	193	+ [FLASH_DMA_INTERRUPT_DESC] = 0x20,
	194	+ [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24,
	195	+ [FLASH_DMA_ERROR_STATUS] = 0x28,
	196	+ [FLASH_DMA_CURRENT_DESC] = 0x30,
	197	+ [FLASH_DMA_CURRENT_DESC_EXT] = 0x34,
	198	+};
	199	+
107	200	/* Controller feature flags */
108	201	enum {
109	202	BRCMNAND_HAS_1K_SECTORS = BIT(0),
..	..	@@ -111,6 +204,8 @@
111	204	BRCMNAND_HAS_CACHE_MODE = BIT(2),
112	205	BRCMNAND_HAS_WP = BIT(3),
113	206	};
	207	+
	208	+struct brcmnand_host;
114	209
115	210	struct brcmnand_controller {
116	211	struct device *dev;
..	..	@@ -130,14 +225,31 @@
130	225
131	226	int cmd_pending;
132	227	bool dma_pending;
	228	+ bool edu_pending;
133	229	struct completion done;
134	230	struct completion dma_done;
	231	+ struct completion edu_done;
135	232
136	233	/* List of NAND hosts (one for each chip-select) */
137	234	struct list_head host_list;
138	235
	236	+ /* EDU info, per-transaction */
	237	+ const u16 *edu_offsets;
	238	+ void __iomem *edu_base;
	239	+ int edu_irq;
	240	+ int edu_count;
	241	+ u64 edu_dram_addr;
	242	+ u32 edu_ext_addr;
	243	+ u32 edu_cmd;
	244	+ u32 edu_config;
	245	+
	246	+ /* flash_dma reg */
	247	+ const u16 *flash_dma_offsets;
139	248	struct brcm_nand_dma_desc *dma_desc;
140	249	dma_addr_t dma_pa;
	250	+
	251	+ int (dma_trans)(struct brcmnand_host host, u64 addr, u32 *buf,
	252	+ u32 len, u8 dma_cmd);
141	253
142	254	/* in-memory cache of the FLASH_CACHE, used only for some commands */
143	255	u8 flash_cache[FC_BYTES];
..	..	@@ -151,6 +263,7 @@
151	263	const unsigned int *block_sizes;
152	264	unsigned int max_page_size;
153	265	const unsigned int *page_sizes;
	266	+ unsigned int page_size_shift;
154	267	unsigned int max_oob;
155	268	u32 features;
156	269
..	..	@@ -159,6 +272,8 @@
159	272	u32 nand_cs_nand_xor;
160	273	u32 corr_stat_threshold;
161	274	u32 flash_dma_mode;
	275	+ u32 flash_edu_mode;
	276	+ bool pio_poll_mode;
162	277	};
163	278
164	279	struct brcmnand_cfg {
..	..	@@ -223,8 +338,38 @@
223	338	BRCMNAND_FC_BASE,
224	339	};
225	340
226		-/* BRCMNAND v4.0 */
227		-static const u16 brcmnand_regs_v40[] = {
	341	+/* BRCMNAND v2.1-v2.2 */
	342	+static const u16 brcmnand_regs_v21[] = {
	343	+ [BRCMNAND_CMD_START] = 0x04,
	344	+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
	345	+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
	346	+ [BRCMNAND_INTFC_STATUS] = 0x5c,
	347	+ [BRCMNAND_CS_SELECT] = 0x14,
	348	+ [BRCMNAND_CS_XOR] = 0x18,
	349	+ [BRCMNAND_LL_OP] = 0,
	350	+ [BRCMNAND_CS0_BASE] = 0x40,
	351	+ [BRCMNAND_CS1_BASE] = 0,
	352	+ [BRCMNAND_CORR_THRESHOLD] = 0,
	353	+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
	354	+ [BRCMNAND_UNCORR_COUNT] = 0,
	355	+ [BRCMNAND_CORR_COUNT] = 0,
	356	+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
	357	+ [BRCMNAND_CORR_ADDR] = 0x64,
	358	+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
	359	+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
	360	+ [BRCMNAND_SEMAPHORE] = 0x50,
	361	+ [BRCMNAND_ID] = 0x54,
	362	+ [BRCMNAND_ID_EXT] = 0,
	363	+ [BRCMNAND_LL_RDATA] = 0,
	364	+ [BRCMNAND_OOB_READ_BASE] = 0x20,
	365	+ [BRCMNAND_OOB_READ_10_BASE] = 0,
	366	+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
	367	+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
	368	+ [BRCMNAND_FC_BASE] = 0x200,
	369	+};
	370	+
	371	+/* BRCMNAND v3.3-v4.0 */
	372	+static const u16 brcmnand_regs_v33[] = {
228	373	[BRCMNAND_CMD_START] = 0x04,
229	374	[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
230	375	[BRCMNAND_CMD_ADDRESS] = 0x0c,
..	..	@@ -421,6 +566,9 @@
421	566	CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
422	567	CFG_DEVICE_SIZE_SHIFT = 24,
423	568
	569	+ /* Only for v2.1 */
	570	+ CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
	571	+
424	572	/* Only for pre-v7.1 (with no CFG_EXT register) */
425	573	CFG_PAGE_SIZE_SHIFT = 20,
426	574	CFG_BLK_SIZE_SHIFT = 28,
..	..	@@ -456,12 +604,16 @@
456	604	{
457	605	static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
458	606	static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
459		- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
	607	+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
	608	+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
	609	+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
	610	+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
	611	+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
460	612
461	613	ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
462	614
463		- /* Only support v4.0+? */
464		- if (ctrl->nand_version < 0x0400) {
	615	+ /* Only support v2.1+ */
	616	+ if (ctrl->nand_version < 0x0201) {
465	617	dev_err(ctrl->dev, "version %#x not supported\n",
466	618	ctrl->nand_version);
467	619	return -ENODEV;
..	..	@@ -470,14 +622,16 @@
470	622	/* Register offsets */
471	623	if (ctrl->nand_version >= 0x0702)
472	624	ctrl->reg_offsets = brcmnand_regs_v72;
473		- else if (ctrl->nand_version >= 0x0701)
	625	+ else if (ctrl->nand_version == 0x0701)
474	626	ctrl->reg_offsets = brcmnand_regs_v71;
475	627	else if (ctrl->nand_version >= 0x0600)
476	628	ctrl->reg_offsets = brcmnand_regs_v60;
477	629	else if (ctrl->nand_version >= 0x0500)
478	630	ctrl->reg_offsets = brcmnand_regs_v50;
479		- else if (ctrl->nand_version >= 0x0400)
480		- ctrl->reg_offsets = brcmnand_regs_v40;
	631	+ else if (ctrl->nand_version >= 0x0303)
	632	+ ctrl->reg_offsets = brcmnand_regs_v33;
	633	+ else if (ctrl->nand_version >= 0x0201)
	634	+ ctrl->reg_offsets = brcmnand_regs_v21;
481	635
482	636	/* Chip-select stride */
483	637	if (ctrl->nand_version >= 0x0701)
..	..	@@ -503,20 +657,38 @@
503	657	ctrl->max_page_size = 16 * 1024;
504	658	ctrl->max_block_size = 2 * 1024 * 1024;
505	659	} else {
506		- ctrl->page_sizes = page_sizes;
	660	+ if (ctrl->nand_version >= 0x0304)
	661	+ ctrl->page_sizes = page_sizes_v3_4;
	662	+ else if (ctrl->nand_version >= 0x0202)
	663	+ ctrl->page_sizes = page_sizes_v2_2;
	664	+ else
	665	+ ctrl->page_sizes = page_sizes_v2_1;
	666	+
	667	+ if (ctrl->nand_version >= 0x0202)
	668	+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
	669	+ else
	670	+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
	671	+
507	672	if (ctrl->nand_version >= 0x0600)
508	673	ctrl->block_sizes = block_sizes_v6;
509		- else
	674	+ else if (ctrl->nand_version >= 0x0400)
510	675	ctrl->block_sizes = block_sizes_v4;
	676	+ else if (ctrl->nand_version >= 0x0202)
	677	+ ctrl->block_sizes = block_sizes_v2_2;
	678	+ else
	679	+ ctrl->block_sizes = block_sizes_v2_1;
511	680
512	681	if (ctrl->nand_version < 0x0400) {
513		- ctrl->max_page_size = 4096;
	682	+ if (ctrl->nand_version < 0x0202)
	683	+ ctrl->max_page_size = 2048;
	684	+ else
	685	+ ctrl->max_page_size = 4096;
514	686	ctrl->max_block_size = 512 * 1024;
515	687	}
516	688	}
517	689
518	690	/* Maximum spare area sector size (per 512B) */
519		- if (ctrl->nand_version >= 0x0702)
	691	+ if (ctrl->nand_version == 0x0702)
520	692	ctrl->max_oob = 128;
521	693	else if (ctrl->nand_version >= 0x0600)
522	694	ctrl->max_oob = 64;
..	..	@@ -545,6 +717,17 @@
545	717	ctrl->features \|= BRCMNAND_HAS_WP;
546	718
547	719	return 0;
	720	+}
	721	+
	722	+static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)
	723	+{
	724	+ /* flash_dma register offsets */
	725	+ if (ctrl->nand_version >= 0x0703)
	726	+ ctrl->flash_dma_offsets = flash_dma_regs_v4;
	727	+ else if (ctrl->nand_version == 0x0602)
	728	+ ctrl->flash_dma_offsets = flash_dma_regs_v0;
	729	+ else
	730	+ ctrl->flash_dma_offsets = flash_dma_regs_v1;
548	731	}
549	732
550	733	static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
..	..	@@ -587,6 +770,22 @@
587	770	int word, u32 val)
588	771	{
589	772	__raw_writel(val, ctrl->nand_fc + word * 4);
	773	+}
	774	+
	775	+static inline void edu_writel(struct brcmnand_controller *ctrl,
	776	+ enum edu_reg reg, u32 val)
	777	+{
	778	+ u16 offs = ctrl->edu_offsets[reg];
	779	+
	780	+ brcmnand_writel(val, ctrl->edu_base + offs);
	781	+}
	782	+
	783	+static inline u32 edu_readl(struct brcmnand_controller *ctrl,
	784	+ enum edu_reg reg)
	785	+{
	786	+ u16 offs = ctrl->edu_offsets[reg];
	787	+
	788	+ return brcmnand_readl(ctrl->edu_base + offs);
590	789	}
591	790
592	791	static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
..	..	@@ -669,7 +868,10 @@
669	868	enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
670	869	int cs = host->cs;
671	870
672		- if (ctrl->nand_version >= 0x0702)
	871	+ if (!ctrl->reg_offsets[reg])
	872	+ return;
	873	+
	874	+ if (ctrl->nand_version == 0x0702)
673	875	bits = 7;
674	876	else if (ctrl->nand_version >= 0x0600)
675	877	bits = 6;
..	..	@@ -723,12 +925,14 @@
723	925
724	926	static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
725	927	{
726		- if (ctrl->nand_version >= 0x0702)
	928	+ if (ctrl->nand_version == 0x0702)
727	929	return GENMASK(7, 0);
728	930	else if (ctrl->nand_version >= 0x0600)
729	931	return GENMASK(6, 0);
730		- else
	932	+ else if (ctrl->nand_version >= 0x0303)
731	933	return GENMASK(5, 0);
	934	+ else
	935	+ return GENMASK(4, 0);
732	936	}
733	937
734	938	#define NAND_ACC_CONTROL_ECC_SHIFT 16
..	..	@@ -853,23 +1057,33 @@
853	1057	* Flash DMA
854	1058	***********************************************************************/
855	1059
856		-enum flash_dma_reg {
857		- FLASH_DMA_REVISION = 0x00,
858		- FLASH_DMA_FIRST_DESC = 0x04,
859		- FLASH_DMA_FIRST_DESC_EXT = 0x08,
860		- FLASH_DMA_CTRL = 0x0c,
861		- FLASH_DMA_MODE = 0x10,
862		- FLASH_DMA_STATUS = 0x14,
863		- FLASH_DMA_INTERRUPT_DESC = 0x18,
864		- FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
865		- FLASH_DMA_ERROR_STATUS = 0x20,
866		- FLASH_DMA_CURRENT_DESC = 0x24,
867		- FLASH_DMA_CURRENT_DESC_EXT = 0x28,
868		-};
869		-
870	1060	static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
871	1061	{
872	1062	return ctrl->flash_dma_base;
	1063	+}
	1064	+
	1065	+static inline bool has_edu(struct brcmnand_controller *ctrl)
	1066	+{
	1067	+ return ctrl->edu_base;
	1068	+}
	1069	+
	1070	+static inline bool use_dma(struct brcmnand_controller *ctrl)
	1071	+{
	1072	+ return has_flash_dma(ctrl) \|\| has_edu(ctrl);
	1073	+}
	1074	+
	1075	+static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)
	1076	+{
	1077	+ if (ctrl->pio_poll_mode)
	1078	+ return;
	1079	+
	1080	+ if (has_flash_dma(ctrl)) {
	1081	+ ctrl->flash_dma_base = NULL;
	1082	+ disable_irq(ctrl->dma_irq);
	1083	+ }
	1084	+
	1085	+ disable_irq(ctrl->irq);
	1086	+ ctrl->pio_poll_mode = true;
873	1087	}
874	1088
875	1089	static inline bool flash_dma_buf_ok(const void *buf)
..	..	@@ -878,14 +1092,19 @@
878	1092	likely(IS_ALIGNED((uintptr_t)buf, 4));
879	1093	}
880	1094
881		-static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
882		- u32 val)
	1095	+static inline void flash_dma_writel(struct brcmnand_controller *ctrl,
	1096	+ enum flash_dma_reg dma_reg, u32 val)
883	1097	{
	1098	+ u16 offs = ctrl->flash_dma_offsets[dma_reg];
	1099	+
884	1100	brcmnand_writel(val, ctrl->flash_dma_base + offs);
885	1101	}
886	1102
887		-static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
	1103	+static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,
	1104	+ enum flash_dma_reg dma_reg)
888	1105	{
	1106	+ u16 offs = ctrl->flash_dma_offsets[dma_reg];
	1107	+
889	1108	return brcmnand_readl(ctrl->flash_dma_base + offs);
890	1109	}
891	1110
..	..	@@ -944,32 +1163,29 @@
944	1163	struct brcmnand_cfg *cfg = &host->hwcfg;
945	1164	int sas = cfg->spare_area_size << cfg->sector_size_1k;
946	1165	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
	1166	+ u32 next;
947	1167
948		- if (section >= sectors * 2)
	1168	+ if (section > sectors)
949	1169	return -ERANGE;
950	1170
951		- oobregion->offset = (section / 2) * sas;
	1171	+ next = (section * sas);
	1172	+ if (section < sectors)
	1173	+ next += 6;
952	1174
953		- if (section & 1) {
954		- oobregion->offset += 9;
955		- oobregion->length = 7;
	1175	+ if (section) {
	1176	+ oobregion->offset = ((section - 1) * sas) + 9;
956	1177	} else {
957		- oobregion->length = 6;
958		-
959		- /* First sector of each page may have BBI */
960		- if (!section) {
961		- /*
962		- * Small-page NAND use byte 6 for BBI while large-page
963		- * NAND use bytes 0 and 1.
964		- */
965		- if (cfg->page_size > 512) {
966		- oobregion->offset += 2;
967		- oobregion->length -= 2;
968		- } else {
969		- oobregion->length--;
970		- }
	1178	+ if (cfg->page_size > 512) {
	1179	+ /* Large page NAND uses first 2 bytes for BBI */
	1180	+ oobregion->offset = 2;
	1181	+ } else {
	1182	+ /* Small page NAND uses last byte before ECC for BBI */
	1183	+ oobregion->offset = 0;
	1184	+ next--;
971	1185	}
972	1186	}
	1187	+
	1188	+ oobregion->length = next - oobregion->offset;
973	1189
974	1190	return 0;
975	1191	}
..	..	@@ -991,7 +1207,7 @@
991	1207	if (section >= sectors)
992	1208	return -ERANGE;
993	1209
994		- oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
	1210	+ oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
995	1211	oobregion->length = chip->ecc.bytes;
996	1212
997	1213	return 0;
..	..	@@ -1229,6 +1445,52 @@
1229	1445	return tbytes;
1230	1446	}
1231	1447
	1448	+static void brcmnand_edu_init(struct brcmnand_controller *ctrl)
	1449	+{
	1450	+ /* initialize edu */
	1451	+ edu_writel(ctrl, EDU_ERR_STATUS, 0);
	1452	+ edu_readl(ctrl, EDU_ERR_STATUS);
	1453	+ edu_writel(ctrl, EDU_DONE, 0);
	1454	+ edu_writel(ctrl, EDU_DONE, 0);
	1455	+ edu_writel(ctrl, EDU_DONE, 0);
	1456	+ edu_writel(ctrl, EDU_DONE, 0);
	1457	+ edu_readl(ctrl, EDU_DONE);
	1458	+}
	1459	+
	1460	+/* edu irq */
	1461	+static irqreturn_t brcmnand_edu_irq(int irq, void *data)
	1462	+{
	1463	+ struct brcmnand_controller *ctrl = data;
	1464	+
	1465	+ if (ctrl->edu_count) {
	1466	+ ctrl->edu_count--;
	1467	+ while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK))
	1468	+ udelay(1);
	1469	+ edu_writel(ctrl, EDU_DONE, 0);
	1470	+ edu_readl(ctrl, EDU_DONE);
	1471	+ }
	1472	+
	1473	+ if (ctrl->edu_count) {
	1474	+ ctrl->edu_dram_addr += FC_BYTES;
	1475	+ ctrl->edu_ext_addr += FC_BYTES;
	1476	+
	1477	+ edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
	1478	+ edu_readl(ctrl, EDU_DRAM_ADDR);
	1479	+ edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
	1480	+ edu_readl(ctrl, EDU_EXT_ADDR);
	1481	+
	1482	+ mb(); /* flush previous writes */
	1483	+ edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
	1484	+ edu_readl(ctrl, EDU_CMD);
	1485	+
	1486	+ return IRQ_HANDLED;
	1487	+ }
	1488	+
	1489	+ complete(&ctrl->edu_done);
	1490	+
	1491	+ return IRQ_HANDLED;
	1492	+}
	1493	+
1232	1494	static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1233	1495	{
1234	1496	struct brcmnand_controller *ctrl = data;
..	..	@@ -1236,6 +1498,16 @@
1236	1498	/* Discard all NAND_CTLRDY interrupts during DMA */
1237	1499	if (ctrl->dma_pending)
1238	1500	return IRQ_HANDLED;
	1501	+
	1502	+ /* check if you need to piggy back on the ctrlrdy irq */
	1503	+ if (ctrl->edu_pending) {
	1504	+ if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0))
	1505	+ /* Discard interrupts while using dedicated edu irq */
	1506	+ return IRQ_HANDLED;
	1507	+
	1508	+ /* no registered edu irq, call handler */
	1509	+ return brcmnand_edu_irq(irq, data);
	1510	+ }
1239	1511
1240	1512	complete(&ctrl->done);
1241	1513	return IRQ_HANDLED;
..	..	@@ -1286,22 +1558,48 @@
1286	1558	* NAND MTD API: read/program/erase
1287	1559	***********************************************************************/
1288	1560
1289		-static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1290		- unsigned int ctrl)
	1561	+static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat,
	1562	+ unsigned int ctrl)
1291	1563	{
1292	1564	/* intentionally left blank */
1293	1565	}
1294	1566
1295		-static int brcmnand_waitfunc(struct mtd_info mtd, struct nand_chip this)
	1567	+static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)
1296	1568	{
1297		- struct nand_chip *chip = mtd_to_nand(mtd);
1298	1569	struct brcmnand_host *host = nand_get_controller_data(chip);
1299	1570	struct brcmnand_controller *ctrl = host->ctrl;
1300		- unsigned long timeo = msecs_to_jiffies(100);
	1571	+ struct mtd_info *mtd = nand_to_mtd(chip);
	1572	+ bool err = false;
	1573	+ int sts;
	1574	+
	1575	+ if (mtd->oops_panic_write) {
	1576	+ /* switch to interrupt polling and PIO mode */
	1577	+ disable_ctrl_irqs(ctrl);
	1578	+ sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
	1579	+ NAND_CTRL_RDY, 0);
	1580	+ err = (sts < 0) ? true : false;
	1581	+ } else {
	1582	+ unsigned long timeo = msecs_to_jiffies(
	1583	+ NAND_POLL_STATUS_TIMEOUT_MS);
	1584	+ /* wait for completion interrupt */
	1585	+ sts = wait_for_completion_timeout(&ctrl->done, timeo);
	1586	+ err = (sts <= 0) ? true : false;
	1587	+ }
	1588	+
	1589	+ return err;
	1590	+}
	1591	+
	1592	+static int brcmnand_waitfunc(struct nand_chip *chip)
	1593	+{
	1594	+ struct brcmnand_host *host = nand_get_controller_data(chip);
	1595	+ struct brcmnand_controller *ctrl = host->ctrl;
	1596	+ bool err = false;
1301	1597
1302	1598	dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1303		- if (ctrl->cmd_pending &&
1304		- wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
	1599	+ if (ctrl->cmd_pending)
	1600	+ err = brcmstb_nand_wait_for_completion(chip);
	1601	+
	1602	+ if (err) {
1305	1603	u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1306	1604	>> brcmnand_cmd_shift(ctrl);
1307	1605
..	..	@@ -1329,7 +1627,6 @@
1329	1627	enum brcmnand_llop_type type, u32 data,
1330	1628	bool last_op)
1331	1629	{
1332		- struct mtd_info *mtd = nand_to_mtd(&host->chip);
1333	1630	struct nand_chip *chip = &host->chip;
1334	1631	struct brcmnand_controller *ctrl = host->ctrl;
1335	1632	u32 tmp;
..	..	@@ -1362,13 +1659,13 @@
1362	1659	(void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1363	1660
1364	1661	brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1365		- return brcmnand_waitfunc(mtd, chip);
	1662	+ return brcmnand_waitfunc(chip);
1366	1663	}
1367	1664
1368		-static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
	1665	+static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command,
1369	1666	int column, int page_addr)
1370	1667	{
1371		- struct nand_chip *chip = mtd_to_nand(mtd);
	1668	+ struct mtd_info *mtd = nand_to_mtd(chip);
1372	1669	struct brcmnand_host *host = nand_get_controller_data(chip);
1373	1670	struct brcmnand_controller *ctrl = host->ctrl;
1374	1671	u64 addr = (u64)page_addr << chip->page_shift;
..	..	@@ -1433,7 +1730,7 @@
1433	1730
1434	1731	brcmnand_set_cmd_addr(mtd, addr);
1435	1732	brcmnand_send_cmd(host, native_cmd);
1436		- brcmnand_waitfunc(mtd, chip);
	1733	+ brcmnand_waitfunc(chip);
1437	1734
1438	1735	if (native_cmd == CMD_PARAMETER_READ \|\|
1439	1736	native_cmd == CMD_PARAMETER_CHANGE_COL) {
..	..	@@ -1467,9 +1764,8 @@
1467	1764	brcmnand_wp(mtd, 1);
1468	1765	}
1469	1766
1470		-static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
	1767	+static uint8_t brcmnand_read_byte(struct nand_chip *chip)
1471	1768	{
1472		- struct nand_chip *chip = mtd_to_nand(mtd);
1473	1769	struct brcmnand_host *host = nand_get_controller_data(chip);
1474	1770	struct brcmnand_controller *ctrl = host->ctrl;
1475	1771	uint8_t ret = 0;
..	..	@@ -1524,19 +1820,18 @@
1524	1820	return ret;
1525	1821	}
1526	1822
1527		-static void brcmnand_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	1823	+static void brcmnand_read_buf(struct nand_chip chip, uint8_t buf, int len)
1528	1824	{
1529	1825	int i;
1530	1826
1531	1827	for (i = 0; i < len; i++, buf++)
1532		- *buf = brcmnand_read_byte(mtd);
	1828	+ *buf = brcmnand_read_byte(chip);
1533	1829	}
1534	1830
1535		-static void brcmnand_write_buf(struct mtd_info mtd, const uint8_t buf,
1536		- int len)
	1831	+static void brcmnand_write_buf(struct nand_chip chip, const uint8_t buf,
	1832	+ int len)
1537	1833	{
1538	1834	int i;
1539		- struct nand_chip *chip = mtd_to_nand(mtd);
1540	1835	struct brcmnand_host *host = nand_get_controller_data(chip);
1541	1836
1542	1837	switch (host->last_cmd) {
..	..	@@ -1549,6 +1844,97 @@
1549	1844	BUG();
1550	1845	break;
1551	1846	}
	1847	+}
	1848	+
	1849	+/**
	1850	+ * Kick EDU engine
	1851	+ */
	1852	+static int brcmnand_edu_trans(struct brcmnand_host host, u64 addr, u32 buf,
	1853	+ u32 len, u8 cmd)
	1854	+{
	1855	+ struct brcmnand_controller *ctrl = host->ctrl;
	1856	+ unsigned long timeo = msecs_to_jiffies(200);
	1857	+ int ret = 0;
	1858	+ int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
	1859	+ u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE);
	1860	+ unsigned int trans = len >> FC_SHIFT;
	1861	+ dma_addr_t pa;
	1862	+
	1863	+ pa = dma_map_single(ctrl->dev, buf, len, dir);
	1864	+ if (dma_mapping_error(ctrl->dev, pa)) {
	1865	+ dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n");
	1866	+ return -ENOMEM;
	1867	+ }
	1868	+
	1869	+ ctrl->edu_pending = true;
	1870	+ ctrl->edu_dram_addr = pa;
	1871	+ ctrl->edu_ext_addr = addr;
	1872	+ ctrl->edu_cmd = edu_cmd;
	1873	+ ctrl->edu_count = trans;
	1874	+
	1875	+ edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);
	1876	+ edu_readl(ctrl, EDU_DRAM_ADDR);
	1877	+ edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);
	1878	+ edu_readl(ctrl, EDU_EXT_ADDR);
	1879	+ edu_writel(ctrl, EDU_LENGTH, FC_BYTES);
	1880	+ edu_readl(ctrl, EDU_LENGTH);
	1881	+
	1882	+ /* Start edu engine */
	1883	+ mb(); /* flush previous writes */
	1884	+ edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);
	1885	+ edu_readl(ctrl, EDU_CMD);
	1886	+
	1887	+ if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) {
	1888	+ dev_err(ctrl->dev,
	1889	+ "timeout waiting for EDU; status %#x, error status %#x\n",
	1890	+ edu_readl(ctrl, EDU_STATUS),
	1891	+ edu_readl(ctrl, EDU_ERR_STATUS));
	1892	+ }
	1893	+
	1894	+ dma_unmap_single(ctrl->dev, pa, len, dir);
	1895	+
	1896	+ /* for program page check NAND status */
	1897	+ if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
	1898	+ INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) &&
	1899	+ edu_cmd == EDU_CMD_WRITE) {
	1900	+ dev_info(ctrl->dev, "program failed at %llx\n",
	1901	+ (unsigned long long)addr);
	1902	+ ret = -EIO;
	1903	+ }
	1904	+
	1905	+ /* Make sure the EDU status is clean */
	1906	+ if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE)
	1907	+ dev_warn(ctrl->dev, "EDU still active: %#x\n",
	1908	+ edu_readl(ctrl, EDU_STATUS));
	1909	+
	1910	+ if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) {
	1911	+ dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n",
	1912	+ (unsigned long long)addr);
	1913	+ ret = -EIO;
	1914	+ }
	1915	+
	1916	+ ctrl->edu_pending = false;
	1917	+ brcmnand_edu_init(ctrl);
	1918	+ edu_writel(ctrl, EDU_STOP, 0); /* force stop */
	1919	+ edu_readl(ctrl, EDU_STOP);
	1920	+
	1921	+ if (!ret && edu_cmd == EDU_CMD_READ) {
	1922	+ u64 err_addr = 0;
	1923	+
	1924	+ /*
	1925	+ * check for ECC errors here, subpage ECC errors are
	1926	+ * retained in ECC error address register
	1927	+ */
	1928	+ err_addr = brcmnand_get_uncorrecc_addr(ctrl);
	1929	+ if (!err_addr) {
	1930	+ err_addr = brcmnand_get_correcc_addr(ctrl);
	1931	+ if (err_addr)
	1932	+ ret = -EUCLEAN;
	1933	+ } else
	1934	+ ret = -EBADMSG;
	1935	+ }
	1936	+
	1937	+ return ret;
1552	1938	}
1553	1939
1554	1940	/**
..	..	@@ -1594,8 +1980,11 @@
1594	1980
1595	1981	flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1596	1982	(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1597		- flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1598		- (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
	1983	+ if (ctrl->nand_version > 0x0602) {
	1984	+ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,
	1985	+ upper_32_bits(desc));
	1986	+ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
	1987	+ }
1599	1988
1600	1989	/* Start FLASH_DMA engine */
1601	1990	ctrl->dma_pending = true;
..	..	@@ -1657,7 +2046,7 @@
1657	2046	brcmnand_set_cmd_addr(mtd, addr);
1658	2047	/* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1659	2048	brcmnand_send_cmd(host, CMD_PAGE_READ);
1660		- brcmnand_waitfunc(mtd, chip);
	2049	+ brcmnand_waitfunc(chip);
1661	2050
1662	2051	if (likely(buf)) {
1663	2052	brcmnand_soc_data_bus_prepare(ctrl->soc, false);
..	..	@@ -1708,28 +2097,31 @@
1708	2097	static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1709	2098	struct nand_chip chip, void buf, u64 addr)
1710	2099	{
1711		- int i, sas;
1712		- void *oob = chip->oob_poi;
	2100	+ struct mtd_oob_region ecc;
	2101	+ int i;
1713	2102	int bitflips = 0;
1714	2103	int page = addr >> chip->page_shift;
1715	2104	int ret;
	2105	+ void *ecc_bytes;
	2106	+ void *ecc_chunk;
1716	2107
1717		- if (!buf) {
1718		- buf = chip->data_buf;
1719		- /* Invalidate page cache */
1720		- chip->pagebuf = -1;
1721		- }
1722		-
1723		- sas = mtd->oobsize / chip->ecc.steps;
	2108	+ if (!buf)
	2109	+ buf = nand_get_data_buf(chip);
1724	2110
1725	2111	/* read without ecc for verification */
1726		- ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
	2112	+ ret = chip->ecc.read_page_raw(chip, buf, true, page);
1727	2113	if (ret)
1728	2114	return ret;
1729	2115
1730		- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1731		- ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1732		- oob, sas, NULL, 0,
	2116	+ for (i = 0; i < chip->ecc.steps; i++) {
	2117	+ ecc_chunk = buf + chip->ecc.size * i;
	2118	+
	2119	+ mtd_ooblayout_ecc(mtd, i, &ecc);
	2120	+ ecc_bytes = chip->oob_poi + ecc.offset;
	2121	+
	2122	+ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
	2123	+ ecc_bytes, ecc.length,
	2124	+ NULL, 0,
1733	2125	chip->ecc.strength);
1734	2126	if (ret < 0)
1735	2127	return ret;
..	..	@@ -1748,21 +2140,28 @@
1748	2140	u64 err_addr = 0;
1749	2141	int err;
1750	2142	bool retry = true;
	2143	+ bool edu_err = false;
1751	2144
1752	2145	dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1753	2146
1754	2147	try_dmaread:
1755	2148	brcmnand_clear_ecc_addr(ctrl);
1756	2149
1757		- if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1758		- err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1759		- CMD_PAGE_READ);
	2150	+ if (ctrl->dma_trans && !oob && flash_dma_buf_ok(buf)) {
	2151	+ err = ctrl->dma_trans(host, addr, buf,
	2152	+ trans * FC_BYTES,
	2153	+ CMD_PAGE_READ);
	2154	+
1760	2155	if (err) {
1761	2156	if (mtd_is_bitflip_or_eccerr(err))
1762	2157	err_addr = addr;
1763	2158	else
1764	2159	return -EIO;
1765	2160	}
	2161	+
	2162	+ if (has_edu(ctrl) && err_addr)
	2163	+ edu_err = true;
	2164	+
1766	2165	} else {
1767	2166	if (oob)
1768	2167	memset(oob, 0x99, mtd->oobsize);
..	..	@@ -1810,6 +2209,11 @@
1810	2209	if (mtd_is_bitflip(err)) {
1811	2210	unsigned int corrected = brcmnand_count_corrected(ctrl);
1812	2211
	2212	+ /* in case of EDU correctable error we read again using PIO */
	2213	+ if (edu_err)
	2214	+ err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
	2215	+ oob, &err_addr);
	2216	+
1813	2217	dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1814	2218	(unsigned long long)err_addr);
1815	2219	mtd->ecc_stats.corrected += corrected;
..	..	@@ -1820,9 +2224,10 @@
1820	2224	return 0;
1821	2225	}
1822	2226
1823		-static int brcmnand_read_page(struct mtd_info mtd, struct nand_chip chip,
1824		- uint8_t *buf, int oob_required, int page)
	2227	+static int brcmnand_read_page(struct nand_chip chip, uint8_t buf,
	2228	+ int oob_required, int page)
1825	2229	{
	2230	+ struct mtd_info *mtd = nand_to_mtd(chip);
1826	2231	struct brcmnand_host *host = nand_get_controller_data(chip);
1827	2232	u8 oob = oob_required ? (u8 )chip->oob_poi : NULL;
1828	2233
..	..	@@ -1832,10 +2237,11 @@
1832	2237	mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1833	2238	}
1834	2239
1835		-static int brcmnand_read_page_raw(struct mtd_info mtd, struct nand_chip chip,
1836		- uint8_t *buf, int oob_required, int page)
	2240	+static int brcmnand_read_page_raw(struct nand_chip chip, uint8_t buf,
	2241	+ int oob_required, int page)
1837	2242	{
1838	2243	struct brcmnand_host *host = nand_get_controller_data(chip);
	2244	+ struct mtd_info *mtd = nand_to_mtd(chip);
1839	2245	u8 oob = oob_required ? (u8 )chip->oob_poi : NULL;
1840	2246	int ret;
1841	2247
..	..	@@ -1848,17 +2254,18 @@
1848	2254	return ret;
1849	2255	}
1850	2256
1851		-static int brcmnand_read_oob(struct mtd_info mtd, struct nand_chip chip,
1852		- int page)
	2257	+static int brcmnand_read_oob(struct nand_chip *chip, int page)
1853	2258	{
	2259	+ struct mtd_info *mtd = nand_to_mtd(chip);
	2260	+
1854	2261	return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1855	2262	mtd->writesize >> FC_SHIFT,
1856	2263	NULL, (u8 *)chip->oob_poi);
1857	2264	}
1858	2265
1859		-static int brcmnand_read_oob_raw(struct mtd_info mtd, struct nand_chip chip,
1860		- int page)
	2266	+static int brcmnand_read_oob_raw(struct nand_chip *chip, int page)
1861	2267	{
	2268	+ struct mtd_info *mtd = nand_to_mtd(chip);
1862	2269	struct brcmnand_host *host = nand_get_controller_data(chip);
1863	2270
1864	2271	brcmnand_set_ecc_enabled(host, 0);
..	..	@@ -1889,10 +2296,12 @@
1889	2296	for (i = 0; i < ctrl->max_oob; i += 4)
1890	2297	oob_reg_write(ctrl, i, 0xffffffff);
1891	2298
1892		- if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1893		- if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1894		- mtd->writesize, CMD_PROGRAM_PAGE))
	2299	+ if (use_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
	2300	+ if (ctrl->dma_trans(host, addr, (u32 *)buf, mtd->writesize,
	2301	+ CMD_PROGRAM_PAGE))
	2302	+
1895	2303	ret = -EIO;
	2304	+
1896	2305	goto out;
1897	2306	}
1898	2307
..	..	@@ -1920,7 +2329,7 @@
1920	2329
1921	2330	/* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1922	2331	brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1923		- status = brcmnand_waitfunc(mtd, chip);
	2332	+ status = brcmnand_waitfunc(chip);
1924	2333
1925	2334	if (status & NAND_STATUS_FAIL) {
1926	2335	dev_info(ctrl->dev, "program failed at %llx\n",
..	..	@@ -1934,9 +2343,10 @@
1934	2343	return ret;
1935	2344	}
1936	2345
1937		-static int brcmnand_write_page(struct mtd_info mtd, struct nand_chip chip,
1938		- const uint8_t *buf, int oob_required, int page)
	2346	+static int brcmnand_write_page(struct nand_chip chip, const uint8_t buf,
	2347	+ int oob_required, int page)
1939	2348	{
	2349	+ struct mtd_info *mtd = nand_to_mtd(chip);
1940	2350	struct brcmnand_host *host = nand_get_controller_data(chip);
1941	2351	void *oob = oob_required ? chip->oob_poi : NULL;
1942	2352
..	..	@@ -1946,10 +2356,10 @@
1946	2356	return nand_prog_page_end_op(chip);
1947	2357	}
1948	2358
1949		-static int brcmnand_write_page_raw(struct mtd_info *mtd,
1950		- struct nand_chip chip, const uint8_t buf,
	2359	+static int brcmnand_write_page_raw(struct nand_chip chip, const uint8_t buf,
1951	2360	int oob_required, int page)
1952	2361	{
	2362	+ struct mtd_info *mtd = nand_to_mtd(chip);
1953	2363	struct brcmnand_host *host = nand_get_controller_data(chip);
1954	2364	void *oob = oob_required ? chip->oob_poi : NULL;
1955	2365
..	..	@@ -1961,16 +2371,16 @@
1961	2371	return nand_prog_page_end_op(chip);
1962	2372	}
1963	2373
1964		-static int brcmnand_write_oob(struct mtd_info mtd, struct nand_chip chip,
1965		- int page)
	2374	+static int brcmnand_write_oob(struct nand_chip *chip, int page)
1966	2375	{
1967		- return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1968		- NULL, chip->oob_poi);
	2376	+ return brcmnand_write(nand_to_mtd(chip), chip,
	2377	+ (u64)page << chip->page_shift, NULL,
	2378	+ chip->oob_poi);
1969	2379	}
1970	2380
1971		-static int brcmnand_write_oob_raw(struct mtd_info mtd, struct nand_chip chip,
1972		- int page)
	2381	+static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)
1973	2382	{
	2383	+ struct mtd_info *mtd = nand_to_mtd(chip);
1974	2384	struct brcmnand_host *host = nand_get_controller_data(chip);
1975	2385	int ret;
1976	2386
..	..	@@ -2059,7 +2469,7 @@
2059	2469	(!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) \|
2060	2470	(device_size << CFG_DEVICE_SIZE_SHIFT);
2061	2471	if (cfg_offs == cfg_ext_offs) {
2062		- tmp \|= (page_size << CFG_PAGE_SIZE_SHIFT) \|
	2472	+ tmp \|= (page_size << ctrl->page_size_shift) \|
2063	2473	(block_size << CFG_BLK_SIZE_SHIFT);
2064	2474	nand_writereg(ctrl, cfg_offs, tmp);
2065	2475	} else {
..	..	@@ -2071,9 +2481,11 @@
2071	2481
2072	2482	tmp = nand_readreg(ctrl, acc_control_offs);
2073	2483	tmp &= ~brcmnand_ecc_level_mask(ctrl);
2074		- tmp \|= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2075	2484	tmp &= ~brcmnand_spare_area_mask(ctrl);
2076		- tmp \|= cfg->spare_area_size;
	2485	+ if (ctrl->nand_version >= 0x0302) {
	2486	+ tmp \|= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
	2487	+ tmp \|= cfg->spare_area_size;
	2488	+ }
2077	2489	nand_writereg(ctrl, acc_control_offs, tmp);
2078	2490
2079	2491	brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
..	..	@@ -2120,6 +2532,8 @@
2120	2532	{
2121	2533	struct mtd_info *mtd = nand_to_mtd(&host->chip);
2122	2534	struct nand_chip *chip = &host->chip;
	2535	+ const struct nand_ecc_props *requirements =
	2536	+ nanddev_get_ecc_requirements(&chip->base);
2123	2537	struct brcmnand_controller *ctrl = host->ctrl;
2124	2538	struct brcmnand_cfg *cfg = &host->hwcfg;
2125	2539	char msg[128];
..	..	@@ -2153,31 +2567,42 @@
2153	2567	cfg->col_adr_bytes = 2;
2154	2568	cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2155	2569
2156		- if (chip->ecc.mode != NAND_ECC_HW) {
	2570	+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
2157	2571	dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2158		- chip->ecc.mode);
	2572	+ chip->ecc.engine_type);
2159	2573	return -EINVAL;
2160	2574	}
2161	2575
2162		- if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
	2576	+ if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
2163	2577	if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2164	2578	/* Default to Hamming for 1-bit ECC, if unspecified */
2165		- chip->ecc.algo = NAND_ECC_HAMMING;
	2579	+ chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2166	2580	else
2167	2581	/* Otherwise, BCH */
2168		- chip->ecc.algo = NAND_ECC_BCH;
	2582	+ chip->ecc.algo = NAND_ECC_ALGO_BCH;
2169	2583	}
2170	2584
2171		- if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 \|\|
2172		- chip->ecc.size != 512)) {
	2585	+ if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
	2586	+ (chip->ecc.strength != 1 \|\| chip->ecc.size != 512)) {
2173	2587	dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2174	2588	chip->ecc.strength, chip->ecc.size);
2175	2589	return -EINVAL;
2176	2590	}
2177	2591
	2592	+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
	2593	+ (!chip->ecc.size \|\| !chip->ecc.strength)) {
	2594	+ if (requirements->step_size && requirements->strength) {
	2595	+ /* use detected ECC parameters */
	2596	+ chip->ecc.size = requirements->step_size;
	2597	+ chip->ecc.strength = requirements->strength;
	2598	+ dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n",
	2599	+ chip->ecc.size, chip->ecc.strength);
	2600	+ }
	2601	+ }
	2602	+
2178	2603	switch (chip->ecc.size) {
2179	2604	case 512:
2180		- if (chip->ecc.algo == NAND_ECC_HAMMING)
	2605	+ if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
2181	2606	cfg->ecc_level = 15;
2182	2607	else
2183	2608	cfg->ecc_level = chip->ecc.strength;
..	..	@@ -2248,7 +2673,7 @@
2248	2673	* to/from, and have nand_base pass us a bounce buffer instead, as
2249	2674	* needed.
2250	2675	*/
2251		- chip->options \|= NAND_USE_BOUNCE_BUFFER;
	2676	+ chip->options \|= NAND_USES_DMA;
2252	2677
2253	2678	if (chip->bbt_options & NAND_BBT_USE_FLASH)
2254	2679	chip->bbt_options \|= NAND_BBT_NO_OOB;
..	..	@@ -2304,17 +2729,14 @@
2304	2729	mtd->owner = THIS_MODULE;
2305	2730	mtd->dev.parent = &pdev->dev;
2306	2731
2307		- chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2308		- chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
	2732	+ chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
	2733	+ chip->legacy.cmdfunc = brcmnand_cmdfunc;
	2734	+ chip->legacy.waitfunc = brcmnand_waitfunc;
	2735	+ chip->legacy.read_byte = brcmnand_read_byte;
	2736	+ chip->legacy.read_buf = brcmnand_read_buf;
	2737	+ chip->legacy.write_buf = brcmnand_write_buf;
2309	2738
2310		- chip->cmd_ctrl = brcmnand_cmd_ctrl;
2311		- chip->cmdfunc = brcmnand_cmdfunc;
2312		- chip->waitfunc = brcmnand_waitfunc;
2313		- chip->read_byte = brcmnand_read_byte;
2314		- chip->read_buf = brcmnand_read_buf;
2315		- chip->write_buf = brcmnand_write_buf;
2316		-
2317		- chip->ecc.mode = NAND_ECC_HW;
	2739	+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2318	2740	chip->ecc.read_page = brcmnand_read_page;
2319	2741	chip->ecc.write_page = brcmnand_write_page;
2320	2742	chip->ecc.read_page_raw = brcmnand_read_page_raw;
..	..	@@ -2392,6 +2814,8 @@
2392	2814
2393	2815	if (has_flash_dma(ctrl))
2394	2816	ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
	2817	+ else if (has_edu(ctrl))
	2818	+ ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
2395	2819
2396	2820	return 0;
2397	2821	}
..	..	@@ -2404,6 +2828,13 @@
2404	2828	if (has_flash_dma(ctrl)) {
2405	2829	flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2406	2830	flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
	2831	+ }
	2832	+
	2833	+ if (has_edu(ctrl)) {
	2834	+ ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);
	2835	+ edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config);
	2836	+ edu_readl(ctrl, EDU_CONFIG);
	2837	+ brcmnand_edu_init(ctrl);
2407	2838	}
2408	2839
2409	2840	brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
..	..	@@ -2435,6 +2866,8 @@
2435	2866	EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2436	2867
2437	2868	static const struct of_device_id brcmnand_of_match[] = {
	2869	+ { .compatible = "brcm,brcmnand-v2.1" },
	2870	+ { .compatible = "brcm,brcmnand-v2.2" },
2438	2871	{ .compatible = "brcm,brcmnand-v4.0" },
2439	2872	{ .compatible = "brcm,brcmnand-v5.0" },
2440	2873	{ .compatible = "brcm,brcmnand-v6.0" },
..	..	@@ -2443,6 +2876,7 @@
2443	2876	{ .compatible = "brcm,brcmnand-v7.0" },
2444	2877	{ .compatible = "brcm,brcmnand-v7.1" },
2445	2878	{ .compatible = "brcm,brcmnand-v7.2" },
	2879	+ { .compatible = "brcm,brcmnand-v7.3" },
2446	2880	{},
2447	2881	};
2448	2882	MODULE_DEVICE_TABLE(of, brcmnand_of_match);
..	..	@@ -2450,6 +2884,49 @@
2450	2884	/***********************************************************************
2451	2885	* Platform driver setup (per controller)
2452	2886	***********************************************************************/
	2887	+static int brcmnand_edu_setup(struct platform_device *pdev)
	2888	+{
	2889	+ struct device *dev = &pdev->dev;
	2890	+ struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
	2891	+ struct resource *res;
	2892	+ int ret;
	2893	+
	2894	+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu");
	2895	+ if (res) {
	2896	+ ctrl->edu_base = devm_ioremap_resource(dev, res);
	2897	+ if (IS_ERR(ctrl->edu_base))
	2898	+ return PTR_ERR(ctrl->edu_base);
	2899	+
	2900	+ ctrl->edu_offsets = edu_regs;
	2901	+
	2902	+ edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND \|
	2903	+ EDU_CONFIG_SWAP_CFG);
	2904	+ edu_readl(ctrl, EDU_CONFIG);
	2905	+
	2906	+ /* initialize edu */
	2907	+ brcmnand_edu_init(ctrl);
	2908	+
	2909	+ ctrl->edu_irq = platform_get_irq_optional(pdev, 1);
	2910	+ if (ctrl->edu_irq < 0) {
	2911	+ dev_warn(dev,
	2912	+ "FLASH EDU enabled, using ctlrdy irq\n");
	2913	+ } else {
	2914	+ ret = devm_request_irq(dev, ctrl->edu_irq,
	2915	+ brcmnand_edu_irq, 0,
	2916	+ "brcmnand-edu", ctrl);
	2917	+ if (ret < 0) {
	2918	+ dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n",
	2919	+ ctrl->edu_irq, ret);
	2920	+ return ret;
	2921	+ }
	2922	+
	2923	+ dev_info(dev, "FLASH EDU enabled using irq %u\n",
	2924	+ ctrl->edu_irq);
	2925	+ }
	2926	+ }
	2927	+
	2928	+ return 0;
	2929	+}
2453	2930
2454	2931	int brcmnand_probe(struct platform_device pdev, struct brcmnand_soc soc)
2455	2932	{
..	..	@@ -2475,6 +2952,7 @@
2475	2952
2476	2953	init_completion(&ctrl->done);
2477	2954	init_completion(&ctrl->dma_done);
	2955	+ init_completion(&ctrl->edu_done);
2478	2956	nand_controller_init(&ctrl->controller);
2479	2957	ctrl->controller.ops = &brcmnand_controller_ops;
2480	2958	INIT_LIST_HEAD(&ctrl->host_list);
..	..	@@ -2529,7 +3007,21 @@
2529	3007	goto err;
2530	3008	}
2531	3009
2532		- flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
	3010	+ /* initialize the dma version */
	3011	+ brcmnand_flash_dma_revision_init(ctrl);
	3012	+
	3013	+ ret = -EIO;
	3014	+ if (ctrl->nand_version >= 0x0700)
	3015	+ ret = dma_set_mask_and_coherent(&pdev->dev,
	3016	+ DMA_BIT_MASK(40));
	3017	+ if (ret)
	3018	+ ret = dma_set_mask_and_coherent(&pdev->dev,
	3019	+ DMA_BIT_MASK(32));
	3020	+ if (ret)
	3021	+ goto err;
	3022	+
	3023	+ /* linked-list and stop on error */
	3024	+ flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);
2533	3025	flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2534	3026
2535	3027	/* Allocate descriptor(s) */
..	..	@@ -2558,6 +3050,16 @@
2558	3050	}
2559	3051
2560	3052	dev_info(dev, "enabling FLASH_DMA\n");
	3053	+ /* set flash dma transfer function to call */
	3054	+ ctrl->dma_trans = brcmnand_dma_trans;
	3055	+ } else {
	3056	+ ret = brcmnand_edu_setup(pdev);
	3057	+ if (ret < 0)
	3058	+ goto err;
	3059	+
	3060	+ if (has_edu(ctrl))
	3061	+ /* set edu transfer function to call */
	3062	+ ctrl->dma_trans = brcmnand_edu_trans;
2561	3063	}
2562	3064
2563	3065	/* Disable automatic device ID config, direct addressing */
..	..	@@ -2648,9 +3150,15 @@
2648	3150	{
2649	3151	struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2650	3152	struct brcmnand_host *host;
	3153	+ struct nand_chip *chip;
	3154	+ int ret;
2651	3155
2652		- list_for_each_entry(host, &ctrl->host_list, node)
2653		- nand_release(&host->chip);
	3156	+ list_for_each_entry(host, &ctrl->host_list, node) {
	3157	+ chip = &host->chip;
	3158	+ ret = mtd_device_unregister(nand_to_mtd(chip));
	3159	+ WARN_ON(ret);
	3160	+ nand_cleanup(chip);
	3161	+ }
2654	3162
2655	3163	clk_disable_unprepare(ctrl->clk);
2656	3164